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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GFX113; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX124 5define amdgpu_cs void @test_uniform_load_b96(ptr addrspace(1) %ptr, i32 %arg) "amdgpu-flat-work-group-size"="1,1" {6; GFX11-LABEL: test_uniform_load_b96:7; GFX11: ; %bb.0: ; %bb8; GFX11-NEXT: v_mov_b32_e32 v3, 09; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)10; GFX11-NEXT: v_lshlrev_b64 v[2:3], 2, v[2:3]11; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v0, v212; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)13; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo14; GFX11-NEXT: v_readfirstlane_b32 s0, v215; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)16; GFX11-NEXT: v_readfirstlane_b32 s1, v317; GFX11-NEXT: s_clause 0x118; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x019; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x820; GFX11-NEXT: s_waitcnt lgkmcnt(0)21; GFX11-NEXT: v_mov_b32_e32 v2, s322; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)23; GFX11-NEXT: v_or3_b32 v2, s2, v2, s024; GFX11-NEXT: global_store_b32 v[0:1], v2, off25; GFX11-NEXT: s_endpgm26;27; GFX12-LABEL: test_uniform_load_b96:28; GFX12: ; %bb.0: ; %bb29; GFX12-NEXT: v_mov_b32_e32 v3, 030; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)31; GFX12-NEXT: v_lshlrev_b64_e32 v[2:3], 2, v[2:3]32; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v233; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)34; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo35; GFX12-NEXT: v_readfirstlane_b32 s0, v236; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)37; GFX12-NEXT: v_readfirstlane_b32 s1, v338; GFX12-NEXT: s_load_b96 s[0:2], s[0:1], 0x039; GFX12-NEXT: s_wait_kmcnt 0x040; GFX12-NEXT: v_mov_b32_e32 v2, s041; GFX12-NEXT: v_or3_b32 v2, v2, s1, s242; GFX12-NEXT: global_store_b32 v[0:1], v2, off43; GFX12-NEXT: s_endpgm44bb:45 %i = zext i32 %arg to i6446 %i1 = getelementptr i32, ptr addrspace(1) %ptr, i64 %i47 %i2 = load <3 x i32>, ptr addrspace(1) %i1, align 448 %i3 = extractelement <3 x i32> %i2, i32 049 %i4 = extractelement <3 x i32> %i2, i32 150 %i5 = extractelement <3 x i32> %i2, i32 251 %i6 = or i32 %i3, %i452 %i7 = or i32 %i5, %i653 store i32 %i7, ptr addrspace(1) %ptr, align 454 ret void55}56