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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s5 6; Tests whether a load chain of 8 constants gets vectorized into a wider load.7define amdgpu_kernel void @constant_load_v8f32(ptr addrspace(4) noalias nocapture readonly %weights, ptr addrspace(1) noalias nocapture %out_ptr) {8; GFX6-LABEL: constant_load_v8f32:9; GFX6: ; %bb.0: ; %entry10; GFX6-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x911; GFX6-NEXT: s_waitcnt lgkmcnt(0)12; GFX6-NEXT: s_load_dword s16, s[10:11], 0x013; GFX6-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x014; GFX6-NEXT: s_mov_b32 s15, 0xf00015; GFX6-NEXT: s_mov_b32 s14, -116; GFX6-NEXT: s_mov_b32 s12, s1017; GFX6-NEXT: s_mov_b32 s13, s1118; GFX6-NEXT: s_waitcnt lgkmcnt(0)19; GFX6-NEXT: v_mov_b32_e32 v0, s1620; GFX6-NEXT: v_add_f32_e32 v0, s0, v021; GFX6-NEXT: v_add_f32_e32 v0, s1, v022; GFX6-NEXT: v_add_f32_e32 v0, s2, v023; GFX6-NEXT: v_add_f32_e32 v0, s3, v024; GFX6-NEXT: v_add_f32_e32 v0, s4, v025; GFX6-NEXT: v_add_f32_e32 v0, s5, v026; GFX6-NEXT: v_add_f32_e32 v0, s6, v027; GFX6-NEXT: v_add_f32_e32 v0, s7, v028; GFX6-NEXT: buffer_store_dword v0, off, s[12:15], 029; GFX6-NEXT: s_endpgm30;31; EG-LABEL: constant_load_v8f32:32; EG: ; %bb.0: ; %entry33; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]34; EG-NEXT: TEX 2 @635; EG-NEXT: ALU 9, @14, KC0[CB0:0-32], KC1[]36; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 137; EG-NEXT: CF_END38; EG-NEXT: PAD39; EG-NEXT: Fetch clause starting at 6:40; EG-NEXT: VTX_READ_128 T2.XYZW, T1.X, 0, #141; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #142; EG-NEXT: VTX_READ_128 T1.XYZW, T1.X, 16, #143; EG-NEXT: ALU clause starting at 12:44; EG-NEXT: MOV T0.X, KC0[2].Z,45; EG-NEXT: MOV * T1.X, KC0[2].Y,46; EG-NEXT: ALU clause starting at 14:47; EG-NEXT: ADD * T0.W, T2.X, T0.X,48; EG-NEXT: ADD * T0.W, T2.Y, PV.W,49; EG-NEXT: ADD * T0.W, T2.Z, PV.W,50; EG-NEXT: ADD * T0.W, T2.W, PV.W,51; EG-NEXT: ADD * T0.W, T1.X, PV.W,52; EG-NEXT: ADD * T0.W, T1.Y, PV.W,53; EG-NEXT: ADD * T0.W, T1.Z, PV.W,54; EG-NEXT: ADD T0.X, T1.W, PV.W,55; EG-NEXT: LSHR * T1.X, KC0[2].Z, literal.x,56; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)57;58; GFX12-LABEL: constant_load_v8f32:59; GFX12: ; %bb.0: ; %entry60; GFX12-NEXT: s_load_b128 s[8:11], s[4:5], 0x2461; GFX12-NEXT: s_wait_kmcnt 0x062; GFX12-NEXT: s_load_b32 s12, s[10:11], 0x063; GFX12-NEXT: s_load_b256 s[0:7], s[8:9], 0x064; GFX12-NEXT: s_wait_kmcnt 0x065; GFX12-NEXT: s_add_f32 s0, s0, s1266; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)67; GFX12-NEXT: s_add_f32 s0, s1, s068; GFX12-NEXT: s_add_f32 s0, s2, s069; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)70; GFX12-NEXT: s_add_f32 s0, s3, s071; GFX12-NEXT: s_add_f32 s0, s4, s072; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)73; GFX12-NEXT: s_add_f32 s0, s5, s074; GFX12-NEXT: s_add_f32 s0, s6, s075; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)76; GFX12-NEXT: s_add_f32 s0, s7, s077; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s078; GFX12-NEXT: global_store_b32 v0, v1, s[10:11]79; GFX12-NEXT: s_endpgm80entry:81 %out_ptr.promoted = load float, ptr addrspace(1) %out_ptr, align 482 %tmp = load float, ptr addrspace(4) %weights, align 483 %add = fadd float %tmp, %out_ptr.promoted84 %arrayidx.1 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 185 %tmp1 = load float, ptr addrspace(4) %arrayidx.1, align 486 %add.1 = fadd float %tmp1, %add87 %arrayidx.2 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 288 %tmp2 = load float, ptr addrspace(4) %arrayidx.2, align 489 %add.2 = fadd float %tmp2, %add.190 %arrayidx.3 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 391 %tmp3 = load float, ptr addrspace(4) %arrayidx.3, align 492 %add.3 = fadd float %tmp3, %add.293 %arrayidx.4 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 494 %tmp4 = load float, ptr addrspace(4) %arrayidx.4, align 495 %add.4 = fadd float %tmp4, %add.396 %arrayidx.5 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 597 %tmp5 = load float, ptr addrspace(4) %arrayidx.5, align 498 %add.5 = fadd float %tmp5, %add.499 %arrayidx.6 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 6100 %tmp6 = load float, ptr addrspace(4) %arrayidx.6, align 4101 %add.6 = fadd float %tmp6, %add.5102 %arrayidx.7 = getelementptr inbounds float, ptr addrspace(4) %weights, i64 7103 %tmp7 = load float, ptr addrspace(4) %arrayidx.7, align 4104 %add.7 = fadd float %tmp7, %add.6105 store float %add.7, ptr addrspace(1) %out_ptr, align 4106 ret void107}108