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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck %s3 4; Test that checks for redundant copies to temporary stack slot produced by5; expandUnalignedLoad.6 7define amdgpu_vs void @test(ptr addrspace(8) inreg %arg1, ptr addrspace(3) %arg2) {8; CHECK-LABEL: test:9; CHECK: ; %bb.0:10; CHECK-NEXT: v_add_i32_e32 v1, vcc, 12, v011; CHECK-NEXT: v_add_i32_e32 v2, vcc, 8, v012; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v013; CHECK-NEXT: s_mov_b32 m0, -114; CHECK-NEXT: ds_read_b32 v3, v115; CHECK-NEXT: ds_read_b32 v2, v216; CHECK-NEXT: ds_read_b32 v1, v417; CHECK-NEXT: ds_read_b32 v0, v018; CHECK-NEXT: s_waitcnt lgkmcnt(0)19; CHECK-NEXT: exp mrt0 off, off, off, off20; CHECK-NEXT: v_mov_b32_e32 v4, 021; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen22; CHECK-NEXT: s_endpgm23 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float poison, float poison, float poison, float poison, i1 false, i1 false)24 %var1 = load <6 x float>, ptr addrspace(3) %arg2, align 425 %var2 = shufflevector <6 x float> %var1, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>26 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %var2, ptr addrspace(8) %arg1, i32 0, i32 0, i32 0, i32 126, i32 0)27 ret void28}29 30define amdgpu_vs void @test_2(ptr addrspace(8) inreg %arg1, i32 %arg2, i32 inreg %arg3, ptr addrspace(3) %arg4) {31; CHECK-LABEL: test_2:32; CHECK: ; %bb.0:33; CHECK-NEXT: v_add_i32_e32 v3, vcc, 20, v134; CHECK-NEXT: v_add_i32_e32 v2, vcc, 16, v135; CHECK-NEXT: v_add_i32_e32 v4, vcc, 28, v136; CHECK-NEXT: v_add_i32_e32 v6, vcc, 24, v137; CHECK-NEXT: v_add_i32_e32 v7, vcc, 12, v138; CHECK-NEXT: v_add_i32_e32 v8, vcc, 8, v139; CHECK-NEXT: v_add_i32_e32 v10, vcc, 4, v140; CHECK-NEXT: s_mov_b32 m0, -141; CHECK-NEXT: ds_read_b32 v2, v242; CHECK-NEXT: ds_read_b32 v5, v443; CHECK-NEXT: ds_read_b32 v4, v644; CHECK-NEXT: ds_read_b32 v9, v745; CHECK-NEXT: ds_read_b32 v8, v846; CHECK-NEXT: ds_read_b32 v7, v1047; CHECK-NEXT: ds_read_b32 v6, v148; CHECK-NEXT: ds_read_b32 v3, v349; CHECK-NEXT: s_waitcnt lgkmcnt(1)50; CHECK-NEXT: tbuffer_store_format_xyzw v[6:9], v0, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc slc51; CHECK-NEXT: s_waitcnt lgkmcnt(0)52; CHECK-NEXT: tbuffer_store_format_xyzw v[2:5], v0, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:16 glc slc53; CHECK-NEXT: s_endpgm54 %load = load <8 x float>, ptr addrspace(3) %arg4, align 455 %vec1 = shufflevector <8 x float> %load, <8 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>56 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %vec1, ptr addrspace(8) %arg1, i32 %arg2, i32 0, i32 %arg3, i32 77, i32 3)57 %vec2 = shufflevector <8 x float> %load, <8 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>58 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %vec2, ptr addrspace(8) %arg1, i32 %arg2, i32 16, i32 %arg3, i32 77, i32 3)59 ret void60}61 62define amdgpu_vs void @test_3(i32 inreg %arg1, i32 inreg %arg2, ptr addrspace(8) inreg %arg3, i32 %arg4, ptr addrspace(3) %arg5, ptr addrspace(3) %arg6) {63; CHECK-LABEL: test_3:64; CHECK: ; %bb.0:65; CHECK-NEXT: s_mov_b32 s7, s566; CHECK-NEXT: s_mov_b32 s6, s467; CHECK-NEXT: s_mov_b32 s5, s368; CHECK-NEXT: s_mov_b32 s4, s269; CHECK-NEXT: v_add_i32_e32 v0, vcc, 12, v170; CHECK-NEXT: v_add_i32_e32 v3, vcc, 8, v171; CHECK-NEXT: v_add_i32_e32 v4, vcc, 4, v172; CHECK-NEXT: v_add_i32_e32 v7, vcc, 20, v173; CHECK-NEXT: v_add_i32_e32 v9, vcc, 16, v174; CHECK-NEXT: v_mov_b32_e32 v10, s075; CHECK-NEXT: v_add_i32_e32 v11, vcc, 12, v276; CHECK-NEXT: v_add_i32_e32 v12, vcc, 8, v277; CHECK-NEXT: s_mov_b32 m0, -178; CHECK-NEXT: ds_read_b32 v6, v079; CHECK-NEXT: ds_read_b32 v5, v380; CHECK-NEXT: ds_read_b32 v4, v481; CHECK-NEXT: ds_read_b32 v8, v782; CHECK-NEXT: ds_read_b32 v7, v983; CHECK-NEXT: ds_read_b32 v3, v184; CHECK-NEXT: v_add_i32_e32 v0, vcc, 4, v285; CHECK-NEXT: v_add_i32_e32 v1, vcc, 20, v286; CHECK-NEXT: v_add_i32_e32 v9, vcc, 16, v287; CHECK-NEXT: s_waitcnt lgkmcnt(0)88; CHECK-NEXT: tbuffer_store_format_xyzw v[3:6], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:264 glc slc89; CHECK-NEXT: tbuffer_store_format_xy v[7:8], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:280 glc slc90; CHECK-NEXT: s_waitcnt expcnt(1)91; CHECK-NEXT: ds_read_b32 v5, v1192; CHECK-NEXT: ds_read_b32 v4, v1293; CHECK-NEXT: ds_read_b32 v3, v094; CHECK-NEXT: ds_read_b32 v1, v195; CHECK-NEXT: ds_read_b32 v0, v996; CHECK-NEXT: ds_read_b32 v2, v297; CHECK-NEXT: s_waitcnt lgkmcnt(1)98; CHECK-NEXT: exp mrt0 off, off, off, off99; CHECK-NEXT: s_waitcnt lgkmcnt(0)100; CHECK-NEXT: tbuffer_store_format_xyzw v[2:5], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc101; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc102; CHECK-NEXT: s_endpgm103 %load1 = load <6 x float>, ptr addrspace(3) %arg5, align 4104 %vec11 = shufflevector <6 x float> %load1, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>105 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %vec11, ptr addrspace(8) %arg3, i32 %arg1, i32 264, i32 %arg2, i32 77, i32 3)106 %vec12 = shufflevector <6 x float> %load1, <6 x float> poison, <2 x i32> <i32 4, i32 5>107 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f32(<2 x float> %vec12, ptr addrspace(8) %arg3, i32 %arg1, i32 280, i32 %arg2, i32 64, i32 3)108 109 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float poison, float poison, float poison, float poison, i1 false, i1 false)110 111 %load2 = load <6 x float>, ptr addrspace(3) %arg6, align 4112 %vec21 = shufflevector <6 x float> %load2, <6 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>113 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %vec21, ptr addrspace(8) %arg3, i32 %arg1, i32 240, i32 %arg2, i32 77, i32 3)114 %vec22 = shufflevector <6 x float> %load2, <6 x float> poison, <2 x i32> <i32 4, i32 5>115 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f32(<2 x float> %vec22, ptr addrspace(8) %arg3, i32 %arg1, i32 256, i32 %arg2, i32 64, i32 3)116 117 ret void118}119 120declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32, i32 immarg, i32 immarg)121declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v2f32(<2 x float>, ptr addrspace(8), i32, i32, i32, i32 immarg, i32 immarg)122declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)123