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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SDAG %s3; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GISEL %s4 5define i32 @range_metadata_sext_i8_signed_range_i32(ptr addrspace(1) %ptr) {6; GCN-LABEL: range_metadata_sext_i8_signed_range_i32:7; GCN: ; %bb.0:8; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; GCN-NEXT: global_load_dword v0, v[0:1], off glc10; GCN-NEXT: s_waitcnt vmcnt(0)11; GCN-NEXT: s_setpc_b64 s[30:31]12 %val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !0, !noundef !{} ; [-127, 128)13 %shl = shl i32 %val, 2414 %ashr = ashr i32 %shl, 2415 ret i32 %ashr16}17 18define i32 @range_metadata_sext_upper_range_limited_i32(ptr addrspace(1) %ptr) {19; GCN-LABEL: range_metadata_sext_upper_range_limited_i32:20; GCN: ; %bb.0:21; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; GCN-NEXT: global_load_dword v0, v[0:1], off glc23; GCN-NEXT: s_waitcnt vmcnt(0)24; GCN-NEXT: v_bfe_i32 v0, v0, 0, 825; GCN-NEXT: s_setpc_b64 s[30:31]26 %val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !1, !noundef !{} ; [-127, 256)27 %shl = shl i32 %val, 2428 %ashr = ashr i32 %shl, 2429 ret i32 %ashr30}31 32define i32 @range_metadata_sext_lower_range_limited_i32(ptr addrspace(1) %ptr) {33; GCN-LABEL: range_metadata_sext_lower_range_limited_i32:34; GCN: ; %bb.0:35; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)36; GCN-NEXT: global_load_dword v0, v[0:1], off glc37; GCN-NEXT: s_waitcnt vmcnt(0)38; GCN-NEXT: v_bfe_i32 v0, v0, 0, 839; GCN-NEXT: s_setpc_b64 s[30:31]40 %val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !2 ; [-255, 128)41 %shl = shl i32 %val, 2442 %ashr = ashr i32 %shl, 2443 ret i32 %ashr44}45 46define i32 @range_metadata_sext_i8_neg_neg_range_i32(ptr addrspace(1) %ptr) {47; SDAG-LABEL: range_metadata_sext_i8_neg_neg_range_i32:48; SDAG: ; %bb.0:49; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; SDAG-NEXT: global_load_dword v0, v[0:1], off glc51; SDAG-NEXT: s_waitcnt vmcnt(0)52; SDAG-NEXT: v_and_b32_e32 v0, 63, v053; SDAG-NEXT: s_setpc_b64 s[30:31]54;55; GISEL-LABEL: range_metadata_sext_i8_neg_neg_range_i32:56; GISEL: ; %bb.0:57; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)58; GISEL-NEXT: global_load_dword v0, v[0:1], off glc59; GISEL-NEXT: s_waitcnt vmcnt(0)60; GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v061; GISEL-NEXT: s_setpc_b64 s[30:31]62 %val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !3, !noundef !{}63 %shl = shl i32 %val, 2564 %ashr = ashr i32 %shl, 2565 ret i32 %ashr66}67 68define i32 @range_metadata_sextload_i8_signed_range_i4_i32(ptr addrspace(1) %ptr) {69; GCN-LABEL: range_metadata_sextload_i8_signed_range_i4_i32:70; GCN: ; %bb.0:71; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)72; GCN-NEXT: global_load_sbyte v0, v[0:1], off glc73; GCN-NEXT: s_waitcnt vmcnt(0)74; GCN-NEXT: s_setpc_b64 s[30:31]75 %load = load volatile i8, ptr addrspace(1) %ptr, align 1, !range !4, !noundef !{}76 %shl = shl i8 %load, 377 %ashr = ashr i8 %shl, 378 %ext = sext i8 %ashr to i3279 ret i32 %ext80}81 82define i25 @range_metadata_sext_i8_signed_range_i25(ptr addrspace(1) %ptr) {83; GCN-LABEL: range_metadata_sext_i8_signed_range_i25:84; GCN: ; %bb.0:85; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)86; GCN-NEXT: global_load_dword v0, v[0:1], off glc87; GCN-NEXT: s_waitcnt vmcnt(0)88; GCN-NEXT: v_bfe_i32 v0, v0, 0, 289; GCN-NEXT: s_setpc_b64 s[30:31]90 %val = load volatile i25, ptr addrspace(1) %ptr, align 4, !range !5, !noundef !{}91 %shl = shl i25 %val, 2392 %ashr = ashr i25 %shl, 2393 ret i25 %ashr94}95 96define i32 @range_metadata_i32_neg1_to_1(ptr addrspace(1) %ptr) {97; GCN-LABEL: range_metadata_i32_neg1_to_1:98; GCN: ; %bb.0:99; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)100; GCN-NEXT: global_load_dword v0, v[0:1], off glc101; GCN-NEXT: s_waitcnt vmcnt(0)102; GCN-NEXT: s_setpc_b64 s[30:31]103 %val = load volatile i32, ptr addrspace(1) %ptr, align 4, !range !6, !noundef !{}104 %shl = shl i32 %val, 31105 %ashr = ashr i32 %shl, 31106 ret i32 %ashr107}108 109define i64 @range_metadata_sext_i8_signed_range_i64(ptr addrspace(1) %ptr) {110; SDAG-LABEL: range_metadata_sext_i8_signed_range_i64:111; SDAG: ; %bb.0:112; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; SDAG-NEXT: global_load_dwordx2 v[1:2], v[0:1], off glc114; SDAG-NEXT: s_waitcnt vmcnt(0)115; SDAG-NEXT: v_bfe_i32 v0, v1, 0, 9116; SDAG-NEXT: v_bfe_i32 v1, v1, 8, 1117; SDAG-NEXT: s_setpc_b64 s[30:31]118;119; GISEL-LABEL: range_metadata_sext_i8_signed_range_i64:120; GISEL: ; %bb.0:121; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; GISEL-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc123; GISEL-NEXT: s_waitcnt vmcnt(0)124; GISEL-NEXT: v_bfe_i32 v0, v0, 0, 9125; GISEL-NEXT: v_ashrrev_i32_e32 v1, 31, v0126; GISEL-NEXT: s_setpc_b64 s[30:31]127 %val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !7, !noundef !{}128 %shl = shl i64 %val, 55129 %ashr = ashr i64 %shl, 55130 ret i64 %ashr131}132 133define i64 @range_metadata_sext_i32_signed_range_i64(ptr addrspace(1) %ptr) {134; GCN-LABEL: range_metadata_sext_i32_signed_range_i64:135; GCN: ; %bb.0:136; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)137; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc138; GCN-NEXT: s_waitcnt vmcnt(0)139; GCN-NEXT: s_setpc_b64 s[30:31]140 %val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !7, !noundef !{}141 %shl = shl i64 %val, 31142 %ashr = ashr i64 %shl, 31143 ret i64 %ashr144}145 146define i64 @range_metadata_sext_i33_signed_range_i64(ptr addrspace(1) %ptr) {147; GCN-LABEL: range_metadata_sext_i33_signed_range_i64:148; GCN: ; %bb.0:149; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)150; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc151; GCN-NEXT: s_waitcnt vmcnt(0)152; GCN-NEXT: s_setpc_b64 s[30:31]153 %val = load volatile i64, ptr addrspace(1) %ptr, align 4, !range !8, !noundef !{}154 %shl = shl i64 %val, 30155 %ashr = ashr i64 %shl, 30156 ret i64 %ashr157}158 159!0 = !{i32 -127, i32 128}160!1 = !{i32 -127, i32 256}161!2 = !{i32 -255, i32 128}162!3 = !{i32 -127, i32 -64}163!4 = !{i8 -15, i8 16}164!5 = !{i25 -127, i25 128}165!6 = !{i32 -1, i32 1}166!7 = !{i64 -4294967295, i64 4294967296}167!8 = !{i64 -8589934591, i64 8589934592}168