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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s3 4; Combine on select c, (load x), (load y) -> load (select c, x, y)5; drops MachinePointerInfo, so it can't be relied on for correctness.6 7define amdgpu_kernel void @select_ptr_crash_i64_flat(i32 %tmp, [8 x i32], ptr %ptr0, [8 x i32], ptr %ptr1, [8 x i32], ptr addrspace(1) %ptr2) {8; GCN-LABEL: select_ptr_crash_i64_flat:9; GCN: ; %bb.0:10; GCN-NEXT: s_add_i32 s12, s12, s1711; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 812; GCN-NEXT: s_load_dword s2, s[8:9], 0x013; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x7814; GCN-NEXT: s_add_u32 s4, s8, 4015; GCN-NEXT: s_addc_u32 s3, s9, 016; GCN-NEXT: s_add_u32 s5, s8, 0x5017; GCN-NEXT: s_addc_u32 s6, s9, 018; GCN-NEXT: s_waitcnt lgkmcnt(0)19; GCN-NEXT: s_cmp_eq_u32 s2, 020; GCN-NEXT: s_cselect_b32 s3, s3, s621; GCN-NEXT: s_cselect_b32 s2, s4, s522; GCN-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x023; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1324; GCN-NEXT: s_waitcnt lgkmcnt(0)25; GCN-NEXT: v_mov_b32_e32 v0, s226; GCN-NEXT: v_mov_b32_e32 v1, s327; GCN-NEXT: s_add_u32 s2, s2, 428; GCN-NEXT: flat_load_dword v0, v[0:1]29; GCN-NEXT: s_addc_u32 s3, s3, 030; GCN-NEXT: v_mov_b32_e32 v1, s231; GCN-NEXT: v_mov_b32_e32 v2, s332; GCN-NEXT: flat_load_dword v1, v[1:2]33; GCN-NEXT: v_mov_b32_e32 v3, s134; GCN-NEXT: v_mov_b32_e32 v2, s035; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)36; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]37; GCN-NEXT: s_endpgm38 %tmp2 = icmp eq i32 %tmp, 039 %tmp3 = load i64, ptr %ptr0, align 840 %tmp4 = load i64, ptr %ptr1, align 841 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp442 store i64 %tmp5, ptr addrspace(1) %ptr2, align 843 ret void44}45 46; The transform currently doesn't happen for non-addrspace 0, but it47; should.48 49define amdgpu_kernel void @select_ptr_crash_i64_global(i32 %tmp, [8 x i32], ptr addrspace(1) %ptr0, [8 x i32], ptr addrspace(1) %ptr1, [8 x i32], ptr addrspace(1) %ptr2) {50; GCN-LABEL: select_ptr_crash_i64_global:51; GCN: ; %bb.0:52; GCN-NEXT: s_add_i32 s12, s12, s1753; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 854; GCN-NEXT: s_load_dword s2, s[8:9], 0x055; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x7856; GCN-NEXT: s_add_u32 s4, s8, 4057; GCN-NEXT: s_addc_u32 s3, s9, 058; GCN-NEXT: s_add_u32 s5, s8, 0x5059; GCN-NEXT: s_addc_u32 s6, s9, 060; GCN-NEXT: s_waitcnt lgkmcnt(0)61; GCN-NEXT: s_cmp_eq_u32 s2, 062; GCN-NEXT: s_cselect_b32 s3, s3, s663; GCN-NEXT: s_cselect_b32 s2, s4, s564; GCN-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x065; GCN-NEXT: v_mov_b32_e32 v0, s066; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1367; GCN-NEXT: v_mov_b32_e32 v1, s168; GCN-NEXT: s_waitcnt lgkmcnt(0)69; GCN-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x070; GCN-NEXT: s_waitcnt lgkmcnt(0)71; GCN-NEXT: v_mov_b32_e32 v2, s272; GCN-NEXT: v_mov_b32_e32 v3, s373; GCN-NEXT: flat_store_dwordx2 v[0:1], v[2:3]74; GCN-NEXT: s_endpgm75 %tmp2 = icmp eq i32 %tmp, 076 %tmp3 = load i64, ptr addrspace(1) %ptr0, align 877 %tmp4 = load i64, ptr addrspace(1) %ptr1, align 878 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp479 store i64 %tmp5, ptr addrspace(1) %ptr2, align 880 ret void81}82 83define amdgpu_kernel void @select_ptr_crash_i64_local(i32 %tmp, ptr addrspace(3) %ptr0, ptr addrspace(3) %ptr1, ptr addrspace(1) %ptr2) {84; GCN-LABEL: select_ptr_crash_i64_local:85; GCN: ; %bb.0:86; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x087; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x1088; GCN-NEXT: s_add_i32 s12, s12, s1789; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 890; GCN-NEXT: s_mov_b32 m0, -191; GCN-NEXT: s_waitcnt lgkmcnt(0)92; GCN-NEXT: s_cmp_eq_u32 s0, 093; GCN-NEXT: s_cselect_b32 s0, s1, s294; GCN-NEXT: v_mov_b32_e32 v0, s095; GCN-NEXT: ds_read_b64 v[0:1], v096; GCN-NEXT: v_mov_b32_e32 v2, s497; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1398; GCN-NEXT: v_mov_b32_e32 v3, s599; GCN-NEXT: s_waitcnt lgkmcnt(0)100; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]101; GCN-NEXT: s_endpgm102 %tmp2 = icmp eq i32 %tmp, 0103 %tmp3 = load i64, ptr addrspace(3) %ptr0, align 8104 %tmp4 = load i64, ptr addrspace(3) %ptr1, align 8105 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4106 store i64 %tmp5, ptr addrspace(1) %ptr2, align 8107 ret void108}109 110; The transform will break addressing mode matching, so unclear it111; would be good to do112 113define amdgpu_kernel void @select_ptr_crash_i64_local_offsets(i32 %tmp, ptr addrspace(3) %ptr0, ptr addrspace(3) %ptr1, ptr addrspace(1) %ptr2) {114; GCN-LABEL: select_ptr_crash_i64_local_offsets:115; GCN: ; %bb.0:116; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0117; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10118; GCN-NEXT: s_add_i32 s12, s12, s17119; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8120; GCN-NEXT: s_mov_b32 m0, -1121; GCN-NEXT: s_waitcnt lgkmcnt(0)122; GCN-NEXT: s_addk_i32 s1, 0x80123; GCN-NEXT: s_addk_i32 s2, 0x200124; GCN-NEXT: s_cmp_eq_u32 s0, 0125; GCN-NEXT: s_cselect_b32 s0, s1, s2126; GCN-NEXT: v_mov_b32_e32 v0, s0127; GCN-NEXT: ds_read_b64 v[0:1], v0128; GCN-NEXT: v_mov_b32_e32 v2, s4129; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13130; GCN-NEXT: v_mov_b32_e32 v3, s5131; GCN-NEXT: s_waitcnt lgkmcnt(0)132; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]133; GCN-NEXT: s_endpgm134 %tmp2 = icmp eq i32 %tmp, 0135 %gep0 = getelementptr inbounds i64, ptr addrspace(3) %ptr0, i64 16136 %gep1 = getelementptr inbounds i64, ptr addrspace(3) %ptr1, i64 64137 %tmp3 = load i64, ptr addrspace(3) %gep0, align 8138 %tmp4 = load i64, ptr addrspace(3) %gep1, align 8139 %tmp5 = select i1 %tmp2, i64 %tmp3, i64 %tmp4140 store i64 %tmp5, ptr addrspace(1) %ptr2, align 8141 ret void142}143 144; The resultant load cannot be treated as uniform145define amdgpu_kernel void @sample_test(ptr addrspace(1) %dest, ptr addrspace(1) %sourceA, ptr addrspace(1) %sourceB, i1 %tobool.not.i) #0 {146; GCN-LABEL: sample_test:147; GCN: ; %bb.0: ; %entry148; GCN-NEXT: s_load_dword s6, s[4:5], 0x18149; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0150; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x10151; GCN-NEXT: v_lshlrev_b32_e32 v2, 3, v0152; GCN-NEXT: s_waitcnt lgkmcnt(0)153; GCN-NEXT: s_bitcmp1_b32 s6, 0154; GCN-NEXT: v_mov_b32_e32 v0, s3155; GCN-NEXT: v_add_u32_e32 v3, vcc, s2, v2156; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc157; GCN-NEXT: v_mov_b32_e32 v1, s5158; GCN-NEXT: s_cselect_b64 vcc, -1, 0159; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc160; GCN-NEXT: v_mov_b32_e32 v0, s4161; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc162; GCN-NEXT: flat_load_dwordx2 v[0:1], v[0:1]163; GCN-NEXT: v_mov_b32_e32 v3, s1164; GCN-NEXT: v_add_u32_e32 v2, vcc, s0, v2165; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc166; GCN-NEXT: s_waitcnt vmcnt(0)167; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]168; GCN-NEXT: s_endpgm169entry:170 %0 = tail call i32 @llvm.amdgcn.workitem.id.x()171 %conv2.i.i.i1 = zext i32 %0 to i64172 %arrayidx.i = getelementptr i64, ptr addrspace(1) %sourceA, i64 %conv2.i.i.i1173 %dest.gep = getelementptr i64, ptr addrspace(1) %dest, i64 %conv2.i.i.i1174 %ld0 = load i64, ptr addrspace(1) %arrayidx.i, align 8, !amdgpu.noclobber !0175 %ld1 = load i64, ptr addrspace(1) %sourceB, align 8176 %cond.i = select i1 %tobool.not.i, i64 %ld0, i64 %ld1177 store i64 %cond.i, ptr addrspace(1) %dest.gep, align 8178 ret void179}180 181; The resultant load cannot be treated as uniform182define amdgpu_kernel void @constant_is_not_uniform(ptr addrspace(1) %dest, ptr addrspace(4) %sourceA, ptr addrspace(4) %sourceB, i1 %tobool.not.i) #0 {183; GCN-LABEL: constant_is_not_uniform:184; GCN: ; %bb.0: ; %entry185; GCN-NEXT: s_load_dword s6, s[4:5], 0x18186; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0187; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x10188; GCN-NEXT: v_lshlrev_b32_e32 v2, 3, v0189; GCN-NEXT: s_waitcnt lgkmcnt(0)190; GCN-NEXT: s_bitcmp1_b32 s6, 0191; GCN-NEXT: v_mov_b32_e32 v0, s3192; GCN-NEXT: v_add_u32_e32 v3, vcc, s2, v2193; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc194; GCN-NEXT: v_mov_b32_e32 v1, s5195; GCN-NEXT: s_cselect_b64 vcc, -1, 0196; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc197; GCN-NEXT: v_mov_b32_e32 v0, s4198; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc199; GCN-NEXT: flat_load_dwordx2 v[0:1], v[0:1]200; GCN-NEXT: v_mov_b32_e32 v3, s1201; GCN-NEXT: v_add_u32_e32 v2, vcc, s0, v2202; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc203; GCN-NEXT: s_waitcnt vmcnt(0)204; GCN-NEXT: flat_store_dwordx2 v[2:3], v[0:1]205; GCN-NEXT: s_endpgm206entry:207 %0 = tail call i32 @llvm.amdgcn.workitem.id.x()208 %conv2.i.i.i1 = zext i32 %0 to i64209 %arrayidx.i = getelementptr i64, ptr addrspace(4) %sourceA, i64 %conv2.i.i.i1210 %dest.gep = getelementptr i64, ptr addrspace(1) %dest, i64 %conv2.i.i.i1211 %ld0 = load i64, ptr addrspace(4) %arrayidx.i, align 8212 %ld1 = load i64, ptr addrspace(4) %sourceB, align 8213 %cond.i = select i1 %tobool.not.i, i64 %ld0, i64 %ld1214 store i64 %cond.i, ptr addrspace(1) %dest.gep, align 8215 ret void216}217 218attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }219 220!0 = !{}221