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1# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s2# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -passes=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck %s3 4# The purpose of this test is to make sure we are combining relevant memory5# operations correctly with/without SCC bit.6 7--- |8 define amdgpu_kernel void @test1(ptr addrspace(1) %out) {9 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 110 store i32 123, ptr addrspace(1) %out.gep.111 store i32 456, ptr addrspace(1) %out12 ret void13 }14 15 define amdgpu_kernel void @test2(ptr addrspace(1) %out) {16 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 117 store i32 123, ptr addrspace(1) %out.gep.118 store i32 456, ptr addrspace(1) %out19 ret void20 }21 22 define amdgpu_kernel void @test3(ptr addrspace(1) %out) {23 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 124 store i32 123, ptr addrspace(1) %out.gep.125 store i32 456, ptr addrspace(1) %out26 ret void27 }28 define amdgpu_kernel void @test4(ptr addrspace(1) %out) {29 %out.gep.1 = getelementptr i32, ptr addrspace(1) %out, i32 130 store i32 123, ptr addrspace(1) %out.gep.131 store i32 456, ptr addrspace(1) %out32 ret void33 }34...35 36# CHECK: BUFFER_STORE_DWORDX2_OFFSET killed %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 0, 0, implicit $exec :: (store (s64) into %ir.out.gep.1, align 4, addrspace 1)37---38name: test139liveins:40 - { reg: '$sgpr0_sgpr1', virtual-reg: '' }41body: |42 bb.0 (%ir-block.0):43 liveins: $sgpr0_sgpr144 45 $vgpr0 = V_MOV_B32_e32 123, implicit $exec46 $vgpr1 = V_MOV_B32_e32 456, implicit $exec47 48 $sgpr2 = S_MOV_B32 -149 $sgpr3 = S_MOV_B32 6144050 51 %0:sgpr_64 = COPY $sgpr0_sgpr152 %1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) poison`, addrspace 4)53 %2:sgpr_32 = COPY $sgpr254 %3:sgpr_32 = COPY $sgpr355 %4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub256 57 %5:vgpr_32 = COPY $vgpr058 %6:vgpr_32 = COPY $vgpr159 60 BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)61 BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)62 63 S_ENDPGM 064...65 66# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)67# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)68---69name: test270liveins:71 - { reg: '$sgpr0_sgpr1', virtual-reg: '' }72body: |73 bb.0 (%ir-block.0):74 liveins: $sgpr0_sgpr175 76 $vgpr0 = V_MOV_B32_e32 123, implicit $exec77 $vgpr1 = V_MOV_B32_e32 456, implicit $exec78 79 $sgpr2 = S_MOV_B32 -180 $sgpr3 = S_MOV_B32 6144081 82 %0:sgpr_64 = COPY $sgpr0_sgpr183 %1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) poison`, addrspace 4)84 %2:sgpr_32 = COPY $sgpr285 %3:sgpr_32 = COPY $sgpr386 %4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub287 88 %5:vgpr_32 = COPY $vgpr089 %6:vgpr_32 = COPY $vgpr190 91 BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)92 BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)93 94 S_ENDPGM 095...96 97# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)98# CHECK: BUFFER_STORE_DWORD_OFFSET %{{[0-9]+}}, %{{[0-9]+}}, 0, 8, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)99---100name: test3101liveins:102 - { reg: '$sgpr0_sgpr1', virtual-reg: '' }103body: |104 bb.0 (%ir-block.0):105 liveins: $sgpr0_sgpr1106 107 $vgpr0 = V_MOV_B32_e32 123, implicit $exec108 $vgpr1 = V_MOV_B32_e32 456, implicit $exec109 110 $sgpr2 = S_MOV_B32 -1111 $sgpr3 = S_MOV_B32 61440112 113 %0:sgpr_64 = COPY $sgpr0_sgpr1114 %1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) poison`, addrspace 4)115 %2:sgpr_32 = COPY $sgpr2116 %3:sgpr_32 = COPY $sgpr3117 %4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub2118 119 %5:vgpr_32 = COPY $vgpr0120 %6:vgpr_32 = COPY $vgpr1121 122 BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 0, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)123 BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)124 125 S_ENDPGM 0126...127 128# CHECK: BUFFER_STORE_DWORDX2_OFFSET killed %{{[0-9]+}}, %{{[0-9]+}}, 0, 4, 16, 0, implicit $exec :: (store (s64) into %ir.out.gep.1, align 4, addrspace 1)129---130name: test4131liveins:132 - { reg: '$sgpr0_sgpr1', virtual-reg: '' }133body: |134 bb.0 (%ir-block.0):135 liveins: $sgpr0_sgpr1136 137 $vgpr0 = V_MOV_B32_e32 123, implicit $exec138 $vgpr1 = V_MOV_B32_e32 456, implicit $exec139 140 $sgpr2 = S_MOV_B32 -1141 $sgpr3 = S_MOV_B32 61440142 143 %0:sgpr_64 = COPY $sgpr0_sgpr1144 %1:sgpr_64 = S_LOAD_DWORDX2_IMM %1, 36, 0 :: (dereferenceable invariant load (s64) from `ptr addrspace(4) poison`, addrspace 4)145 %2:sgpr_32 = COPY $sgpr2146 %3:sgpr_32 = COPY $sgpr3147 %4:sgpr_128 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1, %3, %subreg.sub2148 149 %5:vgpr_32 = COPY $vgpr0150 %6:vgpr_32 = COPY $vgpr1151 152 BUFFER_STORE_DWORD_OFFSET %5, %4, 0, 4, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)153 BUFFER_STORE_DWORD_OFFSET %6, %4, 0, 8, 16, 0, implicit $exec :: (store (s32) into %ir.out.gep.1, addrspace 1)154 155 S_ENDPGM 0156...157