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1; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SICIVI %s2; RUN: llc -mtriple=amdgcn -mcpu=bonaire < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,SICIVI,CIPLUS %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,SICIVI,CIPLUS %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,CIPLUS %s5 6; GCN-LABEL: {{^}}local_i32_load7; SICIVI: s_mov_b32 m08; GFX9-NOT: m09 10; GCN: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:2811; GCN: buffer_store_dword [[REG]],12define amdgpu_kernel void @local_i32_load(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {13 %gep = getelementptr i32, ptr addrspace(3) %in, i32 714 %val = load i32, ptr addrspace(3) %gep, align 415 store i32 %val, ptr addrspace(1) %out, align 416 ret void17}18 19; GCN-LABEL: {{^}}local_i32_load_0_offset20; SICIVI: s_mov_b32 m021; GFX9-NOT: m022 23; GCN: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}}24; GCN: buffer_store_dword [[REG]],25define amdgpu_kernel void @local_i32_load_0_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {26 %val = load i32, ptr addrspace(3) %in, align 427 store i32 %val, ptr addrspace(1) %out, align 428 ret void29}30 31; GCN-LABEL: {{^}}local_i8_load_i16_max_offset:32; SICIVI: s_mov_b32 m033; GFX9-NOT: m034 35; GCN-NOT: add36; GCN: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:6553537; GCN: buffer_store_byte [[REG]],38define amdgpu_kernel void @local_i8_load_i16_max_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {39 %gep = getelementptr i8, ptr addrspace(3) %in, i32 6553540 %val = load i8, ptr addrspace(3) %gep, align 441 store i8 %val, ptr addrspace(1) %out, align 442 ret void43}44 45; GCN-LABEL: {{^}}local_i8_load_over_i16_max_offset:46; SICIVI-DAG: s_mov_b32 m047; GFX9-NOT: m048 49; The LDS offset will be 65536 bytes, which is larger than the size of LDS on50; SI, which is why it is being OR'd with the base pointer.51; SI-DAG: s_bitset1_b32 [[ADDR:s[0-9]+]], 1652; CI-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x1000053; VI-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x1000054; GFX9-DAG: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x1000055 56; GCN-DAG: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]57; GCN: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]]58; GCN: buffer_store_byte [[REG]],59define amdgpu_kernel void @local_i8_load_over_i16_max_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {60 %gep = getelementptr i8, ptr addrspace(3) %in, i32 6553661 %val = load i8, ptr addrspace(3) %gep, align 462 store i8 %val, ptr addrspace(1) %out, align 463 ret void64}65 66; GCN-LABEL: {{^}}local_i64_load:67; SICIVI: s_mov_b32 m068; GFX9-NOT: m069 70; GCN-NOT: add71; GCN: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:5672; GCN: buffer_store_dwordx2 [[REG]],73define amdgpu_kernel void @local_i64_load(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {74 %gep = getelementptr i64, ptr addrspace(3) %in, i32 775 %val = load i64, ptr addrspace(3) %gep, align 876 store i64 %val, ptr addrspace(1) %out, align 877 ret void78}79 80; GCN-LABEL: {{^}}local_i64_load_0_offset81; SICIVI: s_mov_b32 m082; GFX9-NOT: m083 84; GCN: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}85; GCN: buffer_store_dwordx2 [[REG]],86define amdgpu_kernel void @local_i64_load_0_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {87 %val = load i64, ptr addrspace(3) %in, align 888 store i64 %val, ptr addrspace(1) %out, align 889 ret void90}91 92; GCN-LABEL: {{^}}local_f64_load:93; SICIVI: s_mov_b32 m094; GFX9-NOT: m095 96; GCN-NOT: add97; GCN: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:5698; GCN: buffer_store_dwordx2 [[REG]],99define amdgpu_kernel void @local_f64_load(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {100 %gep = getelementptr double, ptr addrspace(3) %in, i32 7101 %val = load double, ptr addrspace(3) %gep, align 8102 store double %val, ptr addrspace(1) %out, align 8103 ret void104}105 106; GCN-LABEL: {{^}}local_f64_load_0_offset107; SICIVI: s_mov_b32 m0108; GFX9-NOT: m0109 110; GCN: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}111; GCN: buffer_store_dwordx2 [[REG]],112define amdgpu_kernel void @local_f64_load_0_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {113 %val = load double, ptr addrspace(3) %in, align 8114 store double %val, ptr addrspace(1) %out, align 8115 ret void116}117 118; GCN-LABEL: {{^}}local_i64_store:119; SICIVI: s_mov_b32 m0120; GFX9-NOT: m0121 122; GCN-NOT: add123; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56124define amdgpu_kernel void @local_i64_store(ptr addrspace(3) %out) #0 {125 %gep = getelementptr i64, ptr addrspace(3) %out, i32 7126 store i64 5678, ptr addrspace(3) %gep, align 8127 ret void128}129 130; GCN-LABEL: {{^}}local_i64_store_0_offset:131; SICIVI: s_mov_b32 m0132; GFX9-NOT: m0133 134; GCN-NOT: add135; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}136define amdgpu_kernel void @local_i64_store_0_offset(ptr addrspace(3) %out) #0 {137 store i64 1234, ptr addrspace(3) %out, align 8138 ret void139}140 141; GCN-LABEL: {{^}}local_f64_store:142; SICIVI: s_mov_b32 m0143; GFX9-NOT: m0144 145; GCN-NOT: add146; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56147define amdgpu_kernel void @local_f64_store(ptr addrspace(3) %out) #0 {148 %gep = getelementptr double, ptr addrspace(3) %out, i32 7149 store double 16.0, ptr addrspace(3) %gep, align 8150 ret void151}152 153; GCN-LABEL: {{^}}local_f64_store_0_offset154; SICIVI: s_mov_b32 m0155; GFX9-NOT: m0156 157; GCN: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}158define amdgpu_kernel void @local_f64_store_0_offset(ptr addrspace(3) %out) #0 {159 store double 20.0, ptr addrspace(3) %out, align 8160 ret void161}162 163; GCN-LABEL: {{^}}local_v2i64_store:164; SICIVI: s_mov_b32 m0165; GFX9-NOT: m0166 167; GCN-NOT: add168; SI: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:14 offset1:15169; CIPLUS: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112170; GCN: s_endpgm171define amdgpu_kernel void @local_v2i64_store(ptr addrspace(3) %out) #0 {172 %gep = getelementptr <2 x i64>, ptr addrspace(3) %out, i32 7173 store <2 x i64> <i64 5678, i64 5678>, ptr addrspace(3) %gep, align 16174 ret void175}176 177; GCN-LABEL: {{^}}local_v2i64_store_0_offset:178; SICIVI: s_mov_b32 m0179; GFX9-NOT: m0180 181; GCN-NOT: add182 183; SI: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:1{{$}}184; CIPLUS: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}185 186; GCN: s_endpgm187define amdgpu_kernel void @local_v2i64_store_0_offset(ptr addrspace(3) %out) #0 {188 store <2 x i64> <i64 1234, i64 1234>, ptr addrspace(3) %out, align 16189 ret void190}191 192; GCN-LABEL: {{^}}local_v4i64_store:193; SICIVI: s_mov_b32 m0194; GFX9-NOT: m0195 196; GCN-NOT: add197; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:30 offset1:31198; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:28 offset1:29199 200; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224{{$}}201; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240{{$}}202 203; GCN: s_endpgm204define amdgpu_kernel void @local_v4i64_store(ptr addrspace(3) %out) #0 {205 %gep = getelementptr <4 x i64>, ptr addrspace(3) %out, i32 7206 store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, ptr addrspace(3) %gep, align 16207 ret void208}209 210; GCN-LABEL: {{^}}local_v4i64_store_0_offset:211; SICIVI: s_mov_b32 m0212; GFX9-NOT: m0213 214; GCN-NOT: add215; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3216; SI-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:1217 218; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}219; CIPLUS-DAG: ds_write_b128 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16{{$}}220 221; GCN: s_endpgm222define amdgpu_kernel void @local_v4i64_store_0_offset(ptr addrspace(3) %out) #0 {223 store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, ptr addrspace(3) %out, align 16224 ret void225}226 227attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }228