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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -amdgpu-s-branch-bits=4 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4; OBJ: Relocations [5; OBJ-NEXT: ]6 7; Used to emit an always 4 byte instruction. Inline asm always assumes8; each instruction is the maximum size.9declare void @llvm.amdgcn.s.sleep(i32) #010 11declare i32 @llvm.amdgcn.workitem.id.x() #112 13 14define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {15; GCN-LABEL: uniform_conditional_max_short_forward_branch:16; GCN: ; %bb.0: ; %bb17; GCN-NEXT: s_load_dword s0, s[4:5], 0xb18; GCN-NEXT: s_waitcnt lgkmcnt(0)19; GCN-NEXT: s_cmp_eq_u32 s0, 020; GCN-NEXT: s_cbranch_scc1 .LBB0_221; GCN-NEXT: ; %bb.1: ; %bb222; GCN-NEXT: ;;#ASMSTART23; GCN-NEXT: v_nop_e6424; GCN-NEXT: v_nop_e6425; GCN-NEXT: v_nop_e6426; GCN-NEXT: ;;#ASMEND27; GCN-NEXT: s_sleep 028; GCN-NEXT: .LBB0_2: ; %bb329; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x930; GCN-NEXT: s_mov_b32 s7, 0xf00031; GCN-NEXT: s_mov_b32 s6, -132; GCN-NEXT: v_mov_b32_e32 v0, s033; GCN-NEXT: s_waitcnt lgkmcnt(0)34; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 035; GCN-NEXT: s_waitcnt vmcnt(0)36; GCN-NEXT: s_endpgm37bb:38 %cmp = icmp eq i32 %cnd, 039 br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch40 41bb2:42; 24 bytes43 call void asm sideeffect44 "v_nop_e6445 v_nop_e6446 v_nop_e64", ""() #047 call void @llvm.amdgcn.s.sleep(i32 0)48 br label %bb349 50bb3:51 store volatile i32 %cnd, ptr addrspace(1) %arg52 ret void53}54 55define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 {56; GCN-LABEL: uniform_conditional_min_long_forward_branch:57; GCN: ; %bb.0: ; %bb058; GCN-NEXT: s_load_dword s0, s[4:5], 0xb59; GCN-NEXT: s_waitcnt lgkmcnt(0)60; GCN-NEXT: s_cmp_eq_u32 s0, 061; GCN-NEXT: s_cbranch_scc0 .LBB1_162; GCN-NEXT: ; %bb.3: ; %bb063; GCN-NEXT: s_getpc_b64 s[2:3]64; GCN-NEXT: .Lpost_getpc0:65; GCN-NEXT: s_add_u32 s2, s2, (.LBB1_2-.Lpost_getpc0)&429496729566; GCN-NEXT: s_addc_u32 s3, s3, (.LBB1_2-.Lpost_getpc0)>>3267; GCN-NEXT: s_setpc_b64 s[2:3]68; GCN-NEXT: .LBB1_1: ; %bb269; GCN-NEXT: ;;#ASMSTART70; GCN-NEXT: v_nop_e6471; GCN-NEXT: v_nop_e6472; GCN-NEXT: v_nop_e6473; GCN-NEXT: v_nop_e6474; GCN-NEXT: ;;#ASMEND75; GCN-NEXT: .LBB1_2: ; %bb376; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x977; GCN-NEXT: s_mov_b32 s7, 0xf00078; GCN-NEXT: s_mov_b32 s6, -179; GCN-NEXT: v_mov_b32_e32 v0, s080; GCN-NEXT: s_waitcnt lgkmcnt(0)81; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 082; GCN-NEXT: s_waitcnt vmcnt(0)83; GCN-NEXT: s_endpgm84bb0:85 %cmp = icmp eq i32 %cnd, 086 br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch87 88bb2:89; 32 bytes90 call void asm sideeffect91 "v_nop_e6492 v_nop_e6493 v_nop_e6494 v_nop_e64", ""() #095 br label %bb396 97bb3:98 store volatile i32 %cnd, ptr addrspace(1) %arg99 ret void100}101 102define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr addrspace(1) %arg, float %cnd) #0 {103; GCN-LABEL: uniform_conditional_min_long_forward_vcnd_branch:104; GCN: ; %bb.0: ; %bb0105; GCN-NEXT: s_load_dword s0, s[4:5], 0xb106; GCN-NEXT: s_waitcnt lgkmcnt(0)107; GCN-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, 0108; GCN-NEXT: s_and_b64 vcc, exec, s[2:3]109; GCN-NEXT: s_cbranch_vccz .LBB2_1110; GCN-NEXT: ; %bb.3: ; %bb0111; GCN-NEXT: s_getpc_b64 s[8:9]112; GCN-NEXT: .Lpost_getpc1:113; GCN-NEXT: s_add_u32 s8, s8, (.LBB2_2-.Lpost_getpc1)&4294967295114; GCN-NEXT: s_addc_u32 s9, s9, (.LBB2_2-.Lpost_getpc1)>>32115; GCN-NEXT: s_setpc_b64 s[8:9]116; GCN-NEXT: .LBB2_1: ; %bb2117; GCN-NEXT: ;;#ASMSTART118; GCN-NEXT: ; 32 bytes119; GCN-NEXT: v_nop_e64120; GCN-NEXT: v_nop_e64121; GCN-NEXT: v_nop_e64122; GCN-NEXT: v_nop_e64123; GCN-NEXT: ;;#ASMEND124; GCN-NEXT: .LBB2_2: ; %bb3125; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9126; GCN-NEXT: s_mov_b32 s7, 0xf000127; GCN-NEXT: s_mov_b32 s6, -1128; GCN-NEXT: v_mov_b32_e32 v0, s0129; GCN-NEXT: s_waitcnt lgkmcnt(0)130; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0131; GCN-NEXT: s_waitcnt vmcnt(0)132; GCN-NEXT: s_endpgm133bb0:134 %cmp = fcmp oeq float %cnd, 0.0135 br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch136 137bb2:138 call void asm sideeffect " ; 32 bytes139 v_nop_e64140 v_nop_e64141 v_nop_e64142 v_nop_e64", ""() #0143 br label %bb3144 145bb3:146 store volatile float %cnd, ptr addrspace(1) %arg147 ret void148}149 150define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 {151; GCN-LABEL: min_long_forward_vbranch:152; GCN: ; %bb.0: ; %bb153; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9154; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0155; GCN-NEXT: v_mov_b32_e32 v1, 0156; GCN-NEXT: s_mov_b32 s3, 0xf000157; GCN-NEXT: s_mov_b32 s2, 0158; GCN-NEXT: s_waitcnt lgkmcnt(0)159; GCN-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc160; GCN-NEXT: s_waitcnt vmcnt(0)161; GCN-NEXT: v_mov_b32_e32 v1, s1162; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0163; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc164; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2165; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc166; GCN-NEXT: s_cbranch_execnz .LBB3_1167; GCN-NEXT: ; %bb.3: ; %bb168; GCN-NEXT: s_getpc_b64 s[6:7]169; GCN-NEXT: .Lpost_getpc2:170; GCN-NEXT: s_add_u32 s6, s6, (.LBB3_2-.Lpost_getpc2)&4294967295171; GCN-NEXT: s_addc_u32 s7, s7, (.LBB3_2-.Lpost_getpc2)>>32172; GCN-NEXT: s_setpc_b64 s[6:7]173; GCN-NEXT: .LBB3_1: ; %bb2174; GCN-NEXT: ;;#ASMSTART175; GCN-NEXT: ; 32 bytes176; GCN-NEXT: v_nop_e64177; GCN-NEXT: v_nop_e64178; GCN-NEXT: v_nop_e64179; GCN-NEXT: v_nop_e64180; GCN-NEXT: ;;#ASMEND181; GCN-NEXT: .LBB3_2: ; %bb3182; GCN-NEXT: s_or_b64 exec, exec, s[0:1]183; GCN-NEXT: s_mov_b32 s0, s2184; GCN-NEXT: s_mov_b32 s1, s2185; GCN-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64186; GCN-NEXT: s_waitcnt vmcnt(0)187; GCN-NEXT: s_endpgm188bb:189 %tid = call i32 @llvm.amdgcn.workitem.id.x()190 %tid.ext = zext i32 %tid to i64191 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tid.ext192 %load = load volatile i32, ptr addrspace(1) %gep193 %cmp = icmp eq i32 %load, 0194 br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch195 196bb2:197 call void asm sideeffect " ; 32 bytes198 v_nop_e64199 v_nop_e64200 v_nop_e64201 v_nop_e64", ""() #0202 br label %bb3203 204bb3:205 store volatile i32 %load, ptr addrspace(1) %gep206 ret void207}208 209define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 {210; GCN-LABEL: long_backward_sbranch:211; GCN: ; %bb.0: ; %bb212; GCN-NEXT: s_mov_b32 s0, 0213; GCN-NEXT: .LBB4_1: ; %bb2214; GCN-NEXT: ; =>This Inner Loop Header: Depth=1215; GCN-NEXT: s_add_i32 s0, s0, 1216; GCN-NEXT: s_cmp_lt_i32 s0, 10217; GCN-NEXT: ;;#ASMSTART218; GCN-NEXT: v_nop_e64219; GCN-NEXT: v_nop_e64220; GCN-NEXT: v_nop_e64221; GCN-NEXT: ;;#ASMEND222; GCN-NEXT: s_cbranch_scc0 .LBB4_2223; GCN-NEXT: ; %bb.3: ; %bb2224; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1225; GCN-NEXT: s_getpc_b64 s[2:3]226; GCN-NEXT: .Lpost_getpc3:227; GCN-NEXT: s_add_u32 s2, s2, (.LBB4_1-.Lpost_getpc3)&4294967295228; GCN-NEXT: s_addc_u32 s3, s3, (.LBB4_1-.Lpost_getpc3)>>32229; GCN-NEXT: s_setpc_b64 s[2:3]230; GCN-NEXT: .LBB4_2: ; %bb3231; GCN-NEXT: s_endpgm232 233bb:234 br label %bb2235 236bb2:237 %loop.idx = phi i32 [ 0, %bb ], [ %inc, %bb2 ]238 ; 24 bytes239 call void asm sideeffect240 "v_nop_e64241 v_nop_e64242 v_nop_e64", ""() #0243 %inc = add nsw i32 %loop.idx, 1 ; add cost 4244 %cmp = icmp slt i32 %inc, 10 ; condition cost = 8245 br i1 %cmp, label %bb2, label %bb3 ; -246 247bb3:248 ret void249}250 251; Requires expansion of unconditional branch from %bb2 to %bb4 (and252; expansion of conditional branch from %bb to %bb3.253 254define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %arg1) {255; GCN-LABEL: uniform_unconditional_min_long_forward_branch:256; GCN: ; %bb.0: ; %bb0257; GCN-NEXT: s_load_dword s0, s[4:5], 0xb258; GCN-NEXT: s_waitcnt lgkmcnt(0)259; GCN-NEXT: s_cmp_eq_u32 s0, 0260; GCN-NEXT: s_mov_b64 s[0:1], -1261; GCN-NEXT: s_cbranch_scc0 .LBB5_1262; GCN-NEXT: ; %bb.7: ; %bb0263; GCN-NEXT: s_getpc_b64 s[6:7]264; GCN-NEXT: .Lpost_getpc5:265; GCN-NEXT: s_add_u32 s6, s6, (.LBB5_4-.Lpost_getpc5)&4294967295266; GCN-NEXT: s_addc_u32 s7, s7, (.LBB5_4-.Lpost_getpc5)>>32267; GCN-NEXT: s_setpc_b64 s[6:7]268; GCN-NEXT: .LBB5_1: ; %Flow269; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1]270; GCN-NEXT: s_cbranch_vccnz .LBB5_3271; GCN-NEXT: .LBB5_2: ; %bb2272; GCN-NEXT: s_mov_b32 s3, 0xf000273; GCN-NEXT: s_mov_b32 s2, -1274; GCN-NEXT: v_mov_b32_e32 v0, 17275; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0276; GCN-NEXT: s_waitcnt vmcnt(0)277; GCN-NEXT: .LBB5_3: ; %bb4278; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9279; GCN-NEXT: s_mov_b32 s3, 0xf000280; GCN-NEXT: s_mov_b32 s2, -1281; GCN-NEXT: s_waitcnt expcnt(0)282; GCN-NEXT: v_mov_b32_e32 v0, 63283; GCN-NEXT: s_waitcnt lgkmcnt(0)284; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0285; GCN-NEXT: s_waitcnt vmcnt(0)286; GCN-NEXT: s_endpgm287; GCN-NEXT: .LBB5_4: ; %bb3288; GCN-NEXT: ;;#ASMSTART289; GCN-NEXT: v_nop_e64290; GCN-NEXT: v_nop_e64291; GCN-NEXT: v_nop_e64292; GCN-NEXT: v_nop_e64293; GCN-NEXT: ;;#ASMEND294; GCN-NEXT: s_mov_b64 vcc, exec295; GCN-NEXT: s_cbranch_execnz .LBB5_5296; GCN-NEXT: ; %bb.9: ; %bb3297; GCN-NEXT: s_getpc_b64 s[6:7]298; GCN-NEXT: .Lpost_getpc6:299; GCN-NEXT: s_add_u32 s6, s6, (.LBB5_2-.Lpost_getpc6)&4294967295300; GCN-NEXT: s_addc_u32 s7, s7, (.LBB5_2-.Lpost_getpc6)>>32301; GCN-NEXT: s_setpc_b64 s[6:7]302; GCN-NEXT: .LBB5_5: ; %bb3303; GCN-NEXT: s_getpc_b64 s[6:7]304; GCN-NEXT: .Lpost_getpc4:305; GCN-NEXT: s_add_u32 s6, s6, (.LBB5_3-.Lpost_getpc4)&4294967295306; GCN-NEXT: s_addc_u32 s7, s7, (.LBB5_3-.Lpost_getpc4)>>32307; GCN-NEXT: s_setpc_b64 s[6:7]308bb0:309 %tmp = icmp ne i32 %arg1, 0310 br i1 %tmp, label %bb2, label %bb3311 312bb2:313 store volatile i32 17, ptr addrspace(1) poison314 br label %bb4315 316bb3:317 ; 32 byte asm318 call void asm sideeffect319 "v_nop_e64320 v_nop_e64321 v_nop_e64322 v_nop_e64", ""() #0323 br label %bb4324 325bb4:326 store volatile i32 63, ptr addrspace(1) %arg327 ret void328}329 330attributes #0 = { nounwind }331attributes #1 = { nounwind readnone }332