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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -amdgpu-enable-rewrite-partial-reg-uses=false < %s | FileCheck %s3 4; This example used to produce a verifier error resulting from the5; register coalescer leaving behind a false live interval when a live6; out copy introduced new liveness for a subregister.7 8define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {9; CHECK-LABEL: liveout_undef_subrange:10; CHECK: ; %bb.0: ; %bb11; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; CHECK-NEXT: v_add_f32_e32 v3, v2, v213; CHECK-NEXT: s_mov_b64 s[4:5], 014; CHECK-NEXT: ; kill: killed $vgpr115; CHECK-NEXT: v_add_f32_e32 v0, v0, v016; CHECK-NEXT: .LBB0_1: ; %bb117; CHECK-NEXT: ; =>This Inner Loop Header: Depth=118; CHECK-NEXT: v_cmp_neq_f32_e32 vcc, 0, v219; CHECK-NEXT: s_or_b64 s[4:5], vcc, s[4:5]20; CHECK-NEXT: s_andn2_b64 exec, exec, s[4:5]21; CHECK-NEXT: s_cbranch_execnz .LBB0_122; CHECK-NEXT: ; %bb.2: ; %bb223; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=124; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]25; CHECK-NEXT: v_mul_f32_e32 v2, v3, v226; CHECK-NEXT: s_mov_b64 s[4:5], 027; CHECK-NEXT: s_cbranch_execnz .LBB0_128; CHECK-NEXT: ; %bb.3: ; %DummyReturnBlock29; CHECK-NEXT: s_setpc_b64 s[30:31]30bb:31 br label %bb132 33bb1: ; preds = %bb3, %bb34 %i = phi <3 x float> [ %arg, %bb ], [ %i11, %bb3 ]35 %i2 = extractelement <3 x float> %i, i64 236 %i3 = fmul float %i2, 1.000000e+0037 %i4 = fmul nsz <3 x float> %arg, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>38 %i5 = insertelement <3 x float> poison, float %i3, i32 039 %i6 = shufflevector <3 x float> %i5, <3 x float> poison, <3 x i32> zeroinitializer40 %i7 = fmul <3 x float> %i4, %i641 %i8 = fcmp oeq float %i3, 0.000000e+0042 br i1 %i8, label %bb3, label %bb243 44bb2: ; preds = %bb145 br label %bb346 47bb3: ; preds = %bb2, %bb148 %i11 = phi <3 x float> [ %i7, %bb2 ], [ %i, %bb1 ]49 br label %bb150}51