334 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -run-pass=liveintervals -run-pass=si-lower-control-flow -mtriple=amdgcn--amdpal -mcpu=gfx1030 -verify-machineinstrs -o - %s | FileCheck %s3# RUN: llc -passes='require<live-intervals>,si-lower-control-flow' -mtriple=amdgcn--amdpal -mcpu=gfx1030 -o - %s | FileCheck %s4 5# Check that verifier passes for the following.6 7# Caused: Live segment doesn't end at a valid instruction8---9name: _amdgpu_cs_main110tracksRegLiveness: true11body: |12 ; CHECK-LABEL: name: _amdgpu_cs_main113 ; CHECK: bb.0:14 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)15 ; CHECK-NEXT: liveins: $vgpr016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr018 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec19 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo20 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc21 ; CHECK-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_]], [[COPY1]], implicit-def dead $scc22 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]]23 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec24 ; CHECK-NEXT: S_BRANCH %bb.225 ; CHECK-NEXT: {{ $}}26 ; CHECK-NEXT: bb.1:27 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, %3, implicit-def $scc28 ; CHECK-NEXT: S_ENDPGM 029 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.2:31 ; CHECK-NEXT: successors: %bb.3(0x80000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: bb.3:34 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)35 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[S_OR_SAVEEXEC_B32_:%[0-9]+]]:sreg_32 = S_OR_SAVEEXEC_B32 [[S_XOR_B32_]], implicit-def $exec, implicit-def $scc, implicit $exec37 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[S_OR_SAVEEXEC_B32_]], implicit-def $scc38 ; CHECK-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_B32_1]], implicit-def $scc39 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec40 ; CHECK-NEXT: S_BRANCH %bb.441 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: bb.4:43 ; CHECK-NEXT: successors: %bb.1(0x80000000)44 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: S_BRANCH %bb.146 bb.0:47 successors: %bb.2(0x40000000), %bb.3(0x40000000)48 liveins: $vgpr049 50 %2:vgpr_32 = COPY killed $vgpr051 %6:sreg_32 = V_CMP_NE_U32_e64 0, killed %2, implicit $exec52 %0:sreg_32 = SI_IF killed %6, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec53 S_BRANCH %bb.254 55 bb.1:56 SI_END_CF killed %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec57 S_ENDPGM 058 59 bb.2:60 successors: %bb.3(0x80000000)61 62 63 bb.3:64 successors: %bb.4(0x40000000), %bb.1(0x40000000)65 66 %1:sreg_32 = SI_ELSE killed %0, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec67 S_BRANCH %bb.468 69 bb.4:70 successors: %bb.1(0x80000000)71 72 S_BRANCH %bb.173 74...75 76# Caused: Assertion `itr != mi2iMap.end() && "Instruction not in maps."' failed.77---78name: _amdgpu_cs_main279tracksRegLiveness: true80body: |81 ; CHECK-LABEL: name: _amdgpu_cs_main282 ; CHECK: bb.0:83 ; CHECK-NEXT: successors: %bb.1(0x80000000)84 ; CHECK-NEXT: liveins: $vgpr085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr087 ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 1, [[COPY]], implicit $exec88 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 089 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]90 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: bb.1:92 ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)93 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY1]]95 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[V_CMP_GT_I32_e64_]], implicit-def $scc96 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc97 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[S_OR_B32_]]98 ; CHECK-NEXT: $exec_lo = S_ANDN2_B32_term $exec_lo, [[S_OR_B32_]], implicit-def $scc99 ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec100 ; CHECK-NEXT: S_BRANCH %bb.2101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: bb.2:103 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[S_OR_B32_]], implicit-def $scc104 ; CHECK-NEXT: S_ENDPGM 0105 bb.0:106 successors: %bb.1(0x80000000)107 liveins: $vgpr0108 109 %4:vgpr_32 = COPY killed $vgpr0110 %8:sreg_32 = V_CMP_GT_I32_e64 1, killed %4, implicit $exec111 %6:sreg_32 = S_MOV_B32 0112 %10:sreg_32 = COPY killed %6113 114 bb.1:115 successors: %bb.2(0x04000000), %bb.1(0x7c000000)116 117 %1:sreg_32 = COPY killed %10118 %2:sreg_32 = SI_IF_BREAK %8, killed %1, implicit-def dead $scc119 %10:sreg_32 = COPY %2120 SI_LOOP %2, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec121 S_BRANCH %bb.2122 123 bb.2:124 SI_END_CF killed %2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec125 S_ENDPGM 0126 127...128 129# Caused: Live range continues after kill flag130---131name: _amdgpu_cs_main3132tracksRegLiveness: true133body: |134 ; CHECK-LABEL: name: _amdgpu_cs_main3135 ; CHECK: bb.0:136 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)137 ; CHECK-NEXT: liveins: $vgpr0138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0140 ; CHECK-NEXT: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, [[COPY]], 0, implicit $mode, implicit $exec141 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo142 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[V_CMP_NGT_F32_e64_]], implicit-def dead $scc143 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]]144 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec145 ; CHECK-NEXT: S_BRANCH %bb.1146 ; CHECK-NEXT: {{ $}}147 ; CHECK-NEXT: bb.1:148 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, 0, 0, [[COPY]], 0, implicit $mode, implicit $exec151 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo152 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[V_CMP_NLT_F32_e64_]], implicit-def dead $scc153 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_1]]154 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec155 ; CHECK-NEXT: S_BRANCH %bb.2156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: bb.2:158 ; CHECK-NEXT: successors: %bb.4(0x80000000)159 ; CHECK-NEXT: {{ $}}160 ; CHECK-NEXT: bb.4:161 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY1]], implicit-def $scc162 ; CHECK-NEXT: S_ENDPGM 0163 bb.0:164 successors: %bb.1(0x40000000), %bb.4(0x40000000)165 liveins: $vgpr0166 167 %2:vgpr_32 = COPY killed $vgpr0168 %5:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, %2, 0, implicit $mode, implicit $exec169 %0:sreg_32 = SI_IF killed %5, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec170 S_BRANCH %bb.1171 172 bb.1:173 successors: %bb.2(0x40000000), %bb.3(0x40000000)174 175 %7:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, 0, 0, killed %2, 0, implicit $mode, implicit $exec176 %1:sreg_32 = SI_IF killed %7, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec177 S_BRANCH %bb.2178 179 bb.2:180 successors: %bb.3(0x80000000)181 182 183 bb.3:184 successors: %bb.4(0x80000000)185 186 SI_END_CF killed %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec187 188 bb.4:189 SI_END_CF killed %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec190 S_ENDPGM 0191 192...193 194# Caused: Live range continues after dead def flag195---196name: _amdgpu_cs_main4197tracksRegLiveness: true198body: |199 ; CHECK-LABEL: name: _amdgpu_cs_main4200 ; CHECK: bb.0:201 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000)202 ; CHECK-NEXT: liveins: $vgpr0203 ; CHECK-NEXT: {{ $}}204 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0205 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0206 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec207 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo208 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc209 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_]]210 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec211 ; CHECK-NEXT: S_BRANCH %bb.1212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: bb.1:214 ; CHECK-NEXT: successors: %bb.6(0x80000000)215 ; CHECK-NEXT: {{ $}}216 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $exec_lo217 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY2]]218 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_MOV_B32_]]219 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY3]]220 ; CHECK-NEXT: S_BRANCH %bb.6221 ; CHECK-NEXT: {{ $}}222 ; CHECK-NEXT: bb.2:223 ; CHECK-NEXT: successors: %bb.5(0x80000000)224 ; CHECK-NEXT: {{ $}}225 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE %9, %subreg.sub0, %9, %subreg.sub1, %9, %subreg.sub2, %9, %subreg.sub3226 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY %11227 ; CHECK-NEXT: BUFFER_ATOMIC_ADD_OFFSET [[COPY6]], [[REG_SEQUENCE]], 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), align 1, addrspace 8)228 ; CHECK-NEXT: S_BRANCH %bb.5229 ; CHECK-NEXT: {{ $}}230 ; CHECK-NEXT: bb.4:231 ; CHECK-NEXT: S_ENDPGM 0232 ; CHECK-NEXT: {{ $}}233 ; CHECK-NEXT: bb.5:234 ; CHECK-NEXT: successors: %bb.4(0x80000000)235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY1]], implicit-def $scc237 ; CHECK-NEXT: S_BRANCH %bb.4238 ; CHECK-NEXT: {{ $}}239 ; CHECK-NEXT: bb.6:240 ; CHECK-NEXT: successors: %bb.7(0x04000000), %bb.6(0x7c000000)241 ; CHECK-NEXT: {{ $}}242 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[COPY4]]243 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[COPY5]]244 ; CHECK-NEXT: [[S_FF1_I32_B32_:%[0-9]+]]:sreg_32 = S_FF1_I32_B32 [[COPY8]]245 ; CHECK-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READLANE_B32 [[COPY]], [[S_FF1_I32_B32_]]246 ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY7]], [[V_READLANE_B32_]], implicit-def dead $scc247 ; CHECK-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 1, [[S_FF1_I32_B32_]], implicit-def dead $scc248 ; CHECK-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[COPY8]], [[S_LSHL_B32_]], implicit-def dead $scc249 ; CHECK-NEXT: S_CMP_LG_U32 [[S_ANDN2_B32_]], 0, implicit-def $scc250 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_ADD_I32_]]251 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_ANDN2_B32_]]252 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.6, implicit killed $scc253 ; CHECK-NEXT: S_BRANCH %bb.7254 ; CHECK-NEXT: {{ $}}255 ; CHECK-NEXT: bb.7:256 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)257 ; CHECK-NEXT: {{ $}}258 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0259 ; CHECK-NEXT: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY2]], 0, implicit $exec260 ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 0, [[V_MBCNT_LO_U32_B32_e64_]], implicit $exec261 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $exec_lo, implicit-def $exec_lo262 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY9]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc263 ; CHECK-NEXT: dead [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_1]], [[COPY9]], implicit-def dead $scc264 ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_AND_B32_1]]265 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec266 ; CHECK-NEXT: S_BRANCH %bb.2267 bb.0:268 successors: %bb.1(0x40000000), %bb.5(0x40000000)269 liveins: $vgpr0270 271 %8:vgpr_32 = COPY killed $vgpr0272 %10:sreg_32 = S_MOV_B32 0273 %11:sreg_32 = V_CMP_NE_U32_e64 0, %8, implicit $exec274 %0:sreg_32 = SI_IF killed %11, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec275 S_BRANCH %bb.1276 277 bb.1:278 successors: %bb.6(0x80000000)279 280 %13:sreg_32 = COPY $exec_lo281 %1:sreg_32 = COPY %13282 %25:sreg_32 = COPY killed %10283 %26:sreg_32 = COPY killed %1284 S_BRANCH %bb.6285 286 bb.2:287 successors: %bb.3(0x80000000)288 289 %23:sgpr_128 = REG_SEQUENCE killed %19, %subreg.sub0, %19, %subreg.sub1, %19, %subreg.sub2, %19, %subreg.sub3290 %24:vgpr_32 = COPY killed %4291 BUFFER_ATOMIC_ADD_OFFSET killed %24, killed %23, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s32), align 1, addrspace 8)292 293 bb.3:294 successors: %bb.5(0x80000000)295 296 SI_END_CF killed %7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec297 S_BRANCH %bb.5298 299 bb.4:300 S_ENDPGM 0301 302 bb.5:303 successors: %bb.4(0x80000000)304 305 SI_END_CF killed %0, implicit-def dead $exec, implicit-def dead $scc, implicit $exec306 S_BRANCH %bb.4307 308 bb.6:309 successors: %bb.7(0x04000000), %bb.6(0x7c000000)310 311 %2:sreg_32 = COPY killed %25312 %3:sreg_32 = COPY killed %26313 %14:sreg_32 = S_FF1_I32_B32 %3314 %15:sreg_32_xm0 = V_READLANE_B32 %8, %14315 %4:sreg_32 = S_ADD_I32 killed %2, killed %15, implicit-def dead $scc316 %17:sreg_32 = S_LSHL_B32 1, killed %14, implicit-def dead $scc317 %5:sreg_32 = S_ANDN2_B32 killed %3, killed %17, implicit-def dead $scc318 S_CMP_LG_U32 %5, 0, implicit-def $scc319 %25:sreg_32 = COPY %4320 %26:sreg_32 = COPY killed %5321 S_CBRANCH_SCC1 %bb.6, implicit killed $scc322 S_BRANCH %bb.7323 324 bb.7:325 successors: %bb.2(0x40000000), %bb.3(0x40000000)326 327 %19:sreg_32 = S_MOV_B32 0328 %20:vgpr_32 = V_MBCNT_LO_U32_B32_e64 killed %13, 0, implicit $exec329 %21:sreg_32 = V_CMP_EQ_U32_e64 0, killed %20, implicit $exec330 %7:sreg_32 = SI_IF killed %21, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec331 S_BRANCH %bb.2332 333...334