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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-i1-copies -o - %s | FileCheck %s3 4# %bb.1 and %bb.3 loop back to each other, and thus neither dominates5# the other.6# When the phi in %bb.3 is handled, it attempted to insert instructions7# in %bb.1 to handle this def, but ended up inserting mask management8# instructions before the def of %34. This is avoided by treating9# IMPLICIT_DEF specially like constants10 11---12name: recursive_vreg_1_phi13tracksRegLiveness: true14machineFunctionInfo:15 isEntryFunction: true16body: |17 ; CHECK-LABEL: name: recursive_vreg_1_phi18 ; CHECK: bb.0:19 ; CHECK-NEXT: successors: %bb.1(0x80000000)20 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr1621 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF23 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2024 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]25 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF26 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1027 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]28 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF29 ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF30 ; CHECK-NEXT: [[V_OR_B32_e32_:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 killed [[DEF3]], killed [[DEF1]], implicit $exec31 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr032 ; CHECK-NEXT: [[DEF4:%[0-9]+]]:sreg_32 = IMPLICIT_DEF33 ; CHECK-NEXT: [[V_ASHRREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 31, [[COPY2]], implicit $exec34 ; CHECK-NEXT: [[DEF5:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF35 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_ASHRREV_I32_e32_]], %subreg.sub136 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 237 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY killed [[S_MOV_B32_2]]38 ; CHECK-NEXT: [[V_LSHL_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_B64_e64 killed [[REG_SEQUENCE]], [[COPY3]], implicit $exec39 ; CHECK-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD killed [[V_LSHL_B64_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)40 ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 041 ; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 6842 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[S_MOV_B32_4]]43 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_3]]44 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub145 ; CHECK-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 43246 ; CHECK-NEXT: [[V_MAD_I64_I32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_e64_1:%[0-9]+]]:sreg_64 = V_MAD_I64_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[S_MOV_B32_5]], [[REG_SEQUENCE1]], 0, implicit $exec47 ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 048 ; CHECK-NEXT: [[DEF6:%[0-9]+]]:sreg_64 = IMPLICIT_DEF49 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: bb.1:51 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)52 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF6]], %bb.0, %31, %bb.354 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.0, %54, %bb.355 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_3]], %bb.0, %29, %bb.356 ; CHECK-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 057 ; CHECK-NEXT: [[S_ANDN2_B64_:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI]], $exec, implicit-def $scc58 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_64 = COPY [[S_ANDN2_B64_]]59 ; CHECK-NEXT: S_CMP_EQ_U32 [[PHI2]], killed [[S_MOV_B32_6]], implicit-def $scc60 ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -161 ; CHECK-NEXT: [[DEF7:%[0-9]+]]:sreg_64 = IMPLICIT_DEF62 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc63 ; CHECK-NEXT: S_BRANCH %bb.264 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: bb.2:66 ; CHECK-NEXT: successors: %bb.3(0x80000000)67 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[V_MAD_I64_I32_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)69 ; CHECK-NEXT: [[S_MOV_B32_7:%[0-9]+]]:sreg_32 = S_MOV_B32 670 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_7]]71 ; CHECK-NEXT: [[V_LSHR_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHR_B32_e32 killed [[FLAT_LOAD_DWORD1]], killed [[COPY7]], implicit $exec72 ; CHECK-NEXT: [[DEF8:%[0-9]+]]:sreg_32 = IMPLICIT_DEF73 ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 1, [[V_LSHR_B32_e32_]], implicit $exec74 ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_AND_B32_e64_]], 1, implicit $exec75 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY [[PHI1]]76 ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY8]], killed [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc77 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[PHI1]]78 ; CHECK-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 killed [[S_AND_B64_]], [[COPY9]], implicit-def dead $scc79 ; CHECK-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 080 ; CHECK-NEXT: [[DEF9:%[0-9]+]]:sreg_64 = IMPLICIT_DEF81 ; CHECK-NEXT: [[S_ANDN2_B64_1:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[COPY6]], $exec, implicit-def $scc82 ; CHECK-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_OR_B64_]], $exec, implicit-def $scc83 ; CHECK-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_1]], [[S_AND_B64_1]], implicit-def $scc84 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: bb.3:86 ; CHECK-NEXT: successors: %bb.4(0x00000000), %bb.1(0x80000000)87 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:sreg_64 = PHI [[COPY6]], %bb.1, [[S_OR_B64_1]], %bb.289 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:sreg_64 = PHI [[PHI1]], %bb.1, [[DEF9]], %bb.290 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:sreg_64_xexec = PHI [[S_MOV_B64_1]], %bb.1, [[S_MOV_B64_2]], %bb.291 ; CHECK-NEXT: [[S_MOV_B32_8:%[0-9]+]]:sreg_32 = S_MOV_B32 -192 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI5]], implicit $exec93 ; CHECK-NEXT: [[S_MOV_B32_9:%[0-9]+]]:sreg_32 = S_MOV_B32 194 ; CHECK-NEXT: [[DEF10:%[0-9]+]]:sreg_32 = IMPLICIT_DEF95 ; CHECK-NEXT: V_CMP_NE_U32_e32 killed [[S_MOV_B32_9]], [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec96 ; CHECK-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc97 ; CHECK-NEXT: [[S_ANDN2_B64_2:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI4]], $exec, implicit-def $scc98 ; CHECK-NEXT: [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[PHI3]], $exec, implicit-def $scc99 ; CHECK-NEXT: [[S_OR_B64_2:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_2]], [[S_AND_B64_2]], implicit-def $scc100 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc101 ; CHECK-NEXT: S_BRANCH %bb.4102 ; CHECK-NEXT: {{ $}}103 ; CHECK-NEXT: bb.4:104 bb.0:105 liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16106 107 %0:sreg_64 = IMPLICIT_DEF108 %1:sreg_32 = S_MOV_B32 20109 %2:vgpr_32 = COPY %1110 %3:vgpr_32 = IMPLICIT_DEF111 %4:sreg_32 = S_MOV_B32 10112 %5:vgpr_32 = COPY %4113 %6:vgpr_32 = IMPLICIT_DEF114 %7:vgpr_32 = IMPLICIT_DEF115 %8:vgpr_32 = V_OR_B32_e32 killed %7, killed %3, implicit $exec116 %9:vgpr_32 = COPY $vgpr0117 %10:sreg_32 = IMPLICIT_DEF118 %11:vgpr_32 = V_ASHRREV_I32_e32 31, %9, implicit $exec119 %12:sreg_32_xm0 = IMPLICIT_DEF120 %13:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %11, %subreg.sub1121 %14:sreg_32 = S_MOV_B32 2122 %15:sgpr_32 = COPY killed %14123 %16:vreg_64 = V_LSHL_B64_e64 killed %13, %15, implicit $exec124 %17:vgpr_32 = FLAT_LOAD_DWORD killed %16, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)125 %18:sreg_32 = S_MOV_B32 0126 %19:sreg_32 = S_MOV_B32 68127 %20:vgpr_32 = COPY killed %19128 %21:vgpr_32 = COPY %18129 %22:vreg_64 = REG_SEQUENCE killed %20, %subreg.sub0, %21, %subreg.sub1130 %23:sreg_32 = S_MOV_B32 432131 %24:vreg_64, %25:sreg_64 = V_MAD_I64_I32_e64 killed %17, killed %23, %22, 0, implicit $exec132 %26:sreg_64 = S_MOV_B64 0133 %27:vreg_1 = COPY %26, implicit $exec134 135 bb.1:136 successors: %bb.2, %bb.3137 138 %28:sreg_32 = PHI %18, %bb.0, %29, %bb.3139 %30:vreg_1 = PHI %27, %bb.0, %31, %bb.3140 %32:sreg_32 = S_MOV_B32 0141 S_CMP_EQ_U32 %28, killed %32, implicit-def $scc142 %33:sreg_64 = S_MOV_B64 -1143 %34:sreg_64 = IMPLICIT_DEF144 %35:vreg_1 = COPY %34145 S_CBRANCH_SCC1 %bb.3, implicit $scc146 S_BRANCH %bb.2147 148 bb.2:149 %36:vgpr_32 = FLAT_LOAD_DWORD %24, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32), addrspace 1)150 %37:sreg_32 = S_MOV_B32 6151 %38:vgpr_32 = COPY %37152 %39:vgpr_32 = V_LSHR_B32_e32 killed %36, killed %38, implicit $exec153 %40:sreg_32 = IMPLICIT_DEF154 %41:vgpr_32 = V_AND_B32_e64 1, %39, implicit $exec155 %42:sreg_64 = V_CMP_EQ_U32_e64 killed %41, 1, implicit $exec156 %43:sreg_64 = COPY %30157 %44:sreg_64 = S_AND_B64 %43, killed %42, implicit-def dead $scc158 %45:sreg_64 = COPY %30159 %46:sreg_64 = S_OR_B64 killed %44, %45, implicit-def dead $scc160 %47:sreg_64 = S_MOV_B64 0161 %48:vreg_1 = COPY %46162 163 bb.3:164 successors: %bb.4(0x00000000), %bb.1(0x80000000)165 166 %31:vreg_1 = PHI %35, %bb.1, %48, %bb.2167 %49:sreg_64_xexec = PHI %33, %bb.1, %47, %bb.2168 %29:sreg_32 = S_MOV_B32 -1169 %50:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %49, implicit $exec170 %51:sreg_32 = S_MOV_B32 1171 %52:sreg_32 = IMPLICIT_DEF172 V_CMP_NE_U32_e32 killed %51, %50, implicit-def $vcc, implicit $exec173 $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc174 S_CBRANCH_VCCNZ %bb.1, implicit $vcc175 S_BRANCH %bb.4176 177 bb.4:178 179...180