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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -codegen-opt-level=0 | FileCheck --check-prefixes=CHECK,NOOPT %s3; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -codegen-opt-level=1 -mattr=+wavefrontsize32 | FileCheck --check-prefixes=CHECK,OPT-WAVE32 %s4; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -codegen-opt-level=1 -mattr=+wavefrontsize64 | FileCheck --check-prefixes=CHECK,OPT-WAVE64 %s5 6declare void @foo(i1)7 8; Verify that the explicit use of a split cluster barrier isn't optimized away.9define amdgpu_kernel void @split_barriers() "amdgpu-flat-work-group-size"="32,32" {10; CHECK-LABEL: define amdgpu_kernel void @split_barriers(11; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {12; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)13; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)14; CHECK-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -3)15; CHECK-NEXT: call void @foo(i1 [[ISFIRST]])16; CHECK-NEXT: ret void17;18 call void @llvm.amdgcn.s.barrier.signal(i32 -3)19 call void @llvm.amdgcn.s.barrier.wait(i16 -3)20 %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -3)21 call void @foo(i1 %isfirst)22 ret void23}24 25define amdgpu_kernel void @s_cluster_barrier() {26; CHECK-LABEL: define amdgpu_kernel void @s_cluster_barrier(27; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {28; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)29; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)30; CHECK-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]31; CHECK: [[BB2]]:32; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)33; CHECK-NEXT: br label %[[BB3]]34; CHECK: [[BB3]]:35; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)36; CHECK-NEXT: ret void37;38 call void @llvm.amdgcn.s.cluster.barrier()39 ret void40}41 42define amdgpu_kernel void @s_cluster_barrier_wg32() "amdgpu-flat-work-group-size"="32,32" {43; NOOPT-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg32(44; NOOPT-SAME: ) #[[ATTR1]] {45; NOOPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)46; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)47; NOOPT-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]48; NOOPT: [[BB2]]:49; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)50; NOOPT-NEXT: br label %[[BB3]]51; NOOPT: [[BB3]]:52; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)53; NOOPT-NEXT: ret void54;55; OPT-WAVE32-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg32(56; OPT-WAVE32-SAME: ) #[[ATTR1]] {57; OPT-WAVE32-NEXT: call void @llvm.amdgcn.wave.barrier()58; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)59; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)60; OPT-WAVE32-NEXT: ret void61;62; OPT-WAVE64-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg32(63; OPT-WAVE64-SAME: ) #[[ATTR1]] {64; OPT-WAVE64-NEXT: call void @llvm.amdgcn.wave.barrier()65; OPT-WAVE64-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)66; OPT-WAVE64-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)67; OPT-WAVE64-NEXT: ret void68;69 call void @llvm.amdgcn.s.cluster.barrier()70 ret void71}72 73define amdgpu_kernel void @s_cluster_barrier_wg64() "amdgpu-flat-work-group-size"="64,64" {74; NOOPT-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg64(75; NOOPT-SAME: ) #[[ATTR2:[0-9]+]] {76; NOOPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)77; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)78; NOOPT-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]79; NOOPT: [[BB2]]:80; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)81; NOOPT-NEXT: br label %[[BB3]]82; NOOPT: [[BB3]]:83; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)84; NOOPT-NEXT: ret void85;86; OPT-WAVE32-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg64(87; OPT-WAVE32-SAME: ) #[[ATTR2:[0-9]+]] {88; OPT-WAVE32-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)89; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)90; OPT-WAVE32-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]91; OPT-WAVE32: [[BB2]]:92; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)93; OPT-WAVE32-NEXT: br label %[[BB3]]94; OPT-WAVE32: [[BB3]]:95; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)96; OPT-WAVE32-NEXT: ret void97;98; OPT-WAVE64-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg64(99; OPT-WAVE64-SAME: ) #[[ATTR2:[0-9]+]] {100; OPT-WAVE64-NEXT: call void @llvm.amdgcn.wave.barrier()101; OPT-WAVE64-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3)102; OPT-WAVE64-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3)103; OPT-WAVE64-NEXT: ret void104;105 call void @llvm.amdgcn.s.cluster.barrier()106 ret void107}108