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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=0 | FileCheck --check-prefixes=CHECK,NOOPT %s3; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=1 -mattr=+wavefrontsize32 | FileCheck --check-prefixes=CHECK,OPT-WAVE32 %s4; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=1 -mattr=+wavefrontsize64 | FileCheck --check-prefixes=CHECK,OPT-WAVE64 %s5 6declare void @foo(i1)7 8define amdgpu_kernel void @barrier() {9; CHECK-LABEL: define amdgpu_kernel void @barrier(10; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)12; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)13; CHECK-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)14; CHECK-NEXT: call void @foo(i1 [[ISFIRST]])15; CHECK-NEXT: ret void16;17 call void @llvm.amdgcn.s.barrier.signal(i32 -1)18 call void @llvm.amdgcn.s.barrier.wait(i16 -1)19 %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)20 call void @foo(i1 %isfirst)21 ret void22}23 24define amdgpu_kernel void @barrier_32threads() "amdgpu-flat-work-group-size"="32,32" {25; NOOPT-LABEL: define amdgpu_kernel void @barrier_32threads(26; NOOPT-SAME: ) #[[ATTR1:[0-9]+]] {27; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)28; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)29; NOOPT-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)30; NOOPT-NEXT: call void @foo(i1 [[ISFIRST]])31; NOOPT-NEXT: ret void32;33; OPT-WAVE32-LABEL: define amdgpu_kernel void @barrier_32threads(34; OPT-WAVE32-SAME: ) #[[ATTR1:[0-9]+]] {35; OPT-WAVE32-NEXT: call void @llvm.amdgcn.wave.barrier()36; OPT-WAVE32-NEXT: call void @foo(i1 true)37; OPT-WAVE32-NEXT: ret void38;39; OPT-WAVE64-LABEL: define amdgpu_kernel void @barrier_32threads(40; OPT-WAVE64-SAME: ) #[[ATTR1:[0-9]+]] {41; OPT-WAVE64-NEXT: call void @llvm.amdgcn.wave.barrier()42; OPT-WAVE64-NEXT: call void @foo(i1 true)43; OPT-WAVE64-NEXT: ret void44;45 call void @llvm.amdgcn.s.barrier.signal(i32 -1)46 call void @llvm.amdgcn.s.barrier.wait(i16 -1)47 %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)48 call void @foo(i1 %isfirst)49 ret void50}51 52define amdgpu_kernel void @barrier_64threads() "amdgpu-flat-work-group-size"="64,64" {53; NOOPT-LABEL: define amdgpu_kernel void @barrier_64threads(54; NOOPT-SAME: ) #[[ATTR2:[0-9]+]] {55; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)56; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)57; NOOPT-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)58; NOOPT-NEXT: call void @foo(i1 [[ISFIRST]])59; NOOPT-NEXT: ret void60;61; OPT-WAVE32-LABEL: define amdgpu_kernel void @barrier_64threads(62; OPT-WAVE32-SAME: ) #[[ATTR2:[0-9]+]] {63; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)64; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)65; OPT-WAVE32-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)66; OPT-WAVE32-NEXT: call void @foo(i1 [[ISFIRST]])67; OPT-WAVE32-NEXT: ret void68;69; OPT-WAVE64-LABEL: define amdgpu_kernel void @barrier_64threads(70; OPT-WAVE64-SAME: ) #[[ATTR2:[0-9]+]] {71; OPT-WAVE64-NEXT: call void @llvm.amdgcn.wave.barrier()72; OPT-WAVE64-NEXT: call void @foo(i1 true)73; OPT-WAVE64-NEXT: ret void74;75 call void @llvm.amdgcn.s.barrier.signal(i32 -1)76 call void @llvm.amdgcn.s.barrier.wait(i16 -1)77 %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)78 call void @foo(i1 %isfirst)79 ret void80}81