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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals2; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -o - -passes=amdgpu-lower-kernel-arguments %s | FileCheck -check-prefixes=GCN,HSA %s3; RUN: opt -mtriple=amdgcn-- -S -o - -passes=amdgpu-lower-kernel-arguments %s | FileCheck -check-prefixes=GCN,MESA %s4 5declare void @llvm.fake.use(...)6 7define amdgpu_kernel void @kern_noargs() {8; GCN-LABEL: @kern_noargs(9; GCN-NEXT:    ret void10;11  ret void12}13 14define amdgpu_kernel void @kern_i8(i8 %arg) #0 {15; HSA-LABEL: @kern_i8(16; HSA-NEXT:    [[KERN_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()17; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 018; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0:![0-9]+]]19; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i820; HSA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 121; HSA-NEXT:    ret void22;23; MESA-LABEL: @kern_i8(24; MESA-NEXT:    [[KERN_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()25; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_KERNARG_SEGMENT]], i64 3626; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0:![0-9]+]]27; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i828; MESA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 129; MESA-NEXT:    ret void30;31  store i8 %arg, ptr addrspace(1) poison, align 132  ret void33}34 35define amdgpu_kernel void @kern_i16(i16 %arg) #0 {36; HSA-LABEL: @kern_i16(37; HSA-NEXT:    [[KERN_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()38; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 039; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]40; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1641; HSA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 142; HSA-NEXT:    ret void43;44; MESA-LABEL: @kern_i16(45; MESA-NEXT:    [[KERN_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()46; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I16_KERNARG_SEGMENT]], i64 3647; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]48; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1649; MESA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 150; MESA-NEXT:    ret void51;52  store i16 %arg, ptr addrspace(1) poison, align 153  ret void54}55 56define amdgpu_kernel void @kern_f16(half %arg) #0 {57; HSA-LABEL: @kern_f16(58; HSA-NEXT:    [[KERN_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()59; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 060; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]61; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1662; HSA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half63; HSA-NEXT:    store half [[ARG_LOAD]], ptr addrspace(1) poison, align 164; HSA-NEXT:    ret void65;66; MESA-LABEL: @kern_f16(67; MESA-NEXT:    [[KERN_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()68; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F16_KERNARG_SEGMENT]], i64 3669; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]70; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1671; MESA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i16 [[TMP2]] to half72; MESA-NEXT:    store half [[ARG_LOAD]], ptr addrspace(1) poison, align 173; MESA-NEXT:    ret void74;75  store half %arg, ptr addrspace(1) poison, align 176  ret void77}78 79define amdgpu_kernel void @kern_zeroext_i8(i8 zeroext %arg) #0 {80; HSA-LABEL: @kern_zeroext_i8(81; HSA-NEXT:    [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()82; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 083; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]84; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i885; HSA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 186; HSA-NEXT:    ret void87;88; MESA-LABEL: @kern_zeroext_i8(89; MESA-NEXT:    [[KERN_ZEROEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()90; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I8_KERNARG_SEGMENT]], i64 3691; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]92; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i893; MESA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 194; MESA-NEXT:    ret void95;96  store i8 %arg, ptr addrspace(1) poison, align 197  ret void98}99 100define amdgpu_kernel void @kern_zeroext_i16(i16 zeroext %arg) #0 {101; HSA-LABEL: @kern_zeroext_i16(102; HSA-NEXT:    [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()103; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 0104; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]105; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16106; HSA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1107; HSA-NEXT:    ret void108;109; MESA-LABEL: @kern_zeroext_i16(110; MESA-NEXT:    [[KERN_ZEROEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()111; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ZEROEXT_I16_KERNARG_SEGMENT]], i64 36112; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]113; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16114; MESA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1115; MESA-NEXT:    ret void116;117  store i16 %arg, ptr addrspace(1) poison, align 1118  ret void119}120 121define amdgpu_kernel void @kern_signext_i8(i8 signext %arg) #0 {122; HSA-LABEL: @kern_signext_i8(123; HSA-NEXT:    [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()124; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 0125; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]126; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8127; HSA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1128; HSA-NEXT:    ret void129;130; MESA-LABEL: @kern_signext_i8(131; MESA-NEXT:    [[KERN_SIGNEXT_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()132; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I8_KERNARG_SEGMENT]], i64 36133; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]134; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8135; MESA-NEXT:    store i8 [[TMP2]], ptr addrspace(1) poison, align 1136; MESA-NEXT:    ret void137;138  store i8 %arg, ptr addrspace(1) poison, align 1139  ret void140}141 142define amdgpu_kernel void @kern_signext_i16(i16 signext %arg) #0 {143; HSA-LABEL: @kern_signext_i16(144; HSA-NEXT:    [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()145; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 0146; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]147; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16148; HSA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1149; HSA-NEXT:    ret void150;151; MESA-LABEL: @kern_signext_i16(152; MESA-NEXT:    [[KERN_SIGNEXT_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()153; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_SIGNEXT_I16_KERNARG_SEGMENT]], i64 36154; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]155; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16156; MESA-NEXT:    store i16 [[TMP2]], ptr addrspace(1) poison, align 1157; MESA-NEXT:    ret void158;159  store i16 %arg, ptr addrspace(1) poison, align 1160  ret void161}162 163define amdgpu_kernel void @kern_i8_i8(i8 %arg0, i8 %arg1) {164; HSA-LABEL: @kern_i8_i8(165; HSA-NEXT:    [[KERN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()166; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0167; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]168; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8169; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 0170; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]171; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8172; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8173; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1174; HSA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1175; HSA-NEXT:    ret void176;177; MESA-LABEL: @kern_i8_i8(178; MESA-NEXT:    [[KERN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()179; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36180; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]181; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8182; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I8_I8_KERNARG_SEGMENT]], i64 36183; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]184; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8185; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8186; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1187; MESA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1188; MESA-NEXT:    ret void189;190  store volatile i8 %arg0, ptr addrspace(1) poison, align 1191  store volatile i8 %arg1, ptr addrspace(1) poison, align 1192  ret void193}194 195define amdgpu_kernel void @kern_v3i8(<3 x i8> %arg) {196; HSA-LABEL: @kern_v3i8(197; HSA-NEXT:    [[KERN_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()198; HSA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 0199; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]200; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24201; HSA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>202; HSA-NEXT:    store <3 x i8> [[ARG_LOAD]], ptr addrspace(1) poison, align 4203; HSA-NEXT:    ret void204;205; MESA-LABEL: @kern_v3i8(206; MESA-NEXT:    [[KERN_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()207; MESA-NEXT:    [[ARG_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I8_KERNARG_SEGMENT]], i64 36208; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]209; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24210; MESA-NEXT:    [[ARG_LOAD:%.*]] = bitcast i24 [[TMP2]] to <3 x i8>211; MESA-NEXT:    store <3 x i8> [[ARG_LOAD]], ptr addrspace(1) poison, align 4212; MESA-NEXT:    ret void213;214  store <3 x i8> %arg, ptr addrspace(1) poison, align 4215  ret void216}217 218define amdgpu_kernel void @kern_i24(i24 %arg0) {219; HSA-LABEL: @kern_i24(220; HSA-NEXT:    [[KERN_I24_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()221; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 0222; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]223; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24224; HSA-NEXT:    store i24 [[TMP2]], ptr addrspace(1) poison, align 4225; HSA-NEXT:    ret void226;227; MESA-LABEL: @kern_i24(228; MESA-NEXT:    [[KERN_I24_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()229; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I24_KERNARG_SEGMENT]], i64 36230; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]231; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i24232; MESA-NEXT:    store i24 [[TMP2]], ptr addrspace(1) poison, align 4233; MESA-NEXT:    ret void234;235  store i24 %arg0, ptr addrspace(1) poison236  ret void237}238 239define amdgpu_kernel void @kern_i32(i32 %arg0) {240; HSA-LABEL: @kern_i32(241; HSA-NEXT:    [[KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()242; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 0243; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]244; HSA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4245; HSA-NEXT:    ret void246;247; MESA-LABEL: @kern_i32(248; MESA-NEXT:    [[KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()249; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_KERNARG_SEGMENT]], i64 36250; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]251; MESA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4252; MESA-NEXT:    ret void253;254  store i32 %arg0, ptr addrspace(1) poison255  ret void256}257 258define amdgpu_kernel void @kern_range_noundef_i32(i32 noundef range(i32 0, 8) %arg0) {259; HSA-LABEL: @kern_range_noundef_i32(260; HSA-NEXT:    [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()261; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT]], i64 0262; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !range [[RNG1:![0-9]+]], !invariant.load [[META0]], !noundef [[META0]]263; HSA-NEXT:    call void (...) @llvm.fake.use(i32 [[ARG0_LOAD]])264; HSA-NEXT:    ret void265;266; MESA-LABEL: @kern_range_noundef_i32(267; MESA-NEXT:    [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()268; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_RANGE_NOUNDEF_I32_KERNARG_SEGMENT]], i64 36269; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !range [[RNG1:![0-9]+]], !invariant.load [[META0]], !noundef [[META0]]270; MESA-NEXT:    call void (...) @llvm.fake.use(i32 [[ARG0_LOAD]])271; MESA-NEXT:    ret void272;273  call void (...) @llvm.fake.use(i32 %arg0)274  ret void275}276 277define amdgpu_kernel void @kern_f32(float %arg0) {278; HSA-LABEL: @kern_f32(279; HSA-NEXT:    [[KERN_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()280; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 0281; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]282; HSA-NEXT:    store float [[ARG0_LOAD]], ptr addrspace(1) poison, align 4283; HSA-NEXT:    ret void284;285; MESA-LABEL: @kern_f32(286; MESA-NEXT:    [[KERN_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()287; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_F32_KERNARG_SEGMENT]], i64 36288; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]289; MESA-NEXT:    store float [[ARG0_LOAD]], ptr addrspace(1) poison, align 4290; MESA-NEXT:    ret void291;292  store float %arg0, ptr addrspace(1) poison293  ret void294}295 296define amdgpu_kernel void @kern_v3i32(<3 x i32> %arg0) {297; HSA-LABEL: @kern_v3i32(298; HSA-NEXT:    [[KERN_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()299; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 0300; HSA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]301; HSA-NEXT:    [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>302; HSA-NEXT:    store <3 x i32> [[ARG0_LOAD]], ptr addrspace(1) poison, align 4303; HSA-NEXT:    ret void304;305; MESA-LABEL: @kern_v3i32(306; MESA-NEXT:    [[KERN_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()307; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V3I32_KERNARG_SEGMENT]], i64 36308; MESA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]309; MESA-NEXT:    [[ARG0_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>310; MESA-NEXT:    store <3 x i32> [[ARG0_LOAD]], ptr addrspace(1) poison, align 4311; MESA-NEXT:    ret void312;313  store <3 x i32> %arg0, ptr addrspace(1) poison, align 4314  ret void315}316 317define amdgpu_kernel void @kern_v8i32(<8 x i32> %arg) #0 {318; HSA-LABEL: @kern_v8i32(319; HSA-NEXT:    [[KERN_V8I32_KERNARG_SEGMENT:%.*]] = call nonnull align 32 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()320; HSA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 0321; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i32>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]322; HSA-NEXT:    store <8 x i32> [[ARG_LOAD]], ptr addrspace(1) poison, align 32323; HSA-NEXT:    ret void324;325; MESA-LABEL: @kern_v8i32(326; MESA-NEXT:    [[KERN_V8I32_KERNARG_SEGMENT:%.*]] = call nonnull align 32 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()327; MESA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I32_KERNARG_SEGMENT]], i64 36328; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i32>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]329; MESA-NEXT:    store <8 x i32> [[ARG_LOAD]], ptr addrspace(1) poison, align 32330; MESA-NEXT:    ret void331;332  store <8 x i32> %arg, ptr addrspace(1) poison333  ret void334}335 336define amdgpu_kernel void @kern_v8i64(<8 x i64> %arg) #0 {337; HSA-LABEL: @kern_v8i64(338; HSA-NEXT:    [[KERN_V8I64_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(320) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()339; HSA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 0340; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]341; HSA-NEXT:    store <8 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 64342; HSA-NEXT:    ret void343;344; MESA-LABEL: @kern_v8i64(345; MESA-NEXT:    [[KERN_V8I64_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(320) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()346; MESA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V8I64_KERNARG_SEGMENT]], i64 36347; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <8 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]348; MESA-NEXT:    store <8 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 64349; MESA-NEXT:    ret void350;351  store <8 x i64> %arg, ptr addrspace(1) poison352  ret void353}354 355define amdgpu_kernel void @kern_v16i64(<16 x i64> %arg) #0 {356; HSA-LABEL: @kern_v16i64(357; HSA-NEXT:    [[KERN_V16I64_KERNARG_SEGMENT:%.*]] = call nonnull align 128 dereferenceable(384) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()358; HSA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 0359; HSA-NEXT:    [[ARG_LOAD:%.*]] = load <16 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]360; HSA-NEXT:    store <16 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 128361; HSA-NEXT:    ret void362;363; MESA-LABEL: @kern_v16i64(364; MESA-NEXT:    [[KERN_V16I64_KERNARG_SEGMENT:%.*]] = call nonnull align 128 dereferenceable(384) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()365; MESA-NEXT:    [[ARG_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_V16I64_KERNARG_SEGMENT]], i64 36366; MESA-NEXT:    [[ARG_LOAD:%.*]] = load <16 x i64>, ptr addrspace(4) [[ARG_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]367; MESA-NEXT:    store <16 x i64> [[ARG_LOAD]], ptr addrspace(1) poison, align 128368; MESA-NEXT:    ret void369;370  store <16 x i64> %arg, ptr addrspace(1) poison371  ret void372}373 374define amdgpu_kernel void @kern_i32_v3i32(i32 %arg0, <3 x i32> %arg1) {375; HSA-LABEL: @kern_i32_v3i32(376; HSA-NEXT:    [[KERN_I32_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()377; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 0378; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]379; HSA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 16380; HSA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]381; HSA-NEXT:    [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>382; HSA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4383; HSA-NEXT:    store <3 x i32> [[ARG1_LOAD]], ptr addrspace(1) poison, align 4384; HSA-NEXT:    ret void385;386; MESA-LABEL: @kern_i32_v3i32(387; MESA-NEXT:    [[KERN_I32_V3I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()388; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 36389; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]390; MESA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_I32_V3I32_KERNARG_SEGMENT]], i64 52391; MESA-NEXT:    [[TMP1:%.*]] = load <4 x i32>, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]392; MESA-NEXT:    [[ARG1_LOAD:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>393; MESA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4394; MESA-NEXT:    store <3 x i32> [[ARG1_LOAD]], ptr addrspace(1) poison, align 4395; MESA-NEXT:    ret void396;397  store i32 %arg0, ptr addrspace(1) poison398  store <3 x i32> %arg1, ptr addrspace(1) poison, align 4399  ret void400}401 402%struct.a = type { i32, i8, [4 x i8] }403%struct.b.packed = type { i8, i32, [3 x i16], <2 x double> }404 405define amdgpu_kernel void @kern_struct_a(%struct.a %arg0) {406; HSA-LABEL: @kern_struct_a(407; HSA-NEXT:    [[KERN_STRUCT_A_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()408; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 0409; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_A:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]410; HSA-NEXT:    store [[STRUCT_A]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 4411; HSA-NEXT:    ret void412;413; MESA-LABEL: @kern_struct_a(414; MESA-NEXT:    [[KERN_STRUCT_A_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()415; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_A_KERNARG_SEGMENT]], i64 36416; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_A:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]417; MESA-NEXT:    store [[STRUCT_A]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 4418; MESA-NEXT:    ret void419;420  store %struct.a %arg0, ptr addrspace(1) poison421  ret void422}423 424define amdgpu_kernel void @kern_struct_b_packed(%struct.b.packed %arg0) #0 {425; HSA-LABEL: @kern_struct_b_packed(426; HSA-NEXT:    [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()427; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 0428; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_B_PACKED:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]429; HSA-NEXT:    store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 16430; HSA-NEXT:    ret void431;432; MESA-LABEL: @kern_struct_b_packed(433; MESA-NEXT:    [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(288) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()434; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_STRUCT_B_PACKED_KERNARG_SEGMENT]], i64 36435; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load [[STRUCT_B_PACKED:%.*]], ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]436; MESA-NEXT:    store [[STRUCT_B_PACKED]] [[ARG0_LOAD]], ptr addrspace(1) poison, align 16437; MESA-NEXT:    ret void438;439  store %struct.b.packed %arg0, ptr addrspace(1) poison440  ret void441}442 443define amdgpu_kernel void @kern_implicit_arg_num_bytes(i32 %arg0) #1 {444; HSA-LABEL: @kern_implicit_arg_num_bytes(445; HSA-NEXT:    [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(48) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()446; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT]], i64 0447; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]448; HSA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4449; HSA-NEXT:    ret void450;451; MESA-LABEL: @kern_implicit_arg_num_bytes(452; MESA-NEXT:    [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(44) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()453; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_IMPLICIT_ARG_NUM_BYTES_KERNARG_SEGMENT]], i64 36454; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]455; MESA-NEXT:    store i32 [[ARG0_LOAD]], ptr addrspace(1) poison, align 4456; MESA-NEXT:    ret void457;458  store i32 %arg0, ptr addrspace(1) poison459  ret void460}461 462define amdgpu_kernel void @kernel_implicitarg_no_struct_align(<16 x i32>, i32 %arg1) #1 {463; HSA-LABEL: @kernel_implicitarg_no_struct_align(464; HSA-NEXT:    [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(112) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()465; HSA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT]], i64 64466; HSA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]467; HSA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 4468; HSA-NEXT:    ret void469;470; MESA-LABEL: @kernel_implicitarg_no_struct_align(471; MESA-NEXT:    [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(108) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()472; MESA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERNEL_IMPLICITARG_NO_STRUCT_ALIGN_KERNARG_SEGMENT]], i64 100473; MESA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]474; MESA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 4475; MESA-NEXT:    ret void476;477  store i32 %arg1, ptr addrspace(1) poison478  ret void479}480 481define amdgpu_kernel void @kern_lds_ptr(ptr addrspace(3) %lds) #0 {482; HSA-LABEL: @kern_lds_ptr(483; HSA-NEXT:    [[KERN_LDS_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()484; HSA-NEXT:    [[LDS_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 0485; HSA-NEXT:    [[LDS_LOAD:%.*]] = load ptr addrspace(3), ptr addrspace(4) [[LDS_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]486; HSA-NEXT:    store i32 0, ptr addrspace(3) [[LDS_LOAD]], align 4487; HSA-NEXT:    ret void488;489; MESA-LABEL: @kern_lds_ptr(490; MESA-NEXT:    [[KERN_LDS_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()491; MESA-NEXT:    [[LDS_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_LDS_PTR_KERNARG_SEGMENT]], i64 36492; MESA-NEXT:    [[LDS_LOAD:%.*]] = load ptr addrspace(3), ptr addrspace(4) [[LDS_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]493; MESA-NEXT:    store i32 0, ptr addrspace(3) [[LDS_LOAD]], align 4494; MESA-NEXT:    ret void495;496  store i32 0, ptr addrspace(3) %lds, align 4497  ret void498}499 500define amdgpu_kernel void @kern_lds_ptr_si(ptr addrspace(3) %lds) #2 {501; HSA-LABEL: @kern_lds_ptr_si(502; HSA-NEXT:    [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()503; HSA-NEXT:    store i32 0, ptr addrspace(3) [[LDS:%.*]], align 4504; HSA-NEXT:    ret void505;506; MESA-LABEL: @kern_lds_ptr_si(507; MESA-NEXT:    [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()508; MESA-NEXT:    store i32 0, ptr addrspace(3) [[LDS:%.*]], align 4509; MESA-NEXT:    ret void510;511  store i32 0, ptr addrspace(3) %lds, align 4512  ret void513}514 515define amdgpu_kernel void @kern_realign_i8_i8(i8 %arg0, i8 %arg1) #0 {516; HSA-LABEL: @kern_realign_i8_i8(517; HSA-NEXT:    [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()518; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0519; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]520; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8521; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 0522; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]523; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8524; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8525; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1526; HSA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1527; HSA-NEXT:    ret void528;529; MESA-LABEL: @kern_realign_i8_i8(530; MESA-NEXT:    [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()531; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36532; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]533; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8534; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_KERNARG_SEGMENT]], i64 36535; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]536; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8537; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8538; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1539; MESA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1540; MESA-NEXT:    ret void541;542  store volatile i8 %arg0, ptr addrspace(1) poison543  store volatile i8 %arg1, ptr addrspace(1) poison544  ret void545}546 547define amdgpu_kernel void @kern_realign_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2) #0 {548; HSA-LABEL: @kern_realign_i8_i8_i8(549; HSA-NEXT:    [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()550; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0551; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]552; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8553; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0554; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]555; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8556; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8557; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 0558; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]559; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16560; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8561; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1562; HSA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1563; HSA-NEXT:    store volatile i8 [[TMP8]], ptr addrspace(1) poison, align 1564; HSA-NEXT:    ret void565;566; MESA-LABEL: @kern_realign_i8_i8_i8(567; MESA-NEXT:    [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()568; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36569; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]570; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8571; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36572; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]573; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8574; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8575; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_KERNARG_SEGMENT]], i64 36576; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]577; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16578; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8579; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1580; MESA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1581; MESA-NEXT:    store volatile i8 [[TMP8]], ptr addrspace(1) poison, align 1582; MESA-NEXT:    ret void583;584  store volatile i8 %arg0, ptr addrspace(1) poison585  store volatile i8 %arg1, ptr addrspace(1) poison586  store volatile i8 %arg2, ptr addrspace(1) poison587  ret void588}589 590define amdgpu_kernel void @kern_realign_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3) #0 {591; HSA-LABEL: @kern_realign_i8_i8_i8_i8(592; HSA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()593; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0594; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]595; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8596; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0597; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]598; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8599; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8600; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0601; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]602; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16603; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8604; HSA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0605; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]606; HSA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24607; HSA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8608; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1609; HSA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1610; HSA-NEXT:    store volatile i8 [[TMP8]], ptr addrspace(1) poison, align 1611; HSA-NEXT:    store volatile i8 [[TMP11]], ptr addrspace(1) poison, align 1612; HSA-NEXT:    ret void613;614; MESA-LABEL: @kern_realign_i8_i8_i8_i8(615; MESA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()616; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36617; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]618; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8619; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36620; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]621; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8622; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8623; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36624; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]625; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16626; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8627; MESA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36628; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]629; MESA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24630; MESA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8631; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1632; MESA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1633; MESA-NEXT:    store volatile i8 [[TMP8]], ptr addrspace(1) poison, align 1634; MESA-NEXT:    store volatile i8 [[TMP11]], ptr addrspace(1) poison, align 1635; MESA-NEXT:    ret void636;637  store volatile i8 %arg0, ptr addrspace(1) poison638  store volatile i8 %arg1, ptr addrspace(1) poison639  store volatile i8 %arg2, ptr addrspace(1) poison640  store volatile i8 %arg3, ptr addrspace(1) poison641  ret void642}643 644define amdgpu_kernel void @kern_realign_i8_v3i8(i8 %arg0, <3 x i8> %arg1) #0 {645; HSA-LABEL: @kern_realign_i8_v3i8(646; HSA-NEXT:    [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()647; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 0648; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]649; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8650; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 4651; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]652; HSA-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24653; HSA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>654; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1655; HSA-NEXT:    store volatile <3 x i8> [[ARG1_LOAD]], ptr addrspace(1) poison, align 4656; HSA-NEXT:    ret void657;658; MESA-LABEL: @kern_realign_i8_v3i8(659; MESA-NEXT:    [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()660; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 36661; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]662; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8663; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_V3I8_KERNARG_SEGMENT]], i64 40664; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]665; MESA-NEXT:    [[TMP4:%.*]] = trunc i32 [[TMP3]] to i24666; MESA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i24 [[TMP4]] to <3 x i8>667; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1668; MESA-NEXT:    store volatile <3 x i8> [[ARG1_LOAD]], ptr addrspace(1) poison, align 4669; MESA-NEXT:    ret void670;671  store volatile i8 %arg0, ptr addrspace(1) poison672  store volatile <3 x i8> %arg1, ptr addrspace(1) poison673  ret void674}675 676define amdgpu_kernel void @kern_realign_i8_i16(i8 %arg0, i16 %arg1) #0 {677; HSA-LABEL: @kern_realign_i8_i16(678; HSA-NEXT:    [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()679; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0680; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]681; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8682; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 0683; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]684; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16685; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16686; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1687; HSA-NEXT:    store volatile i16 [[TMP5]], ptr addrspace(1) poison, align 2688; HSA-NEXT:    ret void689;690; MESA-LABEL: @kern_realign_i8_i16(691; MESA-NEXT:    [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()692; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36693; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]694; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8695; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I16_KERNARG_SEGMENT]], i64 36696; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]697; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16698; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16699; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1700; MESA-NEXT:    store volatile i16 [[TMP5]], ptr addrspace(1) poison, align 2701; MESA-NEXT:    ret void702;703  store volatile i8 %arg0, ptr addrspace(1) poison704  store volatile i16 %arg1, ptr addrspace(1) poison705  ret void706}707 708define amdgpu_kernel void @kern_realign_i1_i1(i1 %arg0, i1 %arg1) #0 {709; HSA-LABEL: @kern_realign_i1_i1(710; HSA-NEXT:    [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()711; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0712; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]713; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1714; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 0715; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]716; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8717; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1718; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1719; HSA-NEXT:    store volatile i1 [[TMP5]], ptr addrspace(1) poison, align 1720; HSA-NEXT:    ret void721;722; MESA-LABEL: @kern_realign_i1_i1(723; MESA-NEXT:    [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()724; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36725; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]726; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1727; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_KERNARG_SEGMENT]], i64 36728; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]729; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8730; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1731; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1732; MESA-NEXT:    store volatile i1 [[TMP5]], ptr addrspace(1) poison, align 1733; MESA-NEXT:    ret void734;735  store volatile i1 %arg0, ptr addrspace(1) poison736  store volatile i1 %arg1, ptr addrspace(1) poison737  ret void738}739 740define amdgpu_kernel void @kern_realign_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2) #0 {741; HSA-LABEL: @kern_realign_i1_i1_i1(742; HSA-NEXT:    [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()743; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0744; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]745; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1746; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0747; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]748; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8749; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1750; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 0751; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]752; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16753; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1754; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1755; HSA-NEXT:    store volatile i1 [[TMP5]], ptr addrspace(1) poison, align 1756; HSA-NEXT:    store volatile i1 [[TMP8]], ptr addrspace(1) poison, align 1757; HSA-NEXT:    ret void758;759; MESA-LABEL: @kern_realign_i1_i1_i1(760; MESA-NEXT:    [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()761; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36762; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]763; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1764; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36765; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]766; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8767; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1768; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_KERNARG_SEGMENT]], i64 36769; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]770; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16771; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1772; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1773; MESA-NEXT:    store volatile i1 [[TMP5]], ptr addrspace(1) poison, align 1774; MESA-NEXT:    store volatile i1 [[TMP8]], ptr addrspace(1) poison, align 1775; MESA-NEXT:    ret void776;777  store volatile i1 %arg0, ptr addrspace(1) poison778  store volatile i1 %arg1, ptr addrspace(1) poison779  store volatile i1 %arg2, ptr addrspace(1) poison780  ret void781}782 783define amdgpu_kernel void @kern_realign_i1_i1_i1_i1(i1 %arg0, i1 %arg1, i1 %arg2, i1 %arg3) #0 {784; HSA-LABEL: @kern_realign_i1_i1_i1_i1(785; HSA-NEXT:    [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()786; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0787; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]788; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1789; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0790; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]791; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8792; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1793; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0794; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]795; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16796; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1797; HSA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 0798; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]799; HSA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24800; HSA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i1801; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1802; HSA-NEXT:    store volatile i1 [[TMP5]], ptr addrspace(1) poison, align 1803; HSA-NEXT:    store volatile i1 [[TMP8]], ptr addrspace(1) poison, align 1804; HSA-NEXT:    store volatile i1 [[TMP11]], ptr addrspace(1) poison, align 1805; HSA-NEXT:    ret void806;807; MESA-LABEL: @kern_realign_i1_i1_i1_i1(808; MESA-NEXT:    [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()809; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36810; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]811; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1812; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36813; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]814; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8815; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i1816; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36817; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]818; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16819; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i1820; MESA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I1_I1_I1_KERNARG_SEGMENT]], i64 36821; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]822; MESA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24823; MESA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i1824; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1825; MESA-NEXT:    store volatile i1 [[TMP5]], ptr addrspace(1) poison, align 1826; MESA-NEXT:    store volatile i1 [[TMP8]], ptr addrspace(1) poison, align 1827; MESA-NEXT:    store volatile i1 [[TMP11]], ptr addrspace(1) poison, align 1828; MESA-NEXT:    ret void829;830  store volatile i1 %arg0, ptr addrspace(1) poison831  store volatile i1 %arg1, ptr addrspace(1) poison832  store volatile i1 %arg2, ptr addrspace(1) poison833  store volatile i1 %arg3, ptr addrspace(1) poison834  ret void835}836 837define amdgpu_kernel void @kern_realign_i1_v3i1(i1 %arg0, <3 x i1> %arg1) #0 {838; HSA-LABEL: @kern_realign_i1_v3i1(839; HSA-NEXT:    [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()840; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0841; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]842; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1843; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 0844; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]845; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8846; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3847; HSA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>848; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1849; HSA-NEXT:    store volatile <3 x i1> [[ARG1_LOAD]], ptr addrspace(1) poison, align 1850; HSA-NEXT:    ret void851;852; MESA-LABEL: @kern_realign_i1_v3i1(853; MESA-NEXT:    [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()854; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36855; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]856; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1857; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_V3I1_KERNARG_SEGMENT]], i64 36858; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]859; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8860; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i3861; MESA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i3 [[TMP5]] to <3 x i1>862; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1863; MESA-NEXT:    store volatile <3 x i1> [[ARG1_LOAD]], ptr addrspace(1) poison, align 1864; MESA-NEXT:    ret void865;866  store volatile i1 %arg0, ptr addrspace(1) poison867  store volatile <3 x i1> %arg1, ptr addrspace(1) poison868  ret void869}870 871define amdgpu_kernel void @kern_realign_i1_i16(i1 %arg0, i16 %arg1) #0 {872; HSA-LABEL: @kern_realign_i1_i16(873; HSA-NEXT:    [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()874; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0875; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]876; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1877; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 0878; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]879; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16880; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16881; HSA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1882; HSA-NEXT:    store volatile i16 [[TMP5]], ptr addrspace(1) poison, align 2883; HSA-NEXT:    ret void884;885; MESA-LABEL: @kern_realign_i1_i16(886; MESA-NEXT:    [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()887; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36888; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]889; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i1890; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I1_I16_KERNARG_SEGMENT]], i64 36891; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]892; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 16893; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i16894; MESA-NEXT:    store volatile i1 [[TMP2]], ptr addrspace(1) poison, align 1895; MESA-NEXT:    store volatile i16 [[TMP5]], ptr addrspace(1) poison, align 2896; MESA-NEXT:    ret void897;898  store volatile i1 %arg0, ptr addrspace(1) poison899  store volatile i16 %arg1, ptr addrspace(1) poison900  ret void901}902 903define amdgpu_kernel void @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(i8 %arg0, i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, i8 %arg5, i8 %arg6, i8 %arg7) #0 {904; HSA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(905; HSA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()906; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0907; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]908; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8909; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0910; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]911; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8912; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8913; HSA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0914; HSA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]915; HSA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16916; HSA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8917; HSA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 0918; HSA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]919; HSA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24920; HSA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8921; HSA-NEXT:    [[ARG5_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 4922; HSA-NEXT:    [[TMP12:%.*]] = load i32, ptr addrspace(4) [[ARG5_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]923; HSA-NEXT:    [[TMP13:%.*]] = lshr i32 [[TMP12]], 8924; HSA-NEXT:    [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8925; HSA-NEXT:    [[ARG6_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 4926; HSA-NEXT:    [[TMP15:%.*]] = load i32, ptr addrspace(4) [[ARG6_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]927; HSA-NEXT:    [[TMP16:%.*]] = lshr i32 [[TMP15]], 16928; HSA-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8929; HSA-NEXT:    [[ARG7_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 4930; HSA-NEXT:    [[TMP18:%.*]] = load i32, ptr addrspace(4) [[ARG7_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]931; HSA-NEXT:    [[TMP19:%.*]] = lshr i32 [[TMP18]], 24932; HSA-NEXT:    [[TMP20:%.*]] = trunc i32 [[TMP19]] to i8933; HSA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1934; HSA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1935; HSA-NEXT:    store volatile i8 [[TMP8]], ptr addrspace(1) poison, align 1936; HSA-NEXT:    store volatile i8 [[TMP11]], ptr addrspace(1) poison, align 1937; HSA-NEXT:    store volatile i8 [[TMP14]], ptr addrspace(1) poison, align 1938; HSA-NEXT:    store volatile i8 [[TMP17]], ptr addrspace(1) poison, align 1939; HSA-NEXT:    store volatile i8 [[TMP20]], ptr addrspace(1) poison, align 1940; HSA-NEXT:    ret void941;942; MESA-LABEL: @kern_realign_i8_i8_i8_i8_i8_i8_i8_i8(943; MESA-NEXT:    [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()944; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36945; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]946; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8947; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36948; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]949; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 8950; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8951; MESA-NEXT:    [[ARG2_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36952; MESA-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(4) [[ARG2_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]953; MESA-NEXT:    [[TMP7:%.*]] = lshr i32 [[TMP6]], 16954; MESA-NEXT:    [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8955; MESA-NEXT:    [[ARG3_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 36956; MESA-NEXT:    [[TMP9:%.*]] = load i32, ptr addrspace(4) [[ARG3_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]957; MESA-NEXT:    [[TMP10:%.*]] = lshr i32 [[TMP9]], 24958; MESA-NEXT:    [[TMP11:%.*]] = trunc i32 [[TMP10]] to i8959; MESA-NEXT:    [[ARG5_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 40960; MESA-NEXT:    [[TMP12:%.*]] = load i32, ptr addrspace(4) [[ARG5_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]961; MESA-NEXT:    [[TMP13:%.*]] = lshr i32 [[TMP12]], 8962; MESA-NEXT:    [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8963; MESA-NEXT:    [[ARG6_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 40964; MESA-NEXT:    [[TMP15:%.*]] = load i32, ptr addrspace(4) [[ARG6_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]965; MESA-NEXT:    [[TMP16:%.*]] = lshr i32 [[TMP15]], 16966; MESA-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8967; MESA-NEXT:    [[ARG7_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_I8_I8_I8_I8_I8_I8_I8_I8_KERNARG_SEGMENT]], i64 40968; MESA-NEXT:    [[TMP18:%.*]] = load i32, ptr addrspace(4) [[ARG7_KERNARG_OFFSET_ALIGN_DOWN]], align 8, !invariant.load [[META0]]969; MESA-NEXT:    [[TMP19:%.*]] = lshr i32 [[TMP18]], 24970; MESA-NEXT:    [[TMP20:%.*]] = trunc i32 [[TMP19]] to i8971; MESA-NEXT:    store volatile i8 [[TMP2]], ptr addrspace(1) poison, align 1972; MESA-NEXT:    store volatile i8 [[TMP5]], ptr addrspace(1) poison, align 1973; MESA-NEXT:    store volatile i8 [[TMP8]], ptr addrspace(1) poison, align 1974; MESA-NEXT:    store volatile i8 [[TMP11]], ptr addrspace(1) poison, align 1975; MESA-NEXT:    store volatile i8 [[TMP14]], ptr addrspace(1) poison, align 1976; MESA-NEXT:    store volatile i8 [[TMP17]], ptr addrspace(1) poison, align 1977; MESA-NEXT:    store volatile i8 [[TMP20]], ptr addrspace(1) poison, align 1978; MESA-NEXT:    ret void979;980  store volatile i8 %arg0, ptr addrspace(1) poison981  store volatile i8 %arg1, ptr addrspace(1) poison982  store volatile i8 %arg2, ptr addrspace(1) poison983  store volatile i8 %arg3, ptr addrspace(1) poison984  store volatile i8 %arg5, ptr addrspace(1) poison985  store volatile i8 %arg6, ptr addrspace(1) poison986  store volatile i8 %arg7, ptr addrspace(1) poison987  ret void988}989 990define amdgpu_kernel void @kern_realign_f16_f16(half %arg0, half %arg1) #0 {991; HSA-LABEL: @kern_realign_f16_f16(992; HSA-NEXT:    [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()993; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0994; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]995; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16996; HSA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half997; HSA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 0998; HSA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]]999; HSA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 161000; HSA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i161001; HSA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half1002; HSA-NEXT:    store volatile half [[ARG0_LOAD]], ptr addrspace(1) poison, align 21003; HSA-NEXT:    store volatile half [[ARG1_LOAD]], ptr addrspace(1) poison, align 21004; HSA-NEXT:    ret void1005;1006; MESA-LABEL: @kern_realign_f16_f16(1007; MESA-NEXT:    [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1008; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 361009; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]1010; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i161011; MESA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half1012; MESA-NEXT:    [[ARG1_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_REALIGN_F16_F16_KERNARG_SEGMENT]], i64 361013; MESA-NEXT:    [[TMP3:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]]1014; MESA-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP3]], 161015; MESA-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i161016; MESA-NEXT:    [[ARG1_LOAD:%.*]] = bitcast i16 [[TMP5]] to half1017; MESA-NEXT:    store volatile half [[ARG0_LOAD]], ptr addrspace(1) poison, align 21018; MESA-NEXT:    store volatile half [[ARG1_LOAD]], ptr addrspace(1) poison, align 21019; MESA-NEXT:    ret void1020;1021  store volatile half %arg0, ptr addrspace(1) poison1022  store volatile half %arg1, ptr addrspace(1) poison1023  ret void1024}1025 1026define amdgpu_kernel void @kern_global_ptr(ptr addrspace(1) %ptr) #0 {1027; HSA-LABEL: @kern_global_ptr(1028; HSA-NEXT:    [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1029; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 01030; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1031; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81032; HSA-NEXT:    ret void1033;1034; MESA-LABEL: @kern_global_ptr(1035; MESA-NEXT:    [[KERN_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1036; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_KERNARG_SEGMENT]], i64 361037; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1038; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81039; MESA-NEXT:    ret void1040;1041  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) poison1042  ret void1043}1044 1045define amdgpu_kernel void @kern_global_ptr_dereferencable(ptr addrspace(1) dereferenceable(42) %ptr) #0 {1046; HSA-LABEL: @kern_global_ptr_dereferencable(1047; HSA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1048; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 01049; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !dereferenceable [[META2:![0-9]+]]1050; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81051; HSA-NEXT:    ret void1052;1053; MESA-LABEL: @kern_global_ptr_dereferencable(1054; MESA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1055; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_KERNARG_SEGMENT]], i64 361056; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !dereferenceable [[META2:![0-9]+]]1057; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81058; MESA-NEXT:    ret void1059;1060  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) poison1061  ret void1062}1063 1064define amdgpu_kernel void @kern_global_ptr_dereferencable_or_null(ptr addrspace(1) dereferenceable_or_null(128) %ptr) #0 {1065; HSA-LABEL: @kern_global_ptr_dereferencable_or_null(1066; HSA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1067; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 01068; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !dereferenceable_or_null [[META3:![0-9]+]]1069; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81070; HSA-NEXT:    ret void1071;1072; MESA-LABEL: @kern_global_ptr_dereferencable_or_null(1073; MESA-NEXT:    [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1074; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_GLOBAL_PTR_DEREFERENCABLE_OR_NULL_KERNARG_SEGMENT]], i64 361075; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !dereferenceable_or_null [[META3:![0-9]+]]1076; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81077; MESA-NEXT:    ret void1078;1079  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) poison1080  ret void1081}1082 1083define amdgpu_kernel void @kern_nonnull_global_ptr(ptr addrspace(1) nonnull %ptr) #0 {1084; HSA-LABEL: @kern_nonnull_global_ptr(1085; HSA-NEXT:    [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1086; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 01087; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !nonnull [[META0]]1088; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81089; HSA-NEXT:    ret void1090;1091; MESA-LABEL: @kern_nonnull_global_ptr(1092; MESA-NEXT:    [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1093; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NONNULL_GLOBAL_PTR_KERNARG_SEGMENT]], i64 361094; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !nonnull [[META0]]1095; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81096; MESA-NEXT:    ret void1097;1098  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) poison1099  ret void1100}1101 1102define amdgpu_kernel void @kern_align32_global_ptr(ptr addrspace(1) align 1024 %ptr) #0 {1103; HSA-LABEL: @kern_align32_global_ptr(1104; HSA-NEXT:    [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1105; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 01106; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !align [[META4:![0-9]+]]1107; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81108; HSA-NEXT:    ret void1109;1110; MESA-LABEL: @kern_align32_global_ptr(1111; MESA-NEXT:    [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1112; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_ALIGN32_GLOBAL_PTR_KERNARG_SEGMENT]], i64 361113; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !align [[META4:![0-9]+]]1114; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) poison, align 81115; MESA-NEXT:    ret void1116;1117  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) poison1118  ret void1119}1120 1121define amdgpu_kernel void @kern_noalias_global_ptr(ptr addrspace(1) noalias %ptr) #0 {1122; GCN-LABEL: @kern_noalias_global_ptr(1123; GCN-NEXT:    [[KERN_NOALIAS_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1124; GCN-NEXT:    store volatile ptr addrspace(1) [[PTR:%.*]], ptr addrspace(1) poison, align 81125; GCN-NEXT:    ret void1126;1127  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) poison1128  ret void1129}1130 1131define amdgpu_kernel void @kern_noalias_global_ptr_x2(ptr addrspace(1) noalias %ptr0, ptr addrspace(1) noalias %ptr1) #0 {1132; GCN-LABEL: @kern_noalias_global_ptr_x2(1133; GCN-NEXT:    [[KERN_NOALIAS_GLOBAL_PTR_X2_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1134; GCN-NEXT:    store volatile ptr addrspace(1) [[PTR0:%.*]], ptr addrspace(1) poison, align 81135; GCN-NEXT:    store volatile ptr addrspace(1) [[PTR1:%.*]], ptr addrspace(1) poison, align 81136; GCN-NEXT:    ret void1137;1138  store volatile ptr addrspace(1) %ptr0, ptr addrspace(1) poison1139  store volatile ptr addrspace(1) %ptr1, ptr addrspace(1) poison1140  ret void1141}1142 1143define amdgpu_kernel void @kern_noundef_global_ptr(ptr addrspace(1) noundef %ptr) #0 {1144; HSA-LABEL: @kern_noundef_global_ptr(1145; HSA-NEXT:    [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1146; HSA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT]], i64 01147; HSA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]1148; HSA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) null, align 81149; HSA-NEXT:    ret void1150;1151; MESA-LABEL: @kern_noundef_global_ptr(1152; MESA-NEXT:    [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1153; MESA-NEXT:    [[PTR_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[KERN_NOUNDEF_GLOBAL_PTR_KERNARG_SEGMENT]], i64 361154; MESA-NEXT:    [[PTR_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[PTR_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]1155; MESA-NEXT:    store volatile ptr addrspace(1) [[PTR_LOAD]], ptr addrspace(1) null, align 81156; MESA-NEXT:    ret void1157;1158  store volatile ptr addrspace(1) %ptr, ptr addrspace(1) null1159  ret void1160}1161 1162define amdgpu_kernel void @struct_i8_i8_arg({i8, i8} %in) #0 {1163; HSA-LABEL: @struct_i8_i8_arg(1164; HSA-NEXT:  entry:1165; HSA-NEXT:    [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1166; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 01167; HSA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i8 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1168; HSA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 01169; HSA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 11170; HSA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 41171; HSA-NEXT:    store volatile i8 [[ELT1]], ptr addrspace(1) null, align 41172; HSA-NEXT:    ret void1173;1174; MESA-LABEL: @struct_i8_i8_arg(1175; MESA-NEXT:  entry:1176; MESA-NEXT:    [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1177; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I8_ARG_KERNARG_SEGMENT]], i64 361178; MESA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i8 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1179; MESA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 01180; MESA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i8 } [[IN_LOAD]], 11181; MESA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 41182; MESA-NEXT:    store volatile i8 [[ELT1]], ptr addrspace(1) null, align 41183; MESA-NEXT:    ret void1184;1185entry:1186  %elt0 = extractvalue {i8, i8} %in, 01187  %elt1 = extractvalue {i8, i8} %in, 11188  store volatile i8 %elt0, ptr addrspace(1) null, align 41189  store volatile i8 %elt1, ptr addrspace(1) null, align 41190  ret void1191}1192 1193define amdgpu_kernel void @struct_i8_i16_arg({i8, i16} %in) #0 {1194; HSA-LABEL: @struct_i8_i16_arg(1195; HSA-NEXT:  entry:1196; HSA-NEXT:    [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1197; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 01198; HSA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i16 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1199; HSA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 01200; HSA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 11201; HSA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 41202; HSA-NEXT:    store volatile i16 [[ELT1]], ptr addrspace(1) null, align 41203; HSA-NEXT:    ret void1204;1205; MESA-LABEL: @struct_i8_i16_arg(1206; MESA-NEXT:  entry:1207; MESA-NEXT:    [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1208; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STRUCT_I8_I16_ARG_KERNARG_SEGMENT]], i64 361209; MESA-NEXT:    [[IN_LOAD:%.*]] = load { i8, i16 }, ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1210; MESA-NEXT:    [[ELT0:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 01211; MESA-NEXT:    [[ELT1:%.*]] = extractvalue { i8, i16 } [[IN_LOAD]], 11212; MESA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 41213; MESA-NEXT:    store volatile i16 [[ELT1]], ptr addrspace(1) null, align 41214; MESA-NEXT:    ret void1215;1216entry:1217  %elt0 = extractvalue {i8, i16} %in, 01218  %elt1 = extractvalue {i8, i16} %in, 11219  store volatile i8 %elt0, ptr addrspace(1) null, align 41220  store volatile i16 %elt1, ptr addrspace(1) null, align 41221  ret void1222}1223 1224define amdgpu_kernel void @array_2xi8_arg([2 x i8] %in) #0 {1225; HSA-LABEL: @array_2xi8_arg(1226; HSA-NEXT:  entry:1227; HSA-NEXT:    [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1228; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 01229; HSA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i8], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1230; HSA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 01231; HSA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 11232; HSA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 41233; HSA-NEXT:    store volatile i8 [[ELT1]], ptr addrspace(1) null, align 41234; HSA-NEXT:    ret void1235;1236; MESA-LABEL: @array_2xi8_arg(1237; MESA-NEXT:  entry:1238; MESA-NEXT:    [[ARRAY_2XI8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1239; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI8_ARG_KERNARG_SEGMENT]], i64 361240; MESA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i8], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1241; MESA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 01242; MESA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i8] [[IN_LOAD]], 11243; MESA-NEXT:    store volatile i8 [[ELT0]], ptr addrspace(1) null, align 41244; MESA-NEXT:    store volatile i8 [[ELT1]], ptr addrspace(1) null, align 41245; MESA-NEXT:    ret void1246;1247entry:1248  %elt0 = extractvalue [2 x i8] %in, 01249  %elt1 = extractvalue [2 x i8] %in, 11250  store volatile i8 %elt0, ptr addrspace(1) null, align 41251  store volatile i8 %elt1, ptr addrspace(1) null, align 41252  ret void1253}1254 1255define amdgpu_kernel void @array_2xi1_arg([2 x i1] %in) #0 {1256; HSA-LABEL: @array_2xi1_arg(1257; HSA-NEXT:  entry:1258; HSA-NEXT:    [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1259; HSA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 01260; HSA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i1], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1261; HSA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 01262; HSA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 11263; HSA-NEXT:    store volatile i1 [[ELT0]], ptr addrspace(1) null, align 41264; HSA-NEXT:    store volatile i1 [[ELT1]], ptr addrspace(1) null, align 41265; HSA-NEXT:    ret void1266;1267; MESA-LABEL: @array_2xi1_arg(1268; MESA-NEXT:  entry:1269; MESA-NEXT:    [[ARRAY_2XI1_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1270; MESA-NEXT:    [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARRAY_2XI1_ARG_KERNARG_SEGMENT]], i64 361271; MESA-NEXT:    [[IN_LOAD:%.*]] = load [2 x i1], ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1272; MESA-NEXT:    [[ELT0:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 01273; MESA-NEXT:    [[ELT1:%.*]] = extractvalue [2 x i1] [[IN_LOAD]], 11274; MESA-NEXT:    store volatile i1 [[ELT0]], ptr addrspace(1) null, align 41275; MESA-NEXT:    store volatile i1 [[ELT1]], ptr addrspace(1) null, align 41276; MESA-NEXT:    ret void1277;1278entry:1279  %elt0 = extractvalue [2 x i1] %in, 01280  %elt1 = extractvalue [2 x i1] %in, 11281  store volatile i1 %elt0, ptr addrspace(1) null, align 41282  store volatile i1 %elt1, ptr addrspace(1) null, align 41283  ret void1284}1285 1286define amdgpu_kernel void @only_empty_struct({} %empty) #0 {1287; GCN-LABEL: @only_empty_struct(1288; GCN-NEXT:    [[ONLY_EMPTY_STRUCT_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1289; GCN-NEXT:    ret void1290;1291  ret void1292}1293 1294define amdgpu_kernel void @empty_struct_with_other({} %empty, i32 %arg1) #0 {1295; HSA-LABEL: @empty_struct_with_other(1296; HSA-NEXT:    [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1297; HSA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 01298; HSA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1299; HSA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 41300; HSA-NEXT:    ret void1301;1302; MESA-LABEL: @empty_struct_with_other(1303; MESA-NEXT:    [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1304; MESA-NEXT:    [[ARG1_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[EMPTY_STRUCT_WITH_OTHER_KERNARG_SEGMENT]], i64 361305; MESA-NEXT:    [[ARG1_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG1_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1306; MESA-NEXT:    store i32 [[ARG1_LOAD]], ptr addrspace(1) poison, align 41307; MESA-NEXT:    ret void1308;1309  store i32 %arg1, ptr addrspace(1) poison1310  ret void1311}1312 1313; Should insert code after the allocas1314define amdgpu_kernel void @static_alloca_kern_i32(i32 %arg0) {1315; HSA-LABEL: @static_alloca_kern_i32(1316; HSA-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)1317; HSA-NEXT:    [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1318; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 01319; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1320; HSA-NEXT:    store volatile i32 [[ARG0_LOAD]], ptr addrspace(5) [[ALLOCA]], align 41321; HSA-NEXT:    ret void1322;1323; MESA-LABEL: @static_alloca_kern_i32(1324; MESA-NEXT:    [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5)1325; MESA-NEXT:    [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1326; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[STATIC_ALLOCA_KERN_I32_KERNARG_SEGMENT]], i64 361327; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1328; MESA-NEXT:    store volatile i32 [[ARG0_LOAD]], ptr addrspace(5) [[ALLOCA]], align 41329; MESA-NEXT:    ret void1330;1331  %alloca = alloca i32, addrspace(5)1332  store volatile i32 %arg0, ptr addrspace(5) %alloca1333  ret void1334}1335 1336; Make sure we don't break the IR if an alloca depends on the1337; kernargs.1338define amdgpu_kernel void @dyn_alloca_kernarg_i32(i32 %n) {1339; HSA-LABEL: @dyn_alloca_kernarg_i32(1340; HSA-NEXT:    [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)1341; HSA-NEXT:    [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1342; HSA-NEXT:    [[N_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 01343; HSA-NEXT:    [[N_LOAD:%.*]] = load i32, ptr addrspace(4) [[N_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1344; HSA-NEXT:    [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)1345; HSA-NEXT:    store volatile i32 0, ptr addrspace(5) [[ALLOCA0]], align 41346; HSA-NEXT:    store volatile i32 1, ptr addrspace(5) [[ALLOCA1]], align 41347; HSA-NEXT:    ret void1348;1349; MESA-LABEL: @dyn_alloca_kernarg_i32(1350; MESA-NEXT:    [[ALLOCA0:%.*]] = alloca i32, align 4, addrspace(5)1351; MESA-NEXT:    [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1352; MESA-NEXT:    [[N_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[DYN_ALLOCA_KERNARG_I32_KERNARG_SEGMENT]], i64 361353; MESA-NEXT:    [[N_LOAD:%.*]] = load i32, ptr addrspace(4) [[N_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1354; MESA-NEXT:    [[ALLOCA1:%.*]] = alloca i32, i32 [[N_LOAD]], align 4, addrspace(5)1355; MESA-NEXT:    store volatile i32 0, ptr addrspace(5) [[ALLOCA0]], align 41356; MESA-NEXT:    store volatile i32 1, ptr addrspace(5) [[ALLOCA1]], align 41357; MESA-NEXT:    ret void1358;1359  %alloca0 = alloca i32, addrspace(5)1360  %alloca1 = alloca i32, i32 %n, addrspace(5)1361  store volatile i32 0, ptr addrspace(5) %alloca01362  store volatile i32 1, ptr addrspace(5) %alloca11363  ret void1364}1365 1366; Byref pointers should only be treated as offsets from kernarg1367define amdgpu_kernel void @byref_constant_i8_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i8) %in.byref) {1368; HSA-LABEL: @byref_constant_i8_arg(1369; HSA-NEXT:    [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1370; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 01371; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1372; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 81373; HSA-NEXT:    [[IN:%.*]] = load i8, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 11374; HSA-NEXT:    [[EXT:%.*]] = zext i8 [[IN]] to i321375; HSA-NEXT:    store i32 [[EXT]], ptr addrspace(1) [[OUT_LOAD]], align 41376; HSA-NEXT:    ret void1377;1378; MESA-LABEL: @byref_constant_i8_arg(1379; MESA-NEXT:    [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1380; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 361381; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1382; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I8_ARG_KERNARG_SEGMENT]], i64 441383; MESA-NEXT:    [[IN:%.*]] = load i8, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 11384; MESA-NEXT:    [[EXT:%.*]] = zext i8 [[IN]] to i321385; MESA-NEXT:    store i32 [[EXT]], ptr addrspace(1) [[OUT_LOAD]], align 41386; MESA-NEXT:    ret void1387;1388  %in = load i8, ptr addrspace(4) %in.byref1389  %ext = zext i8 %in to i321390  store i32 %ext, ptr addrspace(1) %out, align 41391  ret void1392}1393 1394define amdgpu_kernel void @byref_constant_i16_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i16) %in.byref) {1395; HSA-LABEL: @byref_constant_i16_arg(1396; HSA-NEXT:    [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1397; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 01398; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1399; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 81400; HSA-NEXT:    [[IN:%.*]] = load i16, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 21401; HSA-NEXT:    [[EXT:%.*]] = zext i16 [[IN]] to i321402; HSA-NEXT:    store i32 [[EXT]], ptr addrspace(1) [[OUT_LOAD]], align 41403; HSA-NEXT:    ret void1404;1405; MESA-LABEL: @byref_constant_i16_arg(1406; MESA-NEXT:    [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1407; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 361408; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1409; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I16_ARG_KERNARG_SEGMENT]], i64 441410; MESA-NEXT:    [[IN:%.*]] = load i16, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 21411; MESA-NEXT:    [[EXT:%.*]] = zext i16 [[IN]] to i321412; MESA-NEXT:    store i32 [[EXT]], ptr addrspace(1) [[OUT_LOAD]], align 41413; MESA-NEXT:    ret void1414;1415  %in = load i16, ptr addrspace(4) %in.byref1416  %ext = zext i16 %in to i321417  store i32 %ext, ptr addrspace(1) %out, align 41418  ret void1419}1420 1421define amdgpu_kernel void @byref_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) %in.byref, i32 %after.offset) {1422; HSA-LABEL: @byref_constant_i32_arg(1423; HSA-NEXT:    [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1424; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 01425; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1426; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 81427; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 121428; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1429; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 41430; HSA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41431; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41432; HSA-NEXT:    ret void1433;1434; MESA-LABEL: @byref_constant_i32_arg(1435; MESA-NEXT:    [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1436; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 361437; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1438; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 441439; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 481440; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1441; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 41442; MESA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41443; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41444; MESA-NEXT:    ret void1445;1446  %in = load i32, ptr addrspace(4) %in.byref1447  store volatile i32 %in, ptr addrspace(1) %out, align 41448  store volatile i32 %after.offset, ptr addrspace(1) %out, align 41449  ret void1450}1451 1452define amdgpu_kernel void @byref_constant_v4i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(<4 x i32>) %in.byref, i32 %after.offset) {1453; HSA-LABEL: @byref_constant_v4i32_arg(1454; HSA-NEXT:    [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(296) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1455; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 01456; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1457; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 161458; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 321459; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1460; HSA-NEXT:    [[IN:%.*]] = load <4 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 161461; HSA-NEXT:    store volatile <4 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41462; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41463; HSA-NEXT:    ret void1464;1465; MESA-LABEL: @byref_constant_v4i32_arg(1466; MESA-NEXT:    [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(292) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1467; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 361468; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1469; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 521470; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_V4I32_ARG_KERNARG_SEGMENT]], i64 681471; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1472; MESA-NEXT:    [[IN:%.*]] = load <4 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 161473; MESA-NEXT:    store volatile <4 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41474; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41475; MESA-NEXT:    ret void1476;1477  %in = load <4 x i32>, ptr addrspace(4) %in.byref1478  store volatile <4 x i32> %in, ptr addrspace(1) %out, align 41479  store volatile i32 %after.offset, ptr addrspace(1) %out, align 41480  ret void1481}1482 1483define amdgpu_kernel void @byref_align_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 %after.offset) {1484; HSA-LABEL: @byref_align_constant_i32_arg(1485; HSA-NEXT:    [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 256 dereferenceable(520) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1486; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 01487; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1488; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 2561489; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 2601490; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1491; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 41492; HSA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41493; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41494; HSA-NEXT:    ret void1495;1496; MESA-LABEL: @byref_align_constant_i32_arg(1497; MESA-NEXT:    [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 256 dereferenceable(520) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1498; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 361499; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1500; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 2921501; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_ALIGN_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 2961502; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 8, !invariant.load [[META0]]1503; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 41504; MESA-NEXT:    store volatile i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41505; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41506; MESA-NEXT:    ret void1507;1508  %in = load i32, ptr addrspace(4) %in.byref1509  store volatile i32 %in, ptr addrspace(1) %out, align 41510  store volatile i32 %after.offset, ptr addrspace(1) %out, align 41511  ret void1512}1513 1514define amdgpu_kernel void @byref_natural_align_constant_v16i32_arg(ptr addrspace(1) nocapture %out, i8, ptr addrspace(4) byref(<16 x i32>) %in.byref, i32 %after.offset) {1515; HSA-LABEL: @byref_natural_align_constant_v16i32_arg(1516; HSA-NEXT:    [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(392) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1517; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 01518; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1519; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 641520; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 1281521; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1522; HSA-NEXT:    [[IN:%.*]] = load <16 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 641523; HSA-NEXT:    store volatile <16 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41524; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41525; HSA-NEXT:    ret void1526;1527; MESA-LABEL: @byref_natural_align_constant_v16i32_arg(1528; MESA-NEXT:    [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 64 dereferenceable(388) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1529; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 361530; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1531; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 1001532; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_NATURAL_ALIGN_CONSTANT_V16I32_ARG_KERNARG_SEGMENT]], i64 1641533; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1534; MESA-NEXT:    [[IN:%.*]] = load <16 x i32>, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 641535; MESA-NEXT:    store volatile <16 x i32> [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41536; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41537; MESA-NEXT:    ret void1538;1539  %in = load <16 x i32>, ptr addrspace(4) %in.byref1540  store volatile <16 x i32> %in, ptr addrspace(1) %out, align 41541  store volatile i32 %after.offset, ptr addrspace(1) %out, align 41542  ret void1543}1544 1545; Also accept byref kernel arguments with other global address spaces.1546define amdgpu_kernel void @byref_global_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(1) byref(i32) %in.byref) {1547; HSA-LABEL: @byref_global_i32_arg(1548; HSA-NEXT:    [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1549; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 01550; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1551; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 81552; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(1)1553; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(1) [[TMP1]], align 41554; HSA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41555; HSA-NEXT:    ret void1556;1557; MESA-LABEL: @byref_global_i32_arg(1558; MESA-NEXT:    [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1559; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 361560; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1561; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_GLOBAL_I32_ARG_KERNARG_SEGMENT]], i64 441562; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(1)1563; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(1) [[TMP1]], align 41564; MESA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41565; MESA-NEXT:    ret void1566;1567  %in = load i32, ptr addrspace(1) %in.byref1568  store i32 %in, ptr addrspace(1) %out, align 41569  ret void1570}1571 1572define amdgpu_kernel void @byref_flat_i32_arg(ptr addrspace(1) nocapture %out, ptr byref(i32) %in.byref) {1573; HSA-LABEL: @byref_flat_i32_arg(1574; HSA-NEXT:    [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1575; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 01576; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1577; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 81578; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr1579; HSA-NEXT:    [[IN:%.*]] = load i32, ptr [[TMP1]], align 41580; HSA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41581; HSA-NEXT:    ret void1582;1583; MESA-LABEL: @byref_flat_i32_arg(1584; MESA-NEXT:    [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1585; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 361586; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1587; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_FLAT_I32_ARG_KERNARG_SEGMENT]], i64 441588; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr1589; MESA-NEXT:    [[IN:%.*]] = load i32, ptr [[TMP1]], align 41590; MESA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41591; MESA-NEXT:    ret void1592;1593  %in = load i32, ptr %in.byref1594  store i32 %in, ptr addrspace(1) %out, align 41595  ret void1596}1597 1598define amdgpu_kernel void @byref_constant_32bit_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(6) byref(i32) %in.byref) {1599; HSA-LABEL: @byref_constant_32bit_i32_arg(1600; HSA-NEXT:    [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1601; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 01602; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1603; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 81604; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(6)1605; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(6) [[TMP1]], align 41606; HSA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41607; HSA-NEXT:    ret void1608;1609; MESA-LABEL: @byref_constant_32bit_i32_arg(1610; MESA-NEXT:    [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1611; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 361612; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1613; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_32BIT_I32_ARG_KERNARG_SEGMENT]], i64 441614; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(6)1615; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(6) [[TMP1]], align 41616; MESA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41617; MESA-NEXT:    ret void1618;1619  %in = load i32, ptr addrspace(6) %in.byref1620  store i32 %in, ptr addrspace(1) %out, align 41621  ret void1622}1623 1624define amdgpu_kernel void @byref_unknown_as_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(999) byref(i32) %in.byref) {1625; HSA-LABEL: @byref_unknown_as_i32_arg(1626; HSA-NEXT:    [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1627; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 01628; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1629; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 81630; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(999)1631; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(999) [[TMP1]], align 41632; HSA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41633; HSA-NEXT:    ret void1634;1635; MESA-LABEL: @byref_unknown_as_i32_arg(1636; MESA-NEXT:    [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1637; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 361638; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1639; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_UNKNOWN_AS_I32_ARG_KERNARG_SEGMENT]], i64 441640; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(999)1641; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(999) [[TMP1]], align 41642; MESA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41643; MESA-NEXT:    ret void1644;1645  %in = load i32, ptr addrspace(999) %in.byref1646  store i32 %in, ptr addrspace(1) %out, align 41647  ret void1648}1649 1650; Invalid, but should not crash.1651define amdgpu_kernel void @byref_local_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(3) byref(i32) %in.byref) {1652; HSA-LABEL: @byref_local_i32_arg(1653; HSA-NEXT:    [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1654; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 01655; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1656; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 81657; HSA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(3)1658; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(3) [[TMP1]], align 41659; HSA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41660; HSA-NEXT:    ret void1661;1662; MESA-LABEL: @byref_local_i32_arg(1663; MESA-NEXT:    [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(268) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1664; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 361665; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1666; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_LOCAL_I32_ARG_KERNARG_SEGMENT]], i64 441667; MESA-NEXT:    [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]] to ptr addrspace(3)1668; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(3) [[TMP1]], align 41669; MESA-NEXT:    store i32 [[IN]], ptr addrspace(1) [[OUT_LOAD]], align 41670; MESA-NEXT:    ret void1671;1672  %in = load i32, ptr addrspace(3) %in.byref1673  store i32 %in, ptr addrspace(1) %out, align 41674  ret void1675}1676 1677define amdgpu_kernel void @multi_byref_constant_i32_arg(ptr addrspace(1) nocapture %out, ptr addrspace(4) byref(i32) %in0.byref, ptr addrspace(4) byref(i32) %in1.byref, i32 %after.offset) {1678; HSA-LABEL: @multi_byref_constant_i32_arg(1679; HSA-NEXT:    [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(280) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1680; HSA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 01681; HSA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1682; HSA-NEXT:    [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 81683; HSA-NEXT:    [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 121684; HSA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 161685; HSA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]1686; HSA-NEXT:    [[IN0:%.*]] = load i32, ptr addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]], align 41687; HSA-NEXT:    [[IN1:%.*]] = load i32, ptr addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]], align 41688; HSA-NEXT:    store volatile i32 [[IN0]], ptr addrspace(1) [[OUT_LOAD]], align 41689; HSA-NEXT:    store volatile i32 [[IN1]], ptr addrspace(1) [[OUT_LOAD]], align 41690; HSA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41691; HSA-NEXT:    ret void1692;1693; MESA-LABEL: @multi_byref_constant_i32_arg(1694; MESA-NEXT:    [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(276) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1695; MESA-NEXT:    [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 361696; MESA-NEXT:    [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1697; MESA-NEXT:    [[IN0_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 441698; MESA-NEXT:    [[IN1_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 481699; MESA-NEXT:    [[AFTER_OFFSET_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[MULTI_BYREF_CONSTANT_I32_ARG_KERNARG_SEGMENT]], i64 521700; MESA-NEXT:    [[AFTER_OFFSET_LOAD:%.*]] = load i32, ptr addrspace(4) [[AFTER_OFFSET_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]1701; MESA-NEXT:    [[IN0:%.*]] = load i32, ptr addrspace(4) [[IN0_BYREF_BYVAL_KERNARG_OFFSET]], align 41702; MESA-NEXT:    [[IN1:%.*]] = load i32, ptr addrspace(4) [[IN1_BYREF_BYVAL_KERNARG_OFFSET]], align 41703; MESA-NEXT:    store volatile i32 [[IN0]], ptr addrspace(1) [[OUT_LOAD]], align 41704; MESA-NEXT:    store volatile i32 [[IN1]], ptr addrspace(1) [[OUT_LOAD]], align 41705; MESA-NEXT:    store volatile i32 [[AFTER_OFFSET_LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 41706; MESA-NEXT:    ret void1707;1708  %in0 = load i32, ptr addrspace(4) %in0.byref1709  %in1 = load i32, ptr addrspace(4) %in1.byref1710  store volatile i32 %in0, ptr addrspace(1) %out, align 41711  store volatile i32 %in1, ptr addrspace(1) %out, align 41712  store volatile i32 %after.offset, ptr addrspace(1) %out, align 41713  ret void1714}1715 1716define amdgpu_kernel void @byref_constant_i32_arg_offset0(ptr addrspace(4) byref(i32) %in.byref) {1717; HSA-LABEL: @byref_constant_i32_arg_offset0(1718; HSA-NEXT:    [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1719; HSA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT]], i64 01720; HSA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 41721; HSA-NEXT:    store i32 [[IN]], ptr addrspace(1) poison, align 41722; HSA-NEXT:    ret void1723;1724; MESA-LABEL: @byref_constant_i32_arg_offset0(1725; MESA-NEXT:    [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1726; MESA-NEXT:    [[IN_BYREF_BYVAL_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[BYREF_CONSTANT_I32_ARG_OFFSET0_KERNARG_SEGMENT]], i64 361727; MESA-NEXT:    [[IN:%.*]] = load i32, ptr addrspace(4) [[IN_BYREF_BYVAL_KERNARG_OFFSET]], align 41728; MESA-NEXT:    store i32 [[IN]], ptr addrspace(1) poison, align 41729; MESA-NEXT:    ret void1730;1731  %in = load i32, ptr addrspace(4) %in.byref1732  store i32 %in, ptr addrspace(1) poison, align 41733  ret void1734}1735 1736define amdgpu_kernel void @noundef_f32(float noundef %arg0) {1737; HSA-LABEL: @noundef_f32(1738; HSA-NEXT:    [[NOUNDEF_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1739; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F32_KERNARG_SEGMENT]], i64 01740; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]1741; HSA-NEXT:    call void (...) @llvm.fake.use(float [[ARG0_LOAD]])1742; HSA-NEXT:    ret void1743;1744; MESA-LABEL: @noundef_f32(1745; MESA-NEXT:    [[NOUNDEF_F32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1746; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F32_KERNARG_SEGMENT]], i64 361747; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load float, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]1748; MESA-NEXT:    call void (...) @llvm.fake.use(float [[ARG0_LOAD]])1749; MESA-NEXT:    ret void1750;1751  call void (...) @llvm.fake.use(float %arg0)1752  ret void1753}1754 1755define amdgpu_kernel void @noundef_f16(half noundef %arg0) {1756; HSA-LABEL: @noundef_f16(1757; HSA-NEXT:    [[NOUNDEF_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1758; HSA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F16_KERNARG_SEGMENT]], i64 01759; HSA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 16, !invariant.load [[META0]], !noundef [[META0]]1760; HSA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i161761; HSA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half1762; HSA-NEXT:    call void (...) @llvm.fake.use(half [[ARG0_LOAD]])1763; HSA-NEXT:    ret void1764;1765; MESA-LABEL: @noundef_f16(1766; MESA-NEXT:    [[NOUNDEF_F16_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(260) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1767; MESA-NEXT:    [[ARG0_KERNARG_OFFSET_ALIGN_DOWN:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_F16_KERNARG_SEGMENT]], i64 361768; MESA-NEXT:    [[TMP1:%.*]] = load i32, ptr addrspace(4) [[ARG0_KERNARG_OFFSET_ALIGN_DOWN]], align 4, !invariant.load [[META0]], !noundef [[META0]]1769; MESA-NEXT:    [[TMP2:%.*]] = trunc i32 [[TMP1]] to i161770; MESA-NEXT:    [[ARG0_LOAD:%.*]] = bitcast i16 [[TMP2]] to half1771; MESA-NEXT:    call void (...) @llvm.fake.use(half [[ARG0_LOAD]])1772; MESA-NEXT:    ret void1773;1774  call void (...) @llvm.fake.use(half %arg0)1775  ret void1776}1777 1778define amdgpu_kernel void @noundef_v2i32(<2 x i32> noundef %arg0) {1779; HSA-LABEL: @noundef_v2i32(1780; HSA-NEXT:    [[NOUNDEF_V2I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1781; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2I32_KERNARG_SEGMENT]], i64 01782; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]1783; HSA-NEXT:    call void (...) @llvm.fake.use(<2 x i32> [[ARG0_LOAD]])1784; HSA-NEXT:    ret void1785;1786; MESA-LABEL: @noundef_v2i32(1787; MESA-NEXT:    [[NOUNDEF_V2I32_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1788; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2I32_KERNARG_SEGMENT]], i64 361789; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x i32>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]1790; MESA-NEXT:    call void (...) @llvm.fake.use(<2 x i32> [[ARG0_LOAD]])1791; MESA-NEXT:    ret void1792;1793  call void (...) @llvm.fake.use(<2 x i32> %arg0)1794  ret void1795}1796 1797define amdgpu_kernel void @noundef_p0(ptr noundef %arg0) {1798; HSA-LABEL: @noundef_p0(1799; HSA-NEXT:    [[NOUNDEF_P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1800; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_P0_KERNARG_SEGMENT]], i64 01801; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]1802; HSA-NEXT:    call void (...) @llvm.fake.use(ptr [[ARG0_LOAD]])1803; HSA-NEXT:    ret void1804;1805; MESA-LABEL: @noundef_p0(1806; MESA-NEXT:    [[NOUNDEF_P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1807; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_P0_KERNARG_SEGMENT]], i64 361808; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load ptr, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]1809; MESA-NEXT:    call void (...) @llvm.fake.use(ptr [[ARG0_LOAD]])1810; MESA-NEXT:    ret void1811;1812  call void (...) @llvm.fake.use(ptr %arg0)1813  ret void1814}1815 1816define amdgpu_kernel void @noundef_v2p0(<2 x ptr> noundef %arg0) {1817; HSA-LABEL: @noundef_v2p0(1818; HSA-NEXT:    [[NOUNDEF_V2P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1819; HSA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2P0_KERNARG_SEGMENT]], i64 01820; HSA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 16, !invariant.load [[META0]], !noundef [[META0]]1821; HSA-NEXT:    call void (...) @llvm.fake.use(<2 x ptr> [[ARG0_LOAD]])1822; HSA-NEXT:    ret void1823;1824; MESA-LABEL: @noundef_v2p0(1825; MESA-NEXT:    [[NOUNDEF_V2P0_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(272) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()1826; MESA-NEXT:    [[ARG0_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[NOUNDEF_V2P0_KERNARG_SEGMENT]], i64 361827; MESA-NEXT:    [[ARG0_LOAD:%.*]] = load <2 x ptr>, ptr addrspace(4) [[ARG0_KERNARG_OFFSET]], align 4, !invariant.load [[META0]], !noundef [[META0]]1828; MESA-NEXT:    call void (...) @llvm.fake.use(<2 x ptr> [[ARG0_LOAD]])1829; MESA-NEXT:    ret void1830;1831  call void (...) @llvm.fake.use(<2 x ptr> %arg0)1832  ret void1833}1834 1835attributes #0 = { nounwind "target-cpu"="kaveri" }1836attributes #1 = { nounwind "target-cpu"="kaveri" "amdgpu-implicitarg-num-bytes"="40" }1837attributes #2 = { nounwind "target-cpu"="tahiti" }1838 1839 1840;.1841; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) }1842; HSA: attributes #[[ATTR1:[0-9]+]] = { nounwind "target-cpu"="kaveri" }1843; HSA: attributes #[[ATTR2:[0-9]+]] = { nounwind "amdgpu-implicitarg-num-bytes"="40" "target-cpu"="kaveri" }1844; HSA: attributes #[[ATTR3:[0-9]+]] = { nounwind "target-cpu"="tahiti" }1845; HSA: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }1846;.1847; MESA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite) }1848; MESA: attributes #[[ATTR1:[0-9]+]] = { nounwind "target-cpu"="kaveri" }1849; MESA: attributes #[[ATTR2:[0-9]+]] = { nounwind "amdgpu-implicitarg-num-bytes"="40" "target-cpu"="kaveri" }1850; MESA: attributes #[[ATTR3:[0-9]+]] = { nounwind "target-cpu"="tahiti" }1851; MESA: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }1852;.1853; HSA: [[META0]] = !{}1854; HSA: [[RNG1]] = !{i32 0, i32 8}1855; HSA: [[META2]] = !{i64 42}1856; HSA: [[META3]] = !{i64 128}1857; HSA: [[META4]] = !{i64 1024}1858;.1859; MESA: [[META0]] = !{}1860; MESA: [[RNG1]] = !{i32 0, i32 8}1861; MESA: [[META2]] = !{i64 42}1862; MESA: [[META3]] = !{i64 128}1863; MESA: [[META4]] = !{i64 1024}1864;.1865