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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O3 < %s | FileCheck -check-prefix=GCN %s2; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s3; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s4 5@a = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 46@b = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 47@c = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 48 9; FIXME: Should combine the DS instructions into ds_write2 and ds_read2. This10; does not happen because when SILoadStoreOptimizer is run, the reads and writes11; are not adjacent. They are only moved later by MachineScheduler.12 13define amdgpu_kernel void @no_clobber_ds_load_stores_x2(ptr addrspace(1) %arg, i32 %i) {14; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x2(15; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {16; CHECK-NEXT: bb:17; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, align 16, !alias.scope !1, !noalias !418; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 [[I]]19; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !alias.scope !1, !noalias !420; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 1), align 16, !alias.scope !4, !noalias !121; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2.lds, i32 0, i32 1), i32 0, i32 [[I]]22; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !alias.scope !4, !noalias !123; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_A]], [[VAL_B]]24; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 425; CHECK-NEXT: ret void26;27; GCN-LABEL: no_clobber_ds_load_stores_x2:28; GCN: ; %bb.0: ; %bb29; GCN-NEXT: s_load_dword s0, s[4:5], 0x2c30; GCN-NEXT: v_mov_b32_e32 v0, 131; GCN-NEXT: v_mov_b32_e32 v1, 032; GCN-NEXT: v_mov_b32_e32 v2, 233; GCN-NEXT: ds_write_b32 v1, v034; GCN-NEXT: s_waitcnt lgkmcnt(0)35; GCN-NEXT: s_lshl_b32 s0, s0, 236; GCN-NEXT: v_mov_b32_e32 v0, s037; GCN-NEXT: ds_write_b32 v1, v2 offset:25638; GCN-NEXT: ds_read_b32 v2, v039; GCN-NEXT: ds_read_b32 v0, v0 offset:25640; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2441; GCN-NEXT: s_waitcnt lgkmcnt(0)42; GCN-NEXT: v_add_u32_e32 v0, v2, v043; GCN-NEXT: global_store_dword v1, v0, s[0:1]44; GCN-NEXT: s_endpgm45bb:46 store i32 1, ptr addrspace(3) @a, align 447 %gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i48 %val.a = load i32, ptr addrspace(3) %gep.a, align 449 store i32 2, ptr addrspace(3) @b, align 450 %gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i51 %val.b = load i32, ptr addrspace(3) %gep.b, align 452 %val = add i32 %val.a, %val.b53 store i32 %val, ptr addrspace(1) %arg, align 454 ret void55}56 57define amdgpu_kernel void @no_clobber_ds_load_stores_x3(ptr addrspace(1) %arg, i32 %i) {58; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x3(59; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR1:[0-9]+]] {60; CHECK-NEXT: bb:61; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, align 16, !alias.scope !6, !noalias !962; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 [[I]]63; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !alias.scope !6, !noalias !964; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 1), align 16, !alias.scope !12, !noalias !1365; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 1), i32 0, i32 [[I]]66; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !alias.scope !12, !noalias !1367; CHECK-NEXT: store i32 3, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 2), align 16, !alias.scope !14, !noalias !1568; CHECK-NEXT: [[GEP_C:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X3_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x3.lds, i32 0, i32 2), i32 0, i32 [[I]]69; CHECK-NEXT: [[VAL_C:%.*]] = load i32, ptr addrspace(3) [[GEP_C]], align 4, !alias.scope !14, !noalias !1570; CHECK-NEXT: [[VAL_1:%.*]] = add i32 [[VAL_A]], [[VAL_B]]71; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_1]], [[VAL_C]]72; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 473; CHECK-NEXT: ret void74;75; GCN-LABEL: no_clobber_ds_load_stores_x3:76; GCN: ; %bb.0: ; %bb77; GCN-NEXT: s_load_dword s0, s[4:5], 0x2c78; GCN-NEXT: v_mov_b32_e32 v1, 079; GCN-NEXT: v_mov_b32_e32 v2, 280; GCN-NEXT: v_mov_b32_e32 v0, 181; GCN-NEXT: ds_write_b32 v1, v2 offset:25682; GCN-NEXT: s_waitcnt lgkmcnt(0)83; GCN-NEXT: s_lshl_b32 s0, s0, 284; GCN-NEXT: v_mov_b32_e32 v2, 385; GCN-NEXT: ds_write_b32 v1, v086; GCN-NEXT: v_mov_b32_e32 v0, s087; GCN-NEXT: ds_write_b32 v1, v2 offset:51288; GCN-NEXT: ds_read_b32 v2, v089; GCN-NEXT: ds_read_b32 v3, v0 offset:25690; GCN-NEXT: ds_read_b32 v0, v0 offset:51291; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2492; GCN-NEXT: s_waitcnt lgkmcnt(0)93; GCN-NEXT: v_add_u32_e32 v2, v2, v394; GCN-NEXT: v_add_u32_e32 v0, v2, v095; GCN-NEXT: global_store_dword v1, v0, s[0:1]96; GCN-NEXT: s_endpgm97bb:98 store i32 1, ptr addrspace(3) @a, align 499 %gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i100 %val.a = load i32, ptr addrspace(3) %gep.a, align 4101 store i32 2, ptr addrspace(3) @b, align 4102 %gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i103 %val.b = load i32, ptr addrspace(3) %gep.b, align 4104 store i32 3, ptr addrspace(3) @c, align 4105 %gep.c = getelementptr inbounds [64 x i32], ptr addrspace(3) @c, i32 0, i32 %i106 %val.c = load i32, ptr addrspace(3) %gep.c, align 4107 %val.1 = add i32 %val.a, %val.b108 %val = add i32 %val.1, %val.c109 store i32 %val, ptr addrspace(1) %arg, align 4110 ret void111}112 113; CHECK: !0 = !{i32 0, i32 1}114; CHECK: !1 = !{!2}115; CHECK: !2 = distinct !{!2, !3}116; CHECK: !3 = distinct !{!3}117; CHECK: !4 = !{!5}118; CHECK: !5 = distinct !{!5, !3}119; CHECK: !6 = !{!7}120; CHECK: !7 = distinct !{!7, !8}121; CHECK: !8 = distinct !{!8}122; CHECK: !9 = !{!10, !11}123; CHECK: !10 = distinct !{!10, !8}124; CHECK: !11 = distinct !{!11, !8}125; CHECK: !12 = !{!10}126; CHECK: !13 = !{!7, !11}127; CHECK: !14 = !{!11}128; CHECK: !15 = !{!7, !10}129