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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -O3 < %s | FileCheck -check-prefix=GCN %s3 4@a = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 45@b = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 46@c = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 47 8define amdgpu_kernel void @ds_load_stores_aainfo(ptr addrspace(1) %arg, i32 %i) {9; GCN-LABEL: ds_load_stores_aainfo:10; GCN:       ; %bb.0: ; %bb11; GCN-NEXT:    s_load_dword s0, s[4:5], 0x2c12; GCN-NEXT:    v_mov_b32_e32 v0, 113; GCN-NEXT:    v_mov_b32_e32 v1, 014; GCN-NEXT:    s_waitcnt lgkmcnt(0)15; GCN-NEXT:    s_lshl_b32 s0, s0, 216; GCN-NEXT:    v_mov_b32_e32 v4, s017; GCN-NEXT:    ds_read2_b32 v[2:3], v4 offset1:118; GCN-NEXT:    ds_write_b64 v1, v[0:1] offset:51219; GCN-NEXT:    ds_read2_b32 v[4:5], v4 offset0:64 offset1:6520; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2421; GCN-NEXT:    ; sched_group_barrier mask(0x00000100) size(1) SyncID(0)22; GCN-NEXT:    ; sched_group_barrier mask(0x00000200) size(1) SyncID(0)23; GCN-NEXT:    ; sched_group_barrier mask(0x00000100) size(1) SyncID(0)24; GCN-NEXT:    s_waitcnt lgkmcnt(0)25; GCN-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v426; GCN-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc27; GCN-NEXT:    global_store_dwordx2 v1, v[2:3], s[0:1]28; GCN-NEXT:    s_endpgm29bb:30  %gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i31  %gep.b = getelementptr inbounds [64 x i32], ptr addrspace(3) @b, i32 0, i32 %i32 33  %val.a = load i64, ptr addrspace(3) %gep.a, align 4, !tbaa !0, !alias.scope !6, !noalias !534  %val.b = load i64, ptr addrspace(3) %gep.b, align 4, !tbaa !0, !alias.scope !6, !noalias !535 36  store i64 1, ptr addrspace(3) @c, align 4, !tbaa !0, !noalias !237 38  %val = add i64 %val.a, %val.b39  store i64 %val, ptr addrspace(1) %arg, align 440 41  tail call void @llvm.amdgcn.sched.group.barrier(i32 256, i32 1, i32 0)42  tail call void @llvm.amdgcn.sched.group.barrier(i32 512, i32 1, i32 0)43  tail call void @llvm.amdgcn.sched.group.barrier(i32 256, i32 1, i32 0)44  ret void45}46 47  !0 = !{!"omnipotent char", !1, i64 0}48  !1 = !{!1}49  !2 = !{!3}50  !3 = distinct !{!3, !4}51  !4 = distinct !{!4}52  !5 = !{!3}53  !6 = !{!7}54  !7 = !{!7, !4}55