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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt -S -mtriple=amdgcn--amdhsa -passes=amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=OPT %s3; RUN: llc -mtriple=amdgcn--amdhsa < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=GCN %s4 5; Opt checks from utils/update_test_checks.py, llc checks from utils/update_llc_test_checks.py, both modified.6 7; Define four variables and four non-kernel functions which access exactly one variable each8@v0 = addrspace(3) global float poison9@v1 = addrspace(3) global i16 poison, align 1610@v2 = addrspace(3) global i64 poison11@v3 = addrspace(3) global i8 poison12@unused = addrspace(3) global i16 poison13 14; OPT: %llvm.amdgcn.kernel.kernel_no_table.lds.t = type { i64 }15; OPT: %llvm.amdgcn.kernel.k01.lds.t = type { i16, [2 x i8], float }16; OPT: %llvm.amdgcn.kernel.k23.lds.t = type { i64, i8 }17; OPT: %llvm.amdgcn.kernel.k123.lds.t = type { i16, i8, [5 x i8], i64 }18 19 20; Salient parts of the IR lookup table check:21; It has (top level) size 3 as there are 3 kernels that call functions which use lds22; The next level down has type [4 x i16] as there are 4 variables accessed by functions which use lds23; The kernel naming pattern and the structs being named after the functions helps verify placement of poison24; The remainder are constant expressions into the variable instances checked above25 26; OPT{LITERAL}: @llvm.amdgcn.lds.offset.table = internal addrspace(4) constant [3 x [4 x i32]] [[4 x i32] [i32 ptrtoint (ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.kernel.k01.lds.t, ptr addrspace(3) @llvm.amdgcn.kernel.k01.lds, i32 0, i32 2) to i32), i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.kernel.k01.lds to i32), i32 poison, i32 poison], [4 x i32] [i32 poison, i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.kernel.k123.lds to i32), i32 ptrtoint (ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.kernel.k123.lds.t, ptr addrspace(3) @llvm.amdgcn.kernel.k123.lds, i32 0, i32 3) to i32), i32 ptrtoint (ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.kernel.k123.lds.t, ptr addrspace(3) @llvm.amdgcn.kernel.k123.lds, i32 0, i32 1) to i32)], [4 x i32] [i32 poison, i32 poison, i32 ptrtoint (ptr addrspace(3) @llvm.amdgcn.kernel.k23.lds to i32), i32 ptrtoint (ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.kernel.k23.lds.t, ptr addrspace(3) @llvm.amdgcn.kernel.k23.lds, i32 0, i32 1) to i32)]]27 28 29define void @f0() {30; OPT-LABEL: define void @f0() {31; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()32; OPT-NEXT: [[V02:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 033; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[V02]], align 434; OPT-NEXT: [[V03:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3)35; OPT-NEXT: [[LD:%.*]] = load float, ptr addrspace(3) [[V03]], align 436; OPT-NEXT: [[MUL:%.*]] = fmul float [[LD]], 2.000000e+0037; OPT-NEXT: [[V0:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 038; OPT-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[V0]], align 439; OPT-NEXT: [[V01:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(3)40; OPT-NEXT: store float [[MUL]], ptr addrspace(3) [[V01]], align 441; OPT-NEXT: ret void42;43; GCN-LABEL: f0:44; GCN: ; %bb.0:45; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; GCN-NEXT: s_mov_b32 s4, s1547; GCN-NEXT: s_ashr_i32 s5, s15, 3148; GCN-NEXT: s_getpc_b64 s[6:7]49; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+450; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+1251; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 452; GCN-NEXT: s_add_u32 s4, s6, s453; GCN-NEXT: s_addc_u32 s5, s7, s554; GCN-NEXT: s_load_dword s4, s[4:5], 0x055; GCN-NEXT: s_waitcnt lgkmcnt(0)56; GCN-NEXT: v_mov_b32_e32 v0, s457; GCN-NEXT: s_mov_b32 m0, -158; GCN-NEXT: ds_read_b32 v1, v059; GCN-NEXT: s_waitcnt lgkmcnt(0)60; GCN-NEXT: v_add_f32_e32 v1, v1, v161; GCN-NEXT: ds_write_b32 v0, v162; GCN-NEXT: s_waitcnt lgkmcnt(0)63; GCN-NEXT: s_setpc_b64 s[30:31]64 %ld = load float, ptr addrspace(3) @v065 %mul = fmul float %ld, 2.66 store float %mul, ptr addrspace(3) @v067 ret void68}69 70define void @f1() {71; OPT-LABEL: define void @f1() {72; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()73; OPT-NEXT: [[V12:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 174; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[V12]], align 475; OPT-NEXT: [[V13:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3)76; OPT-NEXT: [[LD:%.*]] = load i16, ptr addrspace(3) [[V13]], align 277; OPT-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 378; OPT-NEXT: [[V1:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 179; OPT-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[V1]], align 480; OPT-NEXT: [[V11:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(3)81; OPT-NEXT: store i16 [[MUL]], ptr addrspace(3) [[V11]], align 282; OPT-NEXT: ret void83;84; GCN-LABEL: f1:85; GCN: ; %bb.0:86; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; GCN-NEXT: s_mov_b32 s4, s1588; GCN-NEXT: s_ashr_i32 s5, s15, 3189; GCN-NEXT: s_getpc_b64 s[6:7]90; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+891; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+1692; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 493; GCN-NEXT: s_add_u32 s4, s6, s494; GCN-NEXT: s_addc_u32 s5, s7, s595; GCN-NEXT: s_load_dword s4, s[4:5], 0x096; GCN-NEXT: s_waitcnt lgkmcnt(0)97; GCN-NEXT: v_mov_b32_e32 v0, s498; GCN-NEXT: s_mov_b32 m0, -199; GCN-NEXT: ds_read_u16 v1, v0100; GCN-NEXT: s_waitcnt lgkmcnt(0)101; GCN-NEXT: v_mul_lo_u32 v1, v1, 3102; GCN-NEXT: ds_write_b16 v0, v1103; GCN-NEXT: s_waitcnt lgkmcnt(0)104; GCN-NEXT: s_setpc_b64 s[30:31]105 %ld = load i16, ptr addrspace(3) @v1106 %mul = mul i16 %ld, 3107 store i16 %mul, ptr addrspace(3) @v1108 ret void109}110 111define void @f2() {112; OPT-LABEL: define void @f2() {113; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()114; OPT-NEXT: [[V22:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 2115; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[V22]], align 4116; OPT-NEXT: [[V23:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3)117; OPT-NEXT: [[LD:%.*]] = load i64, ptr addrspace(3) [[V23]], align 8118; OPT-NEXT: [[MUL:%.*]] = mul i64 [[LD]], 4119; OPT-NEXT: [[V2:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 2120; OPT-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[V2]], align 4121; OPT-NEXT: [[V21:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(3)122; OPT-NEXT: store i64 [[MUL]], ptr addrspace(3) [[V21]], align 8123; OPT-NEXT: ret void124;125; GCN-LABEL: f2:126; GCN: ; %bb.0:127; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)128; GCN-NEXT: s_mov_b32 s4, s15129; GCN-NEXT: s_ashr_i32 s5, s15, 31130; GCN-NEXT: s_getpc_b64 s[6:7]131; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+12132; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+20133; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4134; GCN-NEXT: s_add_u32 s4, s6, s4135; GCN-NEXT: s_addc_u32 s5, s7, s5136; GCN-NEXT: s_load_dword s4, s[4:5], 0x0137; GCN-NEXT: s_waitcnt lgkmcnt(0)138; GCN-NEXT: v_mov_b32_e32 v2, s4139; GCN-NEXT: s_mov_b32 m0, -1140; GCN-NEXT: ds_read_b64 v[0:1], v2141; GCN-NEXT: s_waitcnt lgkmcnt(0)142; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 2143; GCN-NEXT: ds_write_b64 v2, v[0:1]144; GCN-NEXT: s_waitcnt lgkmcnt(0)145; GCN-NEXT: s_setpc_b64 s[30:31]146 %ld = load i64, ptr addrspace(3) @v2147 %mul = mul i64 %ld, 4148 store i64 %mul, ptr addrspace(3) @v2149 ret void150}151 152define void @f3() {153; OPT-LABEL: define void @f3() {154; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()155; OPT-NEXT: [[V32:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 3156; OPT-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[V32]], align 4157; OPT-NEXT: [[V33:%.*]] = inttoptr i32 [[TMP2]] to ptr addrspace(3)158; OPT-NEXT: [[LD:%.*]] = load i8, ptr addrspace(3) [[V33]], align 1159; OPT-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 5160; OPT-NEXT: [[V3:%.*]] = getelementptr inbounds [3 x [4 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 3161; OPT-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[V3]], align 4162; OPT-NEXT: [[V31:%.*]] = inttoptr i32 [[TMP3]] to ptr addrspace(3)163; OPT-NEXT: store i8 [[MUL]], ptr addrspace(3) [[V31]], align 1164; OPT-NEXT: ret void165;166; GCN-LABEL: f3:167; GCN: ; %bb.0:168; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)169; GCN-NEXT: s_mov_b32 s4, s15170; GCN-NEXT: s_ashr_i32 s5, s15, 31171; GCN-NEXT: s_getpc_b64 s[6:7]172; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+16173; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+24174; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4175; GCN-NEXT: s_add_u32 s4, s6, s4176; GCN-NEXT: s_addc_u32 s5, s7, s5177; GCN-NEXT: s_load_dword s4, s[4:5], 0x0178; GCN-NEXT: s_waitcnt lgkmcnt(0)179; GCN-NEXT: v_mov_b32_e32 v0, s4180; GCN-NEXT: s_mov_b32 m0, -1181; GCN-NEXT: ds_read_u8 v1, v0182; GCN-NEXT: s_waitcnt lgkmcnt(0)183; GCN-NEXT: v_mul_lo_u32 v1, v1, 5184; GCN-NEXT: ds_write_b8 v0, v1185; GCN-NEXT: s_waitcnt lgkmcnt(0)186; GCN-NEXT: s_setpc_b64 s[30:31]187 %ld = load i8, ptr addrspace(3) @v3188 %mul = mul i8 %ld, 5189 store i8 %mul, ptr addrspace(3) @v3190 ret void191}192 193; Doesn't access any via a function, won't be in the lookup table194define amdgpu_kernel void @kernel_no_table() {195; OPT-LABEL: define amdgpu_kernel void @kernel_no_table(196; OPT-SAME: ) #[[ATTR0:[0-9]+]] {197; OPT-NEXT: [[LD:%.*]] = load i64, ptr addrspace(3) @llvm.amdgcn.kernel.kernel_no_table.lds, align 8198; OPT-NEXT: [[MUL:%.*]] = mul i64 [[LD]], 8199; OPT-NEXT: store i64 [[MUL]], ptr addrspace(3) @llvm.amdgcn.kernel.kernel_no_table.lds, align 8200; OPT-NEXT: ret void201;202; GCN-LABEL: kernel_no_table:203; GCN: ; %bb.0:204; GCN-NEXT: v_mov_b32_e32 v2, 0205; GCN-NEXT: s_mov_b32 m0, -1206; GCN-NEXT: ds_read_b64 v[0:1], v2207; GCN-NEXT: s_waitcnt lgkmcnt(0)208; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 3209; GCN-NEXT: ds_write_b64 v2, v[0:1]210; GCN-NEXT: s_endpgm211 %ld = load i64, ptr addrspace(3) @v2212 %mul = mul i64 %ld, 8213 store i64 %mul, ptr addrspace(3) @v2214 ret void215}216 217; Access two variables, will allocate those two218define amdgpu_kernel void @k01() {219; OPT-LABEL: define amdgpu_kernel void @k01(220; OPT-SAME: ) #[[ATTR0]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] {221; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.kernel.k01.lds) ], !alias.scope [[META3:![0-9]+]], !noalias [[META6:![0-9]+]]222; OPT-NEXT: call void @f0()223; OPT-NEXT: call void @f1()224; OPT-NEXT: ret void225;226; GCN-LABEL: k01:227; GCN: ; %bb.0:228; GCN-NEXT: s_mov_b32 s32, 0229; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13230; GCN-NEXT: s_add_i32 s12, s12, s17231; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8232; GCN-NEXT: s_add_u32 s0, s0, s17233; GCN-NEXT: s_addc_u32 s1, s1, 0234; GCN-NEXT: s_mov_b32 s20, s16235; GCN-NEXT: s_mov_b32 s13, s15236; GCN-NEXT: s_mov_b32 s12, s14237; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]238; GCN-NEXT: s_mov_b64 s[18:19], s[4:5]239; GCN-NEXT: s_getpc_b64 s[4:5]240; GCN-NEXT: s_add_u32 s4, s4, f0@gotpcrel32@lo+4241; GCN-NEXT: s_addc_u32 s5, s5, f0@gotpcrel32@hi+12242; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2243; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0244; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1245; GCN-NEXT: v_or_b32_e32 v0, v0, v1246; GCN-NEXT: v_or_b32_e32 v31, v0, v2247; GCN-NEXT: s_mov_b32 s15, 0248; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]249; GCN-NEXT: s_mov_b32 s14, s20250; GCN-NEXT: s_waitcnt lgkmcnt(0)251; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]252; GCN-NEXT: s_getpc_b64 s[4:5]253; GCN-NEXT: s_add_u32 s4, s4, f1@gotpcrel32@lo+4254; GCN-NEXT: s_addc_u32 s5, s5, f1@gotpcrel32@hi+12255; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0256; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]257; GCN-NEXT: s_mov_b64 s[6:7], s[16:17]258; GCN-NEXT: s_waitcnt lgkmcnt(0)259; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]260; GCN-NEXT: s_endpgm261 262 263 264 call void @f0()265 call void @f1()266 ret void267}268 269define amdgpu_kernel void @k23() {270; OPT-LABEL: define amdgpu_kernel void @k23(271; OPT-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META8:![0-9]+]] {272; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.kernel.k23.lds) ], !alias.scope [[META9:![0-9]+]], !noalias [[META12:![0-9]+]]273; OPT-NEXT: call void @f2()274; OPT-NEXT: call void @f3()275; OPT-NEXT: ret void276;277; GCN-LABEL: k23:278; GCN: ; %bb.0:279; GCN-NEXT: s_mov_b32 s32, 0280; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13281; GCN-NEXT: s_add_i32 s12, s12, s17282; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8283; GCN-NEXT: s_add_u32 s0, s0, s17284; GCN-NEXT: s_addc_u32 s1, s1, 0285; GCN-NEXT: s_mov_b32 s20, s16286; GCN-NEXT: s_mov_b32 s13, s15287; GCN-NEXT: s_mov_b32 s12, s14288; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]289; GCN-NEXT: s_mov_b64 s[18:19], s[4:5]290; GCN-NEXT: s_getpc_b64 s[4:5]291; GCN-NEXT: s_add_u32 s4, s4, f2@gotpcrel32@lo+4292; GCN-NEXT: s_addc_u32 s5, s5, f2@gotpcrel32@hi+12293; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2294; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0295; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1296; GCN-NEXT: v_or_b32_e32 v0, v0, v1297; GCN-NEXT: v_or_b32_e32 v31, v0, v2298; GCN-NEXT: s_mov_b32 s15, 2299; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]300; GCN-NEXT: s_mov_b32 s14, s20301; GCN-NEXT: s_waitcnt lgkmcnt(0)302; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]303; GCN-NEXT: s_getpc_b64 s[4:5]304; GCN-NEXT: s_add_u32 s4, s4, f3@gotpcrel32@lo+4305; GCN-NEXT: s_addc_u32 s5, s5, f3@gotpcrel32@hi+12306; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0307; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]308; GCN-NEXT: s_mov_b64 s[6:7], s[16:17]309; GCN-NEXT: s_waitcnt lgkmcnt(0)310; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]311; GCN-NEXT: s_endpgm312 313 314 call void @f2()315 call void @f3()316 ret void317}318 319; Access and allocate three variables320define amdgpu_kernel void @k123() {321; OPT-LABEL: define amdgpu_kernel void @k123(322; OPT-SAME: ) #[[ATTR1]] !llvm.amdgcn.lds.kernel.id [[META14:![0-9]+]] {323; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"(ptr addrspace(3) @llvm.amdgcn.kernel.k123.lds) ], !alias.scope [[META15:![0-9]+]], !noalias [[META18:![0-9]+]]324; OPT-NEXT: call void @f1()325; OPT-NEXT: [[LD:%.*]] = load i8, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K123_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.k123.lds, i32 0, i32 1), align 2, !alias.scope [[META21:![0-9]+]], !noalias [[META22:![0-9]+]]326; OPT-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 8327; OPT-NEXT: store i8 [[MUL]], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K123_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.k123.lds, i32 0, i32 1), align 2, !alias.scope [[META21]], !noalias [[META22]]328; OPT-NEXT: call void @f2()329; OPT-NEXT: ret void330;331; GCN-LABEL: k123:332; GCN: ; %bb.0:333; GCN-NEXT: s_mov_b32 s32, 0334; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13335; GCN-NEXT: s_add_i32 s12, s12, s17336; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8337; GCN-NEXT: s_add_u32 s0, s0, s17338; GCN-NEXT: s_addc_u32 s1, s1, 0339; GCN-NEXT: s_mov_b32 s20, s16340; GCN-NEXT: s_mov_b32 s13, s15341; GCN-NEXT: s_mov_b32 s12, s14342; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]343; GCN-NEXT: s_mov_b64 s[18:19], s[4:5]344; GCN-NEXT: s_getpc_b64 s[4:5]345; GCN-NEXT: s_add_u32 s4, s4, f1@gotpcrel32@lo+4346; GCN-NEXT: s_addc_u32 s5, s5, f1@gotpcrel32@hi+12347; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2348; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0349; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1350; GCN-NEXT: v_or_b32_e32 v0, v0, v1351; GCN-NEXT: v_or_b32_e32 v31, v0, v2352; GCN-NEXT: s_mov_b32 s15, 1353; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]354; GCN-NEXT: s_mov_b32 s14, s20355; GCN-NEXT: s_waitcnt lgkmcnt(0)356; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]357; GCN-NEXT: v_mov_b32_e32 v0, 0358; GCN-NEXT: s_mov_b32 m0, -1359; GCN-NEXT: ds_read_u8 v1, v0 offset:2360; GCN-NEXT: s_getpc_b64 s[4:5]361; GCN-NEXT: s_add_u32 s4, s4, f2@gotpcrel32@lo+4362; GCN-NEXT: s_addc_u32 s5, s5, f2@gotpcrel32@hi+12363; GCN-NEXT: s_load_dwordx2 s[22:23], s[4:5], 0x0364; GCN-NEXT: s_waitcnt lgkmcnt(0)365; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v1366; GCN-NEXT: ds_write_b8 v0, v1 offset:2367; GCN-NEXT: s_mov_b64 s[4:5], s[18:19]368; GCN-NEXT: s_mov_b64 s[6:7], s[16:17]369; GCN-NEXT: s_swappc_b64 s[30:31], s[22:23]370; GCN-NEXT: s_endpgm371 372 373 call void @f1()374 %ld = load i8, ptr addrspace(3) @v3375 %mul = mul i8 %ld, 8376 store i8 %mul, ptr addrspace(3) @v3377 call void @f2()378 ret void379}380 381 382 383; OPT: attributes #0 = { "amdgpu-lds-size"="8" }384; OPT: attributes #1 = { "amdgpu-lds-size"="16" }385 386!0 = !{i64 0, i64 1}387!1 = !{i32 0}388!2 = !{i32 2}389!3 = !{i32 1}390 391 392; Table size length number-kernels * number-variables * sizeof(uint16_t)393; GCN: .type llvm.amdgcn.lds.offset.table,@object394; GCN-NEXT: .section .data.rel.ro,"aw"395; GCN-NEXT: .p2align 4, 0x0396; GCN-NEXT: llvm.amdgcn.lds.offset.table:397; GCN-NEXT: .long 0+4398; GCN-NEXT: .long 0399; GCN-NEXT: .zero 4400; GCN-NEXT: .zero 4401; GCN-NEXT: .zero 4402; GCN-NEXT: .long 0403; GCN-NEXT: .long 0+8404; GCN-NEXT: .long 0+2405; GCN-NEXT: .zero 4406; GCN-NEXT: .zero 4407; GCN-NEXT: .long 0408; GCN-NEXT: .long 0+8409; GCN-NEXT: .size llvm.amdgcn.lds.offset.table, 48410 411!llvm.module.flags = !{!4}412!4 = !{i32 1, !"amdhsa_code_object_version", i32 500}413