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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs < %s | FileCheck -check-prefix=GFX9-SDAG %s3; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel < %s | FileCheck -check-prefix=GFX9-GISEL %s4; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12-SDAG %s5; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel < %s | FileCheck -check-prefix=GFX12-GISEL %s6; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s7; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel < %s | FileCheck -check-prefix=GFX1250-GISEL %s8 9define amdgpu_cs void @_amdgpu_cs_main() {10; GFX9-SDAG-LABEL: _amdgpu_cs_main:11; GFX9-SDAG: ; %bb.0: ; %.entry12; GFX9-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 1613; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff14; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp915; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s116; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s017; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 018; GFX9-SDAG-NEXT: s_endpgm19;20; GFX9-GISEL-LABEL: _amdgpu_cs_main:21; GFX9-GISEL: ; %bb.0: ; %.entry22; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp923; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff24; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 1625; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s026; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s127; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s228; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 029; GFX9-GISEL-NEXT: s_endpgm30;31; GFX12-SDAG-LABEL: _amdgpu_cs_main:32; GFX12-SDAG: ; %bb.0: ; %.entry33; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff34; GFX12-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 1635; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s036; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s137; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null38; GFX12-SDAG-NEXT: s_endpgm39;40; GFX12-GISEL-LABEL: _amdgpu_cs_main:41; GFX12-GISEL: ; %bb.0: ; %.entry42; GFX12-GISEL-NEXT: s_mov_b32 s0, ttmp943; GFX12-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff44; GFX12-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 1645; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s146; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s247; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null48; GFX12-GISEL-NEXT: s_endpgm49;50; GFX1250-SDAG-LABEL: _amdgpu_cs_main:51; GFX1250-SDAG: ; %bb.0: ; %.entry52; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c54; GFX1250-SDAG-NEXT: s_bfe_u32 s2, ttmp6, 0x4001055; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, 156; GFX1250-SDAG-NEXT: s_and_b32 s1, ttmp6, 1557; GFX1250-SDAG-NEXT: s_mul_i32 s0, ttmp9, s058; GFX1250-SDAG-NEXT: s_and_b32 s3, ttmp7, 0xffff59; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, 160; GFX1250-SDAG-NEXT: s_bfe_u32 s4, ttmp6, 0x4001461; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, s062; GFX1250-SDAG-NEXT: s_mul_i32 s0, s3, s263; GFX1250-SDAG-NEXT: s_bfe_u32 s2, ttmp6, 0x4000464; GFX1250-SDAG-NEXT: s_lshr_b32 s5, ttmp7, 1665; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, 166; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, s067; GFX1250-SDAG-NEXT: s_mul_i32 s0, s5, s468; GFX1250-SDAG-NEXT: s_bfe_u32 s4, ttmp6, 0x4000869; GFX1250-SDAG-NEXT: s_getreg_b32 s6, hwreg(HW_REG_IB_STS2, 6, 4)70; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, s071; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s6, 072; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s5, s473; GFX1250-SDAG-NEXT: s_cselect_b32 s1, ttmp9, s174; GFX1250-SDAG-NEXT: s_cselect_b32 s2, s3, s275; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)76; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s277; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s078; GFX1250-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null79; GFX1250-SDAG-NEXT: s_endpgm80;81; GFX1250-GISEL-LABEL: _amdgpu_cs_main:82; GFX1250-GISEL: ; %bb.0: ; %.entry83; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 184; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c85; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 1586; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 187; GFX1250-GISEL-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4)88; GFX1250-GISEL-NEXT: s_mul_i32 s0, ttmp9, s089; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)90; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, s091; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 092; GFX1250-GISEL-NEXT: s_cselect_b32 s0, ttmp9, s193; GFX1250-GISEL-NEXT: s_bfe_u32 s1, ttmp6, 0x4001094; GFX1250-GISEL-NEXT: s_and_b32 s3, ttmp7, 0xffff95; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, 196; GFX1250-GISEL-NEXT: s_bfe_u32 s4, ttmp6, 0x4000497; GFX1250-GISEL-NEXT: s_mul_i32 s1, s3, s198; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)99; GFX1250-GISEL-NEXT: s_add_co_i32 s4, s4, s1100; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0101; GFX1250-GISEL-NEXT: s_cselect_b32 s1, s3, s4102; GFX1250-GISEL-NEXT: s_bfe_u32 s3, ttmp6, 0x40014103; GFX1250-GISEL-NEXT: s_lshr_b32 s4, ttmp7, 16104; GFX1250-GISEL-NEXT: s_add_co_i32 s3, s3, 1105; GFX1250-GISEL-NEXT: s_bfe_u32 s5, ttmp6, 0x40008106; GFX1250-GISEL-NEXT: s_mul_i32 s3, s4, s3107; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)108; GFX1250-GISEL-NEXT: s_add_co_i32 s5, s5, s3109; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0110; GFX1250-GISEL-NEXT: s_cselect_b32 s2, s4, s5111; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1112; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2113; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null114; GFX1250-GISEL-NEXT: s_endpgm115.entry:116 %idx = call i32 @llvm.amdgcn.workgroup.id.x()117 %idy = call i32 @llvm.amdgcn.workgroup.id.y()118 %idz = call i32 @llvm.amdgcn.workgroup.id.z()119 %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0120 %ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1121 %ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2122 call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)123 ret void124}125 126define amdgpu_cs void @workgroup_id_no_clusters() "amdgpu-cluster-dims"="0,0,0" {127; GFX9-SDAG-LABEL: workgroup_id_no_clusters:128; GFX9-SDAG: ; %bb.0: ; %.entry129; GFX9-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16130; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff131; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9132; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1133; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s0134; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0135; GFX9-SDAG-NEXT: s_endpgm136;137; GFX9-GISEL-LABEL: workgroup_id_no_clusters:138; GFX9-GISEL: ; %bb.0: ; %.entry139; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9140; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff141; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16142; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0143; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1144; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2145; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0146; GFX9-GISEL-NEXT: s_endpgm147;148; GFX12-SDAG-LABEL: workgroup_id_no_clusters:149; GFX12-SDAG: ; %bb.0: ; %.entry150; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff151; GFX12-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16152; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0153; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s1154; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null155; GFX12-SDAG-NEXT: s_endpgm156;157; GFX12-GISEL-LABEL: workgroup_id_no_clusters:158; GFX12-GISEL: ; %bb.0: ; %.entry159; GFX12-GISEL-NEXT: s_mov_b32 s0, ttmp9160; GFX12-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff161; GFX12-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16162; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1163; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2164; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null165; GFX12-GISEL-NEXT: s_endpgm166;167; GFX1250-SDAG-LABEL: workgroup_id_no_clusters:168; GFX1250-SDAG: ; %bb.0: ; %.entry169; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GFX1250-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff171; GFX1250-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16172; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0173; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s1174; GFX1250-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null175; GFX1250-SDAG-NEXT: s_endpgm176;177; GFX1250-GISEL-LABEL: workgroup_id_no_clusters:178; GFX1250-GISEL: ; %bb.0: ; %.entry179; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1180; GFX1250-GISEL-NEXT: s_mov_b32 s0, ttmp9181; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff182; GFX1250-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16183; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1184; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2185; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null186; GFX1250-GISEL-NEXT: s_endpgm187.entry:188 %idx = call i32 @llvm.amdgcn.workgroup.id.x()189 %idy = call i32 @llvm.amdgcn.workgroup.id.y()190 %idz = call i32 @llvm.amdgcn.workgroup.id.z()191 %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0192 %ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1193 %ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2194 call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)195 ret void196}197 198define amdgpu_cs void @workgroup_id_optimized() "amdgpu-cluster-dims"="2,3,4" {199; GFX9-SDAG-LABEL: workgroup_id_optimized:200; GFX9-SDAG: ; %bb.0: ; %.entry201; GFX9-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16202; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff203; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9204; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1205; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s0206; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0207; GFX9-SDAG-NEXT: s_endpgm208;209; GFX9-GISEL-LABEL: workgroup_id_optimized:210; GFX9-GISEL: ; %bb.0: ; %.entry211; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9212; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff213; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16214; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0215; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1216; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2217; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0218; GFX9-GISEL-NEXT: s_endpgm219;220; GFX12-SDAG-LABEL: workgroup_id_optimized:221; GFX12-SDAG: ; %bb.0: ; %.entry222; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff223; GFX12-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16224; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0225; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s1226; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null227; GFX12-SDAG-NEXT: s_endpgm228;229; GFX12-GISEL-LABEL: workgroup_id_optimized:230; GFX12-GISEL: ; %bb.0: ; %.entry231; GFX12-GISEL-NEXT: s_mov_b32 s0, ttmp9232; GFX12-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff233; GFX12-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16234; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1235; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2236; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null237; GFX12-GISEL-NEXT: s_endpgm238;239; GFX1250-SDAG-LABEL: workgroup_id_optimized:240; GFX1250-SDAG: ; %bb.0: ; %.entry241; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1242; GFX1250-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 14243; GFX1250-SDAG-NEXT: s_and_b32 s2, ttmp7, 0xffff244; GFX1250-SDAG-NEXT: s_and_b32 s0, ttmp6, 15245; GFX1250-SDAG-NEXT: s_and_b32 s1, s1, 0x3fffc246; GFX1250-SDAG-NEXT: s_bfe_u32 s3, ttmp6, 0x40008247; GFX1250-SDAG-NEXT: s_mul_i32 s2, s2, 3248; GFX1250-SDAG-NEXT: s_bfe_u32 s4, ttmp6, 0x40004249; GFX1250-SDAG-NEXT: s_lshl1_add_u32 s0, ttmp9, s0250; GFX1250-SDAG-NEXT: s_add_co_i32 s3, s3, s1251; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, s2252; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)253; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s4254; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s3255; GFX1250-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null256; GFX1250-SDAG-NEXT: s_endpgm257;258; GFX1250-GISEL-LABEL: workgroup_id_optimized:259; GFX1250-GISEL: ; %bb.0: ; %.entry260; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1261; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff262; GFX1250-GISEL-NEXT: s_and_b32 s0, ttmp6, 15263; GFX1250-GISEL-NEXT: s_bfe_u32 s2, ttmp6, 0x40004264; GFX1250-GISEL-NEXT: s_mul_i32 s1, s1, 3265; GFX1250-GISEL-NEXT: s_lshr_b32 s3, ttmp7, 16266; GFX1250-GISEL-NEXT: s_bfe_u32 s4, ttmp6, 0x40008267; GFX1250-GISEL-NEXT: s_lshl1_add_u32 s0, ttmp9, s0268; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s2, s1269; GFX1250-GISEL-NEXT: s_lshl2_add_u32 s2, s3, s4270; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1271; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2272; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null273; GFX1250-GISEL-NEXT: s_endpgm274.entry:275 %idx = call i32 @llvm.amdgcn.workgroup.id.x()276 %idy = call i32 @llvm.amdgcn.workgroup.id.y()277 %idz = call i32 @llvm.amdgcn.workgroup.id.z()278 %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0279 %ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1280 %ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2281 call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)282 ret void283}284 285define amdgpu_cs void @caller() {286; GFX9-SDAG-LABEL: caller:287; GFX9-SDAG: ; %bb.0:288; GFX9-SDAG-NEXT: s_getpc_b64 s[8:9]289; GFX9-SDAG-NEXT: s_mov_b32 s8, s0290; GFX9-SDAG-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10291; GFX9-SDAG-NEXT: s_mov_b32 s5, callee@abs32@hi292; GFX9-SDAG-NEXT: s_mov_b32 s4, callee@abs32@lo293; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9294; GFX9-SDAG-NEXT: s_mov_b32 s32, 0295; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)296; GFX9-SDAG-NEXT: s_add_u32 s8, s8, s0297; GFX9-SDAG-NEXT: s_addc_u32 s9, s9, 0298; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[8:9]299; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[10:11]300; GFX9-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]301; GFX9-SDAG-NEXT: s_endpgm302;303; GFX9-GISEL-LABEL: caller:304; GFX9-GISEL: ; %bb.0:305; GFX9-GISEL-NEXT: s_getpc_b64 s[8:9]306; GFX9-GISEL-NEXT: s_mov_b32 s8, s0307; GFX9-GISEL-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10308; GFX9-GISEL-NEXT: s_mov_b32 s4, callee@abs32@lo309; GFX9-GISEL-NEXT: s_mov_b32 s5, callee@abs32@hi310; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9311; GFX9-GISEL-NEXT: s_mov_b32 s32, 0312; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)313; GFX9-GISEL-NEXT: s_add_u32 s8, s8, s0314; GFX9-GISEL-NEXT: s_addc_u32 s9, s9, 0315; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[8:9]316; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[10:11]317; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]318; GFX9-GISEL-NEXT: s_endpgm319;320; GFX12-SDAG-LABEL: caller:321; GFX12-SDAG: ; %bb.0:322; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9323; GFX12-SDAG-NEXT: s_mov_b32 s1, callee@abs32@hi324; GFX12-SDAG-NEXT: s_mov_b32 s0, callee@abs32@lo325; GFX12-SDAG-NEXT: s_mov_b32 s32, 0326; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)327; GFX12-SDAG-NEXT: s_swappc_b64 s[30:31], s[0:1]328; GFX12-SDAG-NEXT: s_endpgm329;330; GFX12-GISEL-LABEL: caller:331; GFX12-GISEL: ; %bb.0:332; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9333; GFX12-GISEL-NEXT: s_mov_b32 s0, callee@abs32@lo334; GFX12-GISEL-NEXT: s_mov_b32 s1, callee@abs32@hi335; GFX12-GISEL-NEXT: s_mov_b32 s32, 0336; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)337; GFX12-GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1]338; GFX12-GISEL-NEXT: s_endpgm339;340; GFX1250-SDAG-LABEL: caller:341; GFX1250-SDAG: ; %bb.0:342; GFX1250-SDAG-NEXT: s_mov_b32 s32, 0343; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1344; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c345; GFX1250-SDAG-NEXT: s_and_b32 s1, ttmp6, 15346; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, 1347; GFX1250-SDAG-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4)348; GFX1250-SDAG-NEXT: s_mul_i32 s0, ttmp9, s0349; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)350; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, s0351; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s2, 0352; GFX1250-SDAG-NEXT: s_cselect_b32 s2, ttmp9, s1353; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], callee@abs64354; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s2355; GFX1250-SDAG-NEXT: s_swap_pc_i64 s[30:31], s[0:1]356; GFX1250-SDAG-NEXT: s_endpgm357;358; GFX1250-GISEL-LABEL: caller:359; GFX1250-GISEL: ; %bb.0:360; GFX1250-GISEL-NEXT: s_mov_b32 s32, 0361; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1362; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c363; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 15364; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1365; GFX1250-GISEL-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4)366; GFX1250-GISEL-NEXT: s_mul_i32 s0, ttmp9, s0367; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)368; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, s0369; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0370; GFX1250-GISEL-NEXT: s_cselect_b32 s2, ttmp9, s1371; GFX1250-GISEL-NEXT: s_mov_b64 s[0:1], callee@abs64372; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s2373; GFX1250-GISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1]374; GFX1250-GISEL-NEXT: s_endpgm375 %idx = call i32 @llvm.amdgcn.workgroup.id.x()376 call amdgpu_gfx void @callee(i32 %idx)377 ret void378}379 380declare amdgpu_gfx void @callee(i32)381 382declare i32 @llvm.amdgcn.workgroup.id.x()383declare i32 @llvm.amdgcn.workgroup.id.y()384declare i32 @llvm.amdgcn.workgroup.id.z()385declare void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32>, ptr addrspace(8), i32, i32, i32 immarg)386