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1; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GCN,GFX942 %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s3 4define i64 @lshl_add_u64_v1v(i64 %v, i64 %a) {5; GCN-LABEL: lshl_add_u64_v1v:6; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 1, v[{{[0-9:]+}}]7 %shl = shl i64 %v, 18 %add = add i64 %shl, %a9 ret i64 %add10}11 12define i64 @lshl_add_u64_v4v(i64 %v, i64 %a) {13; GCN-LABEL: lshl_add_u64_v4v:14; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4, v[{{[0-9:]+}}]15 %shl = shl i64 %v, 416 %add = add i64 %shl, %a17 ret i64 %add18}19 20define i64 @lshl_add_u64_v5v(i64 %v, i64 %a) {21; GCN-LABEL: lshl_add_u64_v5v:22; GCN: v_lshlrev_b6423; GFX942-NEXT: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]24; GFX1250-NEXT: s_delay_alu25; GFX1250-NEXT: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]26 %shl = shl i64 %v, 527 %add = add i64 %shl, %a28 ret i64 %add29}30 31define i64 @lshl_add_u64_vvv(i64 %v, i64 %s, i64 %a) {32; GCN-LABEL: lshl_add_u64_vvv:33; GCN: v_lshlrev_b6434; GFX942-NEXT: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}]35; GFX1250-NEXT: s_delay_alu36; GFX1250-NEXT: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}]37 %shl = shl i64 %v, %s38 %add = add i64 %shl, %a39 ret i64 %add40}41 42define amdgpu_kernel void @lshl_add_u64_s2v(i64 %v) {43; GCN-LABEL: lshl_add_u64_s2v:44; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 2, v[{{[0-9:]+}}]45 %a = load i64, ptr poison46 %shl = shl i64 %v, 247 %add = add i64 %shl, %a48 store i64 %add, ptr poison49 ret void50}51 52define amdgpu_kernel void @lshl_add_u64_v2s(i64 %a) {53; GCN-LABEL: lshl_add_u64_v2s:54; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 2, s[{{[0-9:]+}}]55 %v = load i64, ptr poison56 %shl = shl i64 %v, 257 %add = add i64 %shl, %a58 store i64 %add, ptr poison59 ret void60}61 62define amdgpu_kernel void @lshl_add_u64_s2s(i64 %v, i64 %a) {63; GCN-LABEL: lshl_add_u64_s2s:64; GCN: s_lshl_b6465; GFX942: s_add_u3266; GFX942: s_addc_u3267; GFX1250: s_add_nc_u6468 %shl = shl i64 %v, 269 %add = add i64 %shl, %a70 store i64 %add, ptr poison71 ret void72}73 74define i64 @add_u64_vv(i64 %v, i64 %a) {75; GCN-LABEL: add_u64_vv:76; GFX942: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]77; GFX1250: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]78 %add = add i64 %v, %a79 ret i64 %add80}81 82define amdgpu_kernel void @add_u64_sv(i64 %v) {83; GCN-LABEL: add_u64_sv:84; GFX942: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1]85; GFX1250: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]86 %a = load i64, ptr poison87 %add = add i64 %v, %a88 store i64 %add, ptr poison89 ret void90}91 92define amdgpu_kernel void @add_u64_vs(i64 %a) {93; GCN-LABEL: add_u64_vs:94; GFX942: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1]95; GFX1250: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]96 %v = load i64, ptr poison97 %add = add i64 %v, %a98 store i64 %add, ptr poison99 ret void100}101 102define amdgpu_kernel void @add_u64_ss(i64 %v, i64 %a) {103; GCN-LABEL: add_u64_ss:104; GFX942: s_add_u32105; GFX942: s_addc_u32 s1, s1, s3106; GFX1250: s_add_nc_u64 s[0:1], s[0:1], s[2:3]107 %add = add i64 %v, %a108 store i64 %add, ptr poison109 ret void110}111 112define i32 @lshl_add_u64_gep(ptr %p, i64 %a) {113; GCN-LABEL: lshl_add_u64_gep:114; GCN: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1]115 %gep = getelementptr inbounds i32, ptr %p, i64 %a116 %v = load i32, ptr %gep117 ret i32 %v118}119