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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-- -mcpu=pitcairn < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @zext_shl64_to_32(ptr addrspace(1) nocapture %out, i32 %x) {5; GCN-LABEL: zext_shl64_to_32:6; GCN: ; %bb.0:7; GCN-NEXT: s_load_dword s6, s[4:5], 0xb8; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x99; GCN-NEXT: s_mov_b32 s3, 0xf00010; GCN-NEXT: s_mov_b32 s2, -111; GCN-NEXT: v_mov_b32_e32 v1, 012; GCN-NEXT: s_waitcnt lgkmcnt(0)13; GCN-NEXT: s_lshl_b32 s4, s6, 214; GCN-NEXT: v_mov_b32_e32 v0, s415; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 016; GCN-NEXT: s_endpgm17 %and = and i32 %x, 107374182318 %ext = zext i32 %and to i6419 %shl = shl i64 %ext, 220 store i64 %shl, ptr addrspace(1) %out, align 421 ret void22}23 24define amdgpu_kernel void @sext_shl64_to_32(ptr addrspace(1) nocapture %out, i32 %x) {25; GCN-LABEL: sext_shl64_to_32:26; GCN: ; %bb.0:27; GCN-NEXT: s_load_dword s6, s[4:5], 0xb28; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x929; GCN-NEXT: s_mov_b32 s3, 0xf00030; GCN-NEXT: s_mov_b32 s2, -131; GCN-NEXT: v_mov_b32_e32 v1, 032; GCN-NEXT: s_waitcnt lgkmcnt(0)33; GCN-NEXT: s_and_b32 s4, s6, 0x1fffffff34; GCN-NEXT: s_lshl_b32 s4, s4, 235; GCN-NEXT: v_mov_b32_e32 v0, s436; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 037; GCN-NEXT: s_endpgm38 %and = and i32 %x, 53687091139 %ext = sext i32 %and to i6440 %shl = shl i64 %ext, 241 store i64 %shl, ptr addrspace(1) %out, align 442 ret void43}44 45define amdgpu_kernel void @zext_shl64_overflow(ptr addrspace(1) nocapture %out, i32 %x) {46; GCN-LABEL: zext_shl64_overflow:47; GCN: ; %bb.0:48; GCN-NEXT: s_load_dword s6, s[4:5], 0xb49; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x950; GCN-NEXT: s_mov_b32 s5, 051; GCN-NEXT: s_mov_b32 s3, 0xf00052; GCN-NEXT: s_mov_b32 s2, -153; GCN-NEXT: s_waitcnt lgkmcnt(0)54; GCN-NEXT: s_and_b32 s4, s6, 0x7fffffff55; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 256; GCN-NEXT: v_mov_b32_e32 v0, s457; GCN-NEXT: v_mov_b32_e32 v1, s558; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 059; GCN-NEXT: s_endpgm60 %and = and i32 %x, 214748364761 %ext = zext i32 %and to i6462 %shl = shl i64 %ext, 263 store i64 %shl, ptr addrspace(1) %out, align 464 ret void65}66 67define amdgpu_kernel void @sext_shl64_overflow(ptr addrspace(1) nocapture %out, i32 %x) {68; GCN-LABEL: sext_shl64_overflow:69; GCN: ; %bb.0:70; GCN-NEXT: s_load_dword s6, s[4:5], 0xb71; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x972; GCN-NEXT: s_mov_b32 s5, 073; GCN-NEXT: s_mov_b32 s3, 0xf00074; GCN-NEXT: s_mov_b32 s2, -175; GCN-NEXT: s_waitcnt lgkmcnt(0)76; GCN-NEXT: s_and_b32 s4, s6, 0x7fffffff77; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 278; GCN-NEXT: v_mov_b32_e32 v0, s479; GCN-NEXT: v_mov_b32_e32 v1, s580; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 081; GCN-NEXT: s_endpgm82 %and = and i32 %x, 214748364783 %ext = sext i32 %and to i6484 %shl = shl i64 %ext, 285 store i64 %shl, ptr addrspace(1) %out, align 486 ret void87}88 89define amdgpu_kernel void @mulu24_shl64(ptr addrspace(1) nocapture %arg) {90; GCN-LABEL: mulu24_shl64:91; GCN: ; %bb.0: ; %bb92; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x993; GCN-NEXT: v_and_b32_e32 v0, 6, v094; GCN-NEXT: v_mul_u32_u24_e32 v0, 7, v095; GCN-NEXT: s_mov_b32 s3, 0xf00096; GCN-NEXT: s_mov_b32 s2, 097; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v098; GCN-NEXT: v_mov_b32_e32 v1, 099; GCN-NEXT: s_waitcnt lgkmcnt(0)100; GCN-NEXT: buffer_store_dword v1, v[0:1], s[0:3], 0 addr64101; GCN-NEXT: s_endpgm102bb:103 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()104 %tmp1 = and i32 %tmp, 6105 %mulconv = mul nuw nsw i32 %tmp1, 7106 %tmp2 = zext i32 %mulconv to i64107 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp2108 store i32 0, ptr addrspace(1) %tmp3, align 4109 ret void110}111 112define amdgpu_kernel void @muli24_shl64(ptr addrspace(1) nocapture %arg, ptr addrspace(1) nocapture readonly %arg1) {113; GCN-LABEL: muli24_shl64:114; GCN: ; %bb.0: ; %bb115; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9116; GCN-NEXT: s_mov_b32 s7, 0xf000117; GCN-NEXT: s_mov_b32 s6, 0118; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0119; GCN-NEXT: v_mov_b32_e32 v2, 0120; GCN-NEXT: s_waitcnt lgkmcnt(0)121; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]122; GCN-NEXT: buffer_load_dword v1, v[1:2], s[4:7], 0 addr64123; GCN-NEXT: v_lshlrev_b32_e32 v3, 3, v0124; GCN-NEXT: s_mov_b64 s[2:3], s[6:7]125; GCN-NEXT: v_mov_b32_e32 v4, v2126; GCN-NEXT: s_waitcnt vmcnt(0)127; GCN-NEXT: v_or_b32_e32 v0, 0x800000, v1128; GCN-NEXT: v_mul_i32_i24_e32 v0, -7, v0129; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0130; GCN-NEXT: buffer_store_dwordx2 v[1:2], v[3:4], s[0:3], 0 addr64131; GCN-NEXT: s_endpgm132bb:133 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()134 %tmp2 = sext i32 %tmp to i64135 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i64 %tmp2136 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 4137 %tmp5 = or i32 %tmp4, -8388608138 %tmp6 = mul nsw i32 %tmp5, -7139 %tmp7 = zext i32 %tmp6 to i64140 %tmp8 = shl nuw nsw i64 %tmp7, 3141 %tmp9 = getelementptr inbounds i64, ptr addrspace(1) %arg, i64 %tmp2142 store i64 %tmp8, ptr addrspace(1) %tmp9, align 8143 ret void144}145 146declare i32 @llvm.amdgcn.workitem.id.x()147