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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=machine-cse -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=machine-cse -o - %s | FileCheck %s4 5--- |6 define void @commute_instruction_subreg_target_flag() { ret void }7 define void @commute_target_flag_frame_index() { ret void }8 define void @commute_target_flag_global() { ret void }9 define void @commute_target_flag_global_offset() { ret void }10 define void @commute_target_flag_global_offset_mismatch() { ret void }11 12 declare void @func()13 @gv = external addrspace(1) global i3214 15...16 17# Make sure the subreg index is cleared when commuting a register and immediate.18 19---20name: commute_instruction_subreg_target_flag21tracksRegLiveness: true22body: |23 bb.0:24 liveins: $vgpr0_vgpr125 26 ; CHECK-LABEL: name: commute_instruction_subreg_target_flag27 ; CHECK: liveins: $vgpr0_vgpr128 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr130 ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]].sub1, 64, 0, implicit $exec31 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_]]32 %0:vreg_64 = COPY $vgpr0_vgpr133 %1:vgpr_32 = V_ADD_U32_e64 %0.sub1, 64, 0, implicit $exec34 %2:vgpr_32 = V_ADD_U32_e64 64, %0.sub1, 0, implicit $exec35 S_ENDPGM 0, implicit %1, implicit %236 37...38 39# FIXME: Why doesn't this CSE?40---41name: commute_target_flag_frame_index42tracksRegLiveness: true43stack:44 - { id: 0, type: default, offset: 0, size: 4, alignment: 4 }45body: |46 bb.0:47 liveins: $vgpr0_vgpr148 49 ; CHECK-LABEL: name: commute_target_flag_frame_index50 ; CHECK: liveins: $vgpr0_vgpr151 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr153 ; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, [[COPY]].sub0, 0, implicit $exec54 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_]]55 %0:vreg_64 = COPY $vgpr0_vgpr156 %1:vgpr_32 = V_ADD_U32_e64 %0.sub0, %stack.0, 0, implicit $exec57 %2:vgpr_32 = V_ADD_U32_e64 %stack.0, %0.sub0, 0, implicit $exec58 S_ENDPGM 0, implicit %1, implicit %259 60...61 62# FIXME: Handle commuting global variables63---64name: commute_target_flag_global65tracksRegLiveness: true66body: |67 bb.0:68 liveins: $sgpr0_sgpr169 70 ; CHECK-LABEL: name: commute_target_flag_global71 ; CHECK: liveins: $sgpr0_sgpr172 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr174 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc75 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_]]76 %0:sreg_64 = COPY $sgpr0_sgpr177 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @func, implicit-def dead $scc78 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @func, %0.sub0, implicit-def dead $scc79 S_ENDPGM 0, implicit %1, implicit %280 81...82 83---84name: commute_target_flag_global_offset85tracksRegLiveness: true86body: |87 bb.0:88 liveins: $sgpr0_sgpr189 90 ; CHECK-LABEL: name: commute_target_flag_global_offset91 ; CHECK: liveins: $sgpr0_sgpr192 ; CHECK-NEXT: {{ $}}93 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr194 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc95 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_]]96 %0:sreg_64 = COPY $sgpr0_sgpr197 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc98 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 4, %0.sub0, implicit-def dead $scc99 S_ENDPGM 0, implicit %1, implicit %2100 101...102 103---104name: commute_target_flag_global_offset_mismatch105tracksRegLiveness: true106body: |107 bb.0:108 liveins: $sgpr0_sgpr1109 110 ; CHECK-LABEL: name: commute_target_flag_global_offset_mismatch111 ; CHECK: liveins: $sgpr0_sgpr1112 ; CHECK-NEXT: {{ $}}113 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1114 ; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc115 ; CHECK-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, [[COPY]].sub0, implicit-def dead $scc116 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADD_U32_1]]117 %0:sreg_64 = COPY $sgpr0_sgpr1118 %1:sreg_32 = S_ADD_U32 %0.sub0, target-flags(amdgpu-rel32-lo) @gv + 4, implicit-def dead $scc119 %2:sreg_32 = S_ADD_U32 target-flags(amdgpu-rel32-lo) @gv + 8, %0.sub0, implicit-def dead $scc120 S_ENDPGM 0, implicit %1, implicit %2121 122...123