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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=machine-sink -o - %s | FileCheck -check-prefixes=GFX10 %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=machine-sink --sink-insts-to-avoid-spills=1 -o - %s | FileCheck -check-prefixes=GFX10 %s4 5---6name: multi_else_break7tracksRegLiveness: true8body: |9 ; GFX10-LABEL: name: multi_else_break10 ; GFX10: bb.0:11 ; GFX10-NEXT: successors: %bb.1(0x80000000)12 ; GFX10-NEXT: liveins: $vgpr4, $vgpr513 ; GFX10-NEXT: {{ $}}14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr515 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr416 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 017 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]], implicit $exec18 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF19 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF20 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF21 ; GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 122 ; GFX10-NEXT: {{ $}}23 ; GFX10-NEXT: bb.1:24 ; GFX10-NEXT: successors: %bb.2(0x80000000)25 ; GFX10-NEXT: {{ $}}26 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %9, %bb.627 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, %11, %bb.628 ; GFX10-NEXT: {{ $}}29 ; GFX10-NEXT: bb.2:30 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)31 ; GFX10-NEXT: {{ $}}32 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[DEF1]], %bb.1, %13, %bb.533 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32 = PHI [[DEF]], %bb.1, %15, %bb.534 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.1, %17, %bb.535 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, %19, %bb.536 ; GFX10-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[PHI5]], [[COPY1]], implicit $exec37 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]38 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[PHI3]], $exec_lo, implicit-def $scc39 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[PHI2]], $exec_lo, implicit-def $scc40 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_LT_I32_e64_]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec41 ; GFX10-NEXT: S_BRANCH %bb.442 ; GFX10-NEXT: {{ $}}43 ; GFX10-NEXT: bb.3:44 ; GFX10-NEXT: SI_END_CF %9, implicit-def dead $exec, implicit-def dead $scc, implicit $exec45 ; GFX10-NEXT: S_ENDPGM 046 ; GFX10-NEXT: {{ $}}47 ; GFX10-NEXT: bb.4:48 ; GFX10-NEXT: successors: %bb.5(0x80000000)49 ; GFX10-NEXT: {{ $}}50 ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[PHI5]], [[S_MOV_B32_1]], 0, implicit $exec51 ; GFX10-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NE_U32_e64 [[COPY]], [[V_ADD_U32_e64_]], implicit $exec52 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[S_OR_B32_]], $exec_lo, implicit-def $scc53 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[S_ANDN2_B32_]]54 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32 = S_ANDN2_B32 [[S_OR_B32_1]], $exec_lo, implicit-def $scc55 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_CMP_NE_U32_e64_]], $exec_lo, implicit-def $scc56 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_ANDN2_B32_1]], [[S_AND_B32_]], implicit-def $scc57 ; GFX10-NEXT: {{ $}}58 ; GFX10-NEXT: bb.5:59 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.2(0x7c000000)60 ; GFX10-NEXT: {{ $}}61 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32 = PHI [[S_OR_B32_1]], %bb.2, [[S_OR_B32_2]], %bb.462 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:sreg_32 = PHI [[S_OR_B32_]], %bb.2, [[COPY4]], %bb.463 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.2, [[V_ADD_U32_e64_]], %bb.464 ; GFX10-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec65 ; GFX10-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_32 = SI_IF_BREAK [[PHI6]], [[PHI4]], implicit-def dead $scc66 ; GFX10-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec67 ; GFX10-NEXT: S_BRANCH %bb.668 ; GFX10-NEXT: {{ $}}69 ; GFX10-NEXT: bb.6:70 ; GFX10-NEXT: successors: %bb.3(0x04000000), %bb.1(0x7c000000)71 ; GFX10-NEXT: {{ $}}72 ; GFX10-NEXT: [[PHI9:%[0-9]+]]:vgpr_32 = PHI [[PHI8]], %bb.573 ; GFX10-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec74 ; GFX10-NEXT: [[SI_IF_BREAK1:%[0-9]+]]:sreg_32 = SI_IF_BREAK [[PHI7]], [[PHI]], implicit-def dead $scc75 ; GFX10-NEXT: SI_LOOP [[SI_IF_BREAK1]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec76 ; GFX10-NEXT: S_BRANCH %bb.377 bb.0:78 successors: %bb.1(0x80000000)79 liveins: $vgpr4, $vgpr580 81 %21:vgpr_32 = COPY $vgpr582 %20:vgpr_32 = COPY $vgpr483 %23:sreg_32 = S_MOV_B32 084 %33:vgpr_32 = COPY %23, implicit $exec85 %38:sreg_32 = IMPLICIT_DEF86 %44:sreg_32 = IMPLICIT_DEF87 %26:sreg_32 = IMPLICIT_DEF88 %29:sreg_32 = S_MOV_B32 189 90 bb.1:91 successors: %bb.2(0x80000000)92 93 %0:sreg_32 = PHI %23, %bb.0, %12, %bb.694 %1:vgpr_32 = PHI %33, %bb.0, %13, %bb.695 96 bb.2:97 successors: %bb.4(0x40000000), %bb.5(0x40000000)98 99 %48:sreg_32 = PHI %44, %bb.1, %10, %bb.5100 %42:sreg_32 = PHI %38, %bb.1, %8, %bb.5101 %2:sreg_32 = PHI %23, %bb.1, %11, %bb.5102 %3:vgpr_32 = PHI %1, %bb.1, %9, %bb.5103 %27:sreg_32 = V_CMP_LT_I32_e64 %3, %20, implicit $exec104 %36:vgpr_32 = COPY %26105 %39:sreg_32 = S_OR_B32 %42, $exec_lo, implicit-def $scc106 %45:sreg_32 = S_OR_B32 %48, $exec_lo, implicit-def $scc107 %4:sreg_32 = SI_IF killed %27, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec108 S_BRANCH %bb.4109 110 bb.3:111 SI_END_CF %12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec112 S_ENDPGM 0113 114 bb.4:115 successors: %bb.5(0x80000000)116 117 %6:vgpr_32 = V_ADD_U32_e64 %3, %29, 0, implicit $exec118 %30:sreg_32 = V_CMP_NE_U32_e64 %21, %6, implicit $exec119 %43:sreg_32 = S_ANDN2_B32 %39, $exec_lo, implicit-def $scc120 %40:sreg_32 = COPY %43121 %49:sreg_32 = S_ANDN2_B32 %45, $exec_lo, implicit-def $scc122 %50:sreg_32 = S_AND_B32 %30, $exec_lo, implicit-def $scc123 %46:sreg_32 = S_OR_B32 %49, %50, implicit-def $scc124 125 bb.5:126 successors: %bb.6(0x04000000), %bb.2(0x7c000000)127 128 %10:sreg_32 = PHI %45, %bb.2, %46, %bb.4129 %8:sreg_32 = PHI %39, %bb.2, %40, %bb.4130 %9:vgpr_32 = PHI %36, %bb.2, %6, %bb.4131 SI_END_CF %4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec132 %11:sreg_32 = SI_IF_BREAK %10, %2, implicit-def dead $scc133 %12:sreg_32 = SI_IF_BREAK %8, %0, implicit-def dead $scc134 SI_LOOP %11, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec135 S_BRANCH %bb.6136 137 bb.6:138 successors: %bb.3(0x04000000), %bb.1(0x7c000000)139 140 %13:vgpr_32 = PHI %9, %bb.5141 SI_END_CF %11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec142 SI_LOOP %12, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec143 S_BRANCH %bb.3144...145