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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -mtriple=amdgcn -run-pass=early-machinelicm -simplify-mir -o - %s | FileCheck %s3# RUN: llc -mtriple=amdgcn -passes=early-machinelicm -simplify-mir -o - %s | FileCheck %s4 5# Test to check machine LICM does not hoist convergent instructions,6# DS_PERMUTE_B32 in this example.7 8---9name: licm_reg_sequence10body: |11 ; CHECK-LABEL: name: licm_reg_sequence12 ; CHECK: bb.0:13 ; CHECK-NEXT: liveins: $vgpr0, $vgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr016 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr117 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub118 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: bb.1:20 ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE]]21 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc22 ; CHECK-NEXT: S_BRANCH %bb.223 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: bb.2:25 ; CHECK-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]26 ; CHECK-NEXT: S_ENDPGM 027 bb.0:28 liveins: $vgpr0, $vgpr129 successors: %bb.130 31 %0:vgpr_32 = COPY $vgpr032 %1:vgpr_32 = COPY $vgpr133 34 bb.1:35 successors: %bb.1, %bb.236 37 %3:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub138 S_NOP 0, implicit %339 S_CBRANCH_SCC1 %bb.1, implicit undef $scc40 S_BRANCH %bb.241 42 bb.2:43 $vgpr0 = COPY %344 S_ENDPGM 045 46...47 48# Don't bother handling reg_sequence with physreg uses (is there any49# reason for these to be legal)?50---51name: licm_reg_sequence_physreg_use52body: |53 ; CHECK-LABEL: name: licm_reg_sequence_physreg_use54 ; CHECK: bb.0:55 ; CHECK-NEXT: liveins: $vgpr0, $vgpr156 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr058 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr159 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: bb.1:61 ; CHECK-NEXT: liveins: $vgpr062 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, $vgpr1, %subreg.sub164 ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE]]65 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc66 ; CHECK-NEXT: S_BRANCH %bb.267 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: bb.2:69 ; CHECK-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]70 ; CHECK-NEXT: S_ENDPGM 071 bb.0:72 liveins: $vgpr0, $vgpr173 successors: %bb.174 75 %0:vgpr_32 = COPY $vgpr076 %1:vgpr_32 = COPY $vgpr177 78 bb.1:79 successors: %bb.1, %bb.280 liveins: $vgpr081 82 %3:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, $vgpr1, %subreg.sub183 S_NOP 0, implicit %384 S_CBRANCH_SCC1 %bb.1, implicit undef $scc85 S_BRANCH %bb.286 87 bb.2:88 $vgpr0 = COPY %389 S_ENDPGM 090 91...92 93---94name: licm_insert_subreg95body: |96 ; CHECK-LABEL: name: licm_insert_subreg97 ; CHECK: bb.0:98 ; CHECK-NEXT: liveins: $vgpr0, $vgpr199 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1102 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF103 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub0104 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[INSERT_SUBREG]], [[COPY1]], %subreg.sub1105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: bb.1:107 ; CHECK-NEXT: S_NOP 0, implicit [[INSERT_SUBREG1]]108 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc109 ; CHECK-NEXT: S_BRANCH %bb.2110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: bb.2:112 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[INSERT_SUBREG1]]113 ; CHECK-NEXT: S_ENDPGM 0114 bb.0:115 liveins: $vgpr0, $vgpr1116 successors: %bb.1117 118 %0:vgpr_32 = COPY $vgpr0119 %1:vgpr_32 = COPY $vgpr1120 121 bb.1:122 successors: %bb.1, %bb.2123 124 %3:vreg_64 = IMPLICIT_DEF125 %4:vreg_64 = INSERT_SUBREG %3, %0, %subreg.sub0126 %5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1127 S_NOP 0, implicit %5128 S_CBRANCH_SCC1 %bb.1, implicit undef $scc129 S_BRANCH %bb.2130 131 bb.2:132 $vgpr0_vgpr1 = COPY %5133 S_ENDPGM 0134 135...136