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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=early-machinelicm %s -o - | FileCheck %s4 5# Issue #100115: test that MachineLICM does not assert on the undef use operand6# of the REG_SEQUENCE instruction.7---8name: test_undef_use9tracksRegLiveness: true10body: |11 ; CHECK-LABEL: name: test_undef_use12 ; CHECK: bb.0:13 ; CHECK-NEXT: successors: %bb.1(0x80000000)14 ; CHECK-NEXT: liveins: $vgpr0, $vgpr115 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF17 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF18 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: bb.1:20 ; CHECK-NEXT: successors: %bb.3(0x80000000)21 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, undef [[DEF]], %subreg.sub123 ; CHECK-NEXT: S_BRANCH %bb.324 ; CHECK-NEXT: {{ $}}25 ; CHECK-NEXT: bb.2:26 ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.1(0x7c000000)27 ; CHECK-NEXT: {{ $}}28 ; CHECK-NEXT: $vcc_lo = COPY undef [[DEF1]]29 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.5, implicit $vcc_lo30 ; CHECK-NEXT: S_BRANCH %bb.131 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: bb.3:33 ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)34 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit undef $scc36 ; CHECK-NEXT: S_BRANCH %bb.437 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: bb.4:39 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)40 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: SI_LOOP undef [[DEF1]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec42 ; CHECK-NEXT: S_BRANCH %bb.243 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: bb.5:45 ; CHECK-NEXT: S_ENDPGM 046 bb.0:47 successors: %bb.1(0x80000000)48 liveins: $vgpr0, $vgpr149 50 %0:vgpr_32 = IMPLICIT_DEF51 %1:sreg_32 = IMPLICIT_DEF52 53 bb.1:54 successors: %bb.3(0x80000000)55 56 %2:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, undef %0, %subreg.sub157 S_BRANCH %bb.358 59 bb.2:60 successors: %bb.5(0x04000000), %bb.1(0x7c000000)61 62 $vcc_lo = COPY undef %163 S_CBRANCH_VCCNZ %bb.5, implicit $vcc64 S_BRANCH %bb.165 66 bb.3:67 successors: %bb.4(0x04000000), %bb.3(0x7c000000)68 69 S_CBRANCH_SCC1 %bb.3, implicit undef $scc70 S_BRANCH %bb.471 72 bb.4:73 successors: %bb.2(0x40000000), %bb.1(0x40000000)74 75 SI_LOOP undef %1, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec76 S_BRANCH %bb.277 78 bb.5:79 S_ENDPGM 080...81