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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-TRUE16 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-FAKE16 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,SDAG-GFX9 %s5; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,SDAG-VI %s6; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=SDAG-CI %s7 8; FIXME-TRUE16. fix gisel9; XUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16 %s10; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16 %s11; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GISEL-GFX9 %s12; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=VI,GISEL-VI %s13; RUN: llc -global-isel -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GISEL-CI %s14 15define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %src1, half %src2) #0 {16; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:17; GFX11: ; %bb.0:18; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]20; GFX11-NEXT: s_setpc_b64 s[30:31]21;22; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:23; GFX9: ; %bb.0:24; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)25; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]26; GFX9-NEXT: s_setpc_b64 s[30:31]27;28; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:29; VI: ; %bb.0:30; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; VI-NEXT: v_cvt_f32_f16_e32 v0, v032; VI-NEXT: v_cvt_f32_f16_e32 v1, v133; VI-NEXT: v_cvt_f32_f16_e32 v2, v234; VI-NEXT: v_mac_f32_e32 v2, v0, v135; VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD36; VI-NEXT: s_setpc_b64 s[30:31]37;38; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:39; SDAG-CI: ; %bb.0:40; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v142; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v243; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v044; SDAG-CI-NEXT: s_setpc_b64 s[30:31]45;46; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo:47; GISEL-CI: ; %bb.0:48; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)49; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v050; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v151; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v252; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v153; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v254; GISEL-CI-NEXT: s_setpc_b64 s[30:31]55 %src0.ext = fpext half %src0 to float56 %src1.ext = fpext half %src1 to float57 %src2.ext = fpext half %src2 to float58 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)59 %cvt.result = fptrunc float %result to half60 %vec.result = insertelement <2 x half> poison, half %cvt.result, i32 161 ret <2 x half> %vec.result62}63 64define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %src1, half %src2) #0 {65; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:66; SDAG-GFX11-TRUE16: ; %bb.0:67; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; SDAG-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]69; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)70; SDAG-GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, 1.0, v0.l71; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]72;73; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:74; SDAG-GFX11-FAKE16: ; %bb.0:75; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; SDAG-GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0x3c0077; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)78; SDAG-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]79; SDAG-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v380; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]81;82; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:83; GFX9: ; %bb.0:84; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)85; GFX9-NEXT: v_mov_b32_e32 v3, 0x3c0086; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]87; GFX9-NEXT: v_mov_b32_e32 v0, v388; GFX9-NEXT: s_setpc_b64 s[30:31]89;90; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:91; VI: ; %bb.0:92; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)93; VI-NEXT: v_cvt_f32_f16_e32 v0, v094; VI-NEXT: v_cvt_f32_f16_e32 v1, v195; VI-NEXT: v_cvt_f32_f16_e32 v2, v296; VI-NEXT: v_mac_f32_e32 v2, v0, v197; VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD98; VI-NEXT: v_or_b32_e32 v0, 0x3c00, v099; VI-NEXT: s_setpc_b64 s[30:31]100;101; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:102; SDAG-CI: ; %bb.0:103; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)104; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1105; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2106; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v0107; SDAG-CI-NEXT: v_mov_b32_e32 v0, 1.0108; SDAG-CI-NEXT: s_setpc_b64 s[30:31]109;110; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:111; GISEL-GFX11: ; %bb.0:112; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; GISEL-GFX11-NEXT: v_mov_b32_e32 v3, 0x3c00114; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)115; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]116; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, v3117; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]118;119; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo:120; GISEL-CI: ; %bb.0:121; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0123; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1124; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2125; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1126; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v2127; GISEL-CI-NEXT: v_mov_b32_e32 v0, 0x3c00128; GISEL-CI-NEXT: s_setpc_b64 s[30:31]129 %src0.ext = fpext half %src0 to float130 %src1.ext = fpext half %src1 to float131 %src2.ext = fpext half %src2 to float132 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)133 %cvt.result = fptrunc float %result to half134 %vec.result = insertelement <2 x half> <half 1.0, half poison>, half %cvt.result, i32 1135 ret <2 x half> %vec.result136}137 138define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src1, half %src2, half %lo) #0 {139; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:140; SDAG-GFX11-TRUE16: ; %bb.0:141; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]143; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l144; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]145;146; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:147; SDAG-GFX11-FAKE16: ; %bb.0:148; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; SDAG-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]150; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)151; SDAG-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v3152; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]153;154; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:155; GFX9: ; %bb.0:156; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]158; GFX9-NEXT: v_mov_b32_e32 v0, v3159; GFX9-NEXT: s_setpc_b64 s[30:31]160;161; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:162; VI: ; %bb.0:163; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; VI-NEXT: v_cvt_f32_f16_e32 v0, v0165; VI-NEXT: v_cvt_f32_f16_e32 v1, v1166; VI-NEXT: v_cvt_f32_f16_e32 v2, v2167; VI-NEXT: v_mac_f32_e32 v2, v0, v1168; VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD169; VI-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD170; VI-NEXT: s_setpc_b64 s[30:31]171;172; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:173; SDAG-CI: ; %bb.0:174; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1176; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2177; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v0178; SDAG-CI-NEXT: v_mov_b32_e32 v0, v3179; SDAG-CI-NEXT: s_setpc_b64 s[30:31]180;181; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:182; GISEL-GFX11: ; %bb.0:183; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)184; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]185; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)186; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, v3187; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]188;189; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo:190; GISEL-CI: ; %bb.0:191; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)192; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0193; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1194; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2195; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1196; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v2197; GISEL-CI-NEXT: v_mov_b32_e32 v0, v3198; GISEL-CI-NEXT: s_setpc_b64 s[30:31]199 %src0.ext = fpext half %src0 to float200 %src1.ext = fpext half %src1 to float201 %src2.ext = fpext half %src2 to float202 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)203 %cvt.result = fptrunc float %result to half204 %vec = insertelement <2 x half> poison, half %lo, i32 0205 %vec.result = insertelement <2 x half> %vec, half %cvt.result, i32 1206 ret <2 x half> %vec.result207}208 209define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {210; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:211; SDAG-GFX11-TRUE16: ; %bb.0:212; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)213; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]214; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0215; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]216;217; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:218; SDAG-GFX11-FAKE16: ; %bb.0:219; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; SDAG-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]221; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)222; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0223; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]224;225; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:226; SDAG-GFX9: ; %bb.0:227; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)228; SDAG-GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]229; SDAG-GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0230; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]231;232; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:233; VI: ; %bb.0:234; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)235; VI-NEXT: v_cvt_f32_f16_e32 v0, v0236; VI-NEXT: v_cvt_f32_f16_e32 v1, v1237; VI-NEXT: v_cvt_f32_f16_e32 v2, v2238; VI-NEXT: v_mac_f32_e32 v2, v0, v1239; VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD240; VI-NEXT: s_setpc_b64 s[30:31]241;242; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:243; SDAG-CI: ; %bb.0:244; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1246; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2247; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0248; SDAG-CI-NEXT: s_setpc_b64 s[30:31]249;250; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:251; GISEL-GFX11: ; %bb.0:252; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)253; GISEL-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]254; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)255; GISEL-GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0256; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0257; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]258;259; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:260; GISEL-GFX9: ; %bb.0:261; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)262; GISEL-GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]263; GISEL-GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0264; GISEL-GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0265; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]266;267; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:268; GISEL-CI: ; %bb.0:269; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)270; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0271; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1272; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2273; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1274; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2275; GISEL-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0276; GISEL-CI-NEXT: s_setpc_b64 s[30:31]277 %src0.ext = fpext half %src0 to float278 %src1.ext = fpext half %src1 to float279 %src2.ext = fpext half %src2 to float280 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)281 %cvt.result = fptrunc float %result to half282 %bc = bitcast half %cvt.result to i16283 %ext = zext i16 %bc to i32284 %shr = shl i32 %ext, 16285 ret i32 %shr286}287 288define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {289; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:290; SDAG-GFX11-TRUE16: ; %bb.0:291; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)292; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]293; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0294; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]295;296; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:297; SDAG-GFX11-FAKE16: ; %bb.0:298; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)299; SDAG-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]300; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)301; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0302; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]303;304; SDAG-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:305; SDAG-GFX9: ; %bb.0:306; SDAG-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)307; SDAG-GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]308; SDAG-GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0309; SDAG-GFX9-NEXT: s_setpc_b64 s[30:31]310;311; SDAG-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:312; SDAG-VI: ; %bb.0:313; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)314; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0315; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1316; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v2, v2317; SDAG-VI-NEXT: v_mac_f32_e32 v2, v0, v1318; SDAG-VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD319; SDAG-VI-NEXT: s_setpc_b64 s[30:31]320;321; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:322; SDAG-CI: ; %bb.0:323; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)324; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1325; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2326; SDAG-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0327; SDAG-CI-NEXT: s_setpc_b64 s[30:31]328;329; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:330; GISEL-GFX11: ; %bb.0:331; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)332; GISEL-GFX11-NEXT: v_fma_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]333; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)334; GISEL-GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16335; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0336; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]337;338; GISEL-GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:339; GISEL-GFX9: ; %bb.0:340; GISEL-GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; GISEL-GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]342; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, 16343; GISEL-GFX9-NEXT: v_lshlrev_b32_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0344; GISEL-GFX9-NEXT: s_setpc_b64 s[30:31]345;346; GISEL-VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:347; GISEL-VI: ; %bb.0:348; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)349; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v0350; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1351; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v2352; GISEL-VI-NEXT: v_mac_f32_e32 v2, v0, v1353; GISEL-VI-NEXT: v_cvt_f16_f32_e32 v0, v2354; GISEL-VI-NEXT: v_mov_b32_e32 v1, 16355; GISEL-VI-NEXT: v_lshlrev_b32_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0356; GISEL-VI-NEXT: s_setpc_b64 s[30:31]357;358; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:359; GISEL-CI: ; %bb.0:360; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)361; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0362; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1363; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2364; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1365; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2366; GISEL-CI-NEXT: v_bfe_i32 v0, v0, 0, 16367; GISEL-CI-NEXT: v_lshlrev_b32_e32 v0, 16, v0368; GISEL-CI-NEXT: s_setpc_b64 s[30:31]369 %src0.ext = fpext half %src0 to float370 %src1.ext = fpext half %src1 to float371 %src2.ext = fpext half %src2 to float372 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)373 %cvt.result = fptrunc float %result to half374 %bc = bitcast half %cvt.result to i16375 %ext = sext i16 %bc to i32376 %shr = shl i32 %ext, 16377 ret i32 %shr378}379 380define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {381; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:382; SDAG-GFX11-TRUE16: ; %bb.0:383; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)384; SDAG-GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp385; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)386; SDAG-GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v0387; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]388;389; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:390; SDAG-GFX11-FAKE16: ; %bb.0:391; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)392; SDAG-GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp393; SDAG-GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)394; SDAG-GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0395; SDAG-GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0396; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]397;398; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:399; GFX9: ; %bb.0:400; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)401; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp402; GFX9-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD403; GFX9-NEXT: s_setpc_b64 s[30:31]404;405; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:406; VI: ; %bb.0:407; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)408; VI-NEXT: v_cvt_f32_f16_e32 v0, v0409; VI-NEXT: v_cvt_f32_f16_e32 v1, v1410; VI-NEXT: v_cvt_f32_f16_e32 v2, v2411; VI-NEXT: v_mad_f32 v0, v0, v1, v2 clamp412; VI-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD413; VI-NEXT: s_setpc_b64 s[30:31]414;415; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:416; SDAG-CI: ; %bb.0:417; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)418; SDAG-CI-NEXT: v_mad_f32 v0, v0, v1, v2 clamp419; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v0420; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v0421; SDAG-CI-NEXT: s_setpc_b64 s[30:31]422;423; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:424; GISEL-GFX11: ; %bb.0:425; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)426; GISEL-GFX11-NEXT: v_fma_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp427; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)428; GISEL-GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0429; GISEL-GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0430; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]431;432; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:433; GISEL-CI: ; %bb.0:434; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)435; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0436; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1437; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2438; GISEL-CI-NEXT: v_mad_f32 v0, v0, v1, v2 clamp439; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v0440; GISEL-CI-NEXT: s_setpc_b64 s[30:31]441 %src0.ext = fpext half %src0 to float442 %src1.ext = fpext half %src1 to float443 %src2.ext = fpext half %src2 to float444 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)445 %max = call float @llvm.maxnum.f32(float %result, float 0.0)446 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)447 %cvt.result = fptrunc float %clamp to half448 %vec.result = insertelement <2 x half> poison, half %cvt.result, i32 1449 ret <2 x half> %vec.result450}451 452define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {453; GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:454; GFX11: ; %bb.0:455; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)456; GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp457; GFX11-NEXT: s_setpc_b64 s[30:31]458;459; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:460; GFX9: ; %bb.0:461; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)462; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp463; GFX9-NEXT: s_setpc_b64 s[30:31]464;465; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:466; VI: ; %bb.0:467; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; VI-NEXT: v_cvt_f32_f16_e32 v0, v0469; VI-NEXT: v_cvt_f32_f16_e32 v1, v1470; VI-NEXT: v_cvt_f32_f16_e32 v2, v2471; VI-NEXT: v_mac_f32_e32 v2, v0, v1472; VI-NEXT: v_cvt_f16_f32_sdwa v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD473; VI-NEXT: s_setpc_b64 s[30:31]474;475; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:476; SDAG-CI: ; %bb.0:477; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)478; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1479; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2480; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v1, v0 clamp481; SDAG-CI-NEXT: s_setpc_b64 s[30:31]482;483; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:484; GISEL-CI: ; %bb.0:485; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)486; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0487; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1488; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2489; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1490; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2491; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0492; GISEL-CI-NEXT: v_max_f32_e32 v0, 0, v0493; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v0494; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0495; GISEL-CI-NEXT: v_min_f32_e32 v0, 1.0, v0496; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v0497; GISEL-CI-NEXT: s_setpc_b64 s[30:31]498 %src0.ext = fpext half %src0 to float499 %src1.ext = fpext half %src1 to float500 %src2.ext = fpext half %src2 to float501 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)502 %cvt.result = fptrunc float %result to half503 %max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)504 %clamp = call half @llvm.minnum.f16(half %max, half 1.0)505 %vec.result = insertelement <2 x half> poison, half %clamp, i32 1506 ret <2 x half> %vec.result507}508 509define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use(half %src0, half %src1, half %src2) #0 {510; SDAG-GFX11-TRUE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:511; SDAG-GFX11-TRUE16: ; %bb.0:512; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)513; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l514; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)515; SDAG-GFX11-TRUE16-NEXT: v_fma_mixlo_f16 v0, v3, v1, v2 op_sel_hi:[1,1,1]516; SDAG-GFX11-TRUE16-NEXT: v_fma_mixhi_f16 v0, v3, v1, v2 op_sel_hi:[1,1,1] clamp517; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off dlc518; SDAG-GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0519; SDAG-GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]520;521; SDAG-GFX11-FAKE16-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:522; SDAG-GFX11-FAKE16: ; %bb.0:523; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)524; SDAG-GFX11-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]525; SDAG-GFX11-FAKE16-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp526; SDAG-GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v3, off dlc527; SDAG-GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0528; SDAG-GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]529;530; GFX9-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:531; GFX9: ; %bb.0:532; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)533; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]534; GFX9-NEXT: global_store_short v[0:1], v3, off535; GFX9-NEXT: s_waitcnt vmcnt(0)536; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp537; GFX9-NEXT: s_setpc_b64 s[30:31]538;539; VI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:540; VI: ; %bb.0:541; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)542; VI-NEXT: v_cvt_f32_f16_e32 v0, v0543; VI-NEXT: v_cvt_f32_f16_e32 v1, v1544; VI-NEXT: v_cvt_f32_f16_e32 v2, v2545; VI-NEXT: v_mac_f32_e32 v2, v0, v1546; VI-NEXT: v_cvt_f16_f32_e32 v0, v2547; VI-NEXT: flat_store_short v[0:1], v0548; VI-NEXT: s_waitcnt vmcnt(0)549; VI-NEXT: v_max_f16_sdwa v0, v0, v0 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD550; VI-NEXT: s_setpc_b64 s[30:31]551;552; SDAG-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:553; SDAG-CI: ; %bb.0:554; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)555; SDAG-CI-NEXT: v_mac_f32_e32 v2, v0, v1556; SDAG-CI-NEXT: v_cvt_f16_f32_e32 v0, v2557; SDAG-CI-NEXT: s_mov_b32 s7, 0xf000558; SDAG-CI-NEXT: s_mov_b32 s6, -1559; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v1, v0 clamp560; SDAG-CI-NEXT: buffer_store_short v0, off, s[4:7], 0561; SDAG-CI-NEXT: s_waitcnt vmcnt(0)562; SDAG-CI-NEXT: s_setpc_b64 s[30:31]563;564; GISEL-GFX11-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:565; GISEL-GFX11: ; %bb.0:566; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)567; GISEL-GFX11-NEXT: v_fma_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]568; GISEL-GFX11-NEXT: v_fma_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp569; GISEL-GFX11-NEXT: global_store_b16 v[0:1], v3, off dlc570; GISEL-GFX11-NEXT: s_waitcnt_vscnt null, 0x0571; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31]572;573; GISEL-CI-LABEL: v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:574; GISEL-CI: ; %bb.0:575; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)576; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0577; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1578; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2579; GISEL-CI-NEXT: s_mov_b32 s6, -1580; GISEL-CI-NEXT: s_mov_b32 s7, 0xf000581; GISEL-CI-NEXT: v_mac_f32_e32 v2, v0, v1582; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v0, v2583; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v0584; GISEL-CI-NEXT: buffer_store_short v0, off, s[4:7], 0585; GISEL-CI-NEXT: s_waitcnt vmcnt(0)586; GISEL-CI-NEXT: v_max_f32_e32 v1, 0, v1587; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v1588; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1589; GISEL-CI-NEXT: v_min_f32_e32 v1, 1.0, v1590; GISEL-CI-NEXT: v_cvt_f16_f32_e32 v1, v1591; GISEL-CI-NEXT: s_setpc_b64 s[30:31]592 %src0.ext = fpext half %src0 to float593 %src1.ext = fpext half %src1 to float594 %src2.ext = fpext half %src2 to float595 %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)596 %cvt.result = fptrunc float %result to half597 store volatile half %cvt.result, ptr addrspace(1) poison598 %max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)599 %clamp = call half @llvm.minnum.f16(half %max, half 1.0)600 %vec.result = insertelement <2 x half> poison, half %clamp, i32 1601 ret <2 x half> %vec.result602}603 604declare half @llvm.minnum.f16(half, half) #1605declare half @llvm.maxnum.f16(half, half) #1606declare float @llvm.minnum.f32(float, float) #1607declare float @llvm.maxnum.f32(float, float) #1608declare float @llvm.fmuladd.f32(float, float, float) #1609declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1610 611attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }612attributes #1 = { nounwind readnone speculatable }613;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:614; GISEL-GFX11-FAKE16: {{.*}}615; SDAG-GFX11: {{.*}}616