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1; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s2 3; If the workgroup id range is restricted, we should be able to use4; mad24 for the usual indexing pattern.5 6declare i32 @llvm.amdgcn.workgroup.id.x() #07declare i32 @llvm.amdgcn.workitem.id.x() #08declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #09 10; GCN-LABEL: {{^}}get_global_id_0:11; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff12; GCN: s_mul_i32 [[MUL:s[0-9]+]], s14, [[WGSIZEX]]13; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, [[MUL]], v014define amdgpu_kernel void @get_global_id_0(ptr addrspace(1) %out) #1 {15 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()16 %gep = getelementptr inbounds i32, ptr addrspace(4) %dispatch.ptr, i64 117 %workgroup.size.xy = load i32, ptr addrspace(4) %gep, align 4, !invariant.load !018 %workgroup.size.x = and i32 %workgroup.size.xy, 6553519 20 %workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !121 %workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !222 23 %mul = mul i32 %workgroup.id.x, %workgroup.size.x24 %add = add i32 %mul, %workitem.id.x25 26 store i32 %add, ptr addrspace(1) %out, align 427 ret void28}29 30attributes #0 = { nounwind readnone }31attributes #1 = { nounwind }32 33!0 = !{}34!1 = !{i32 0, i32 1024}35!2 = !{i32 0, i32 16777216}36