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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CI %s3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX9 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11,GFX1100 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 < %s | FileCheck -check-prefixes=GFX11,GFX1150 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s8; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s9; RUN: llc -mtriple=amdgcn -mcpu=gfx11-generic --amdhsa-code-object-version=6 < %s | FileCheck -check-prefixes=GFX11,GFX1100 %s10 11; On GFX11, ensure vdst and src2 do not partially overlap. Full overlap is ok.12 13define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {14; CI-LABEL: mad_i64_i32_sextops:15; CI: ; %bb.0:16; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]18; CI-NEXT: s_setpc_b64 s[30:31]19;20; SI-LABEL: mad_i64_i32_sextops:21; SI: ; %bb.0:22; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; SI-NEXT: v_mul_lo_u32 v4, v0, v124; SI-NEXT: v_mul_hi_i32 v1, v0, v125; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v226; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc27; SI-NEXT: s_setpc_b64 s[30:31]28;29; GFX9-LABEL: mad_i64_i32_sextops:30; GFX9: ; %bb.0:31; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]33; GFX9-NEXT: s_setpc_b64 s[30:31]34;35; GFX1100-LABEL: mad_i64_i32_sextops:36; GFX1100: ; %bb.0:37; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)38; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v039; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)40; GFX1100-NEXT: v_mad_i64_i32 v[0:1], null, v5, v4, v[2:3]41; GFX1100-NEXT: s_setpc_b64 s[30:31]42;43; GFX1150-LABEL: mad_i64_i32_sextops:44; GFX1150: ; %bb.0:45; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)46; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, v[2:3]47; GFX1150-NEXT: s_setpc_b64 s[30:31]48;49; GFX12-LABEL: mad_i64_i32_sextops:50; GFX12: ; %bb.0:51; GFX12-NEXT: s_wait_loadcnt_dscnt 0x052; GFX12-NEXT: s_wait_expcnt 0x053; GFX12-NEXT: s_wait_samplecnt 0x054; GFX12-NEXT: s_wait_bvhcnt 0x055; GFX12-NEXT: s_wait_kmcnt 0x056; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, v[2:3]57; GFX12-NEXT: s_setpc_b64 s[30:31]58;59; GFX1250-LABEL: mad_i64_i32_sextops:60; GFX1250: ; %bb.0:61; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x062; GFX1250-NEXT: s_wait_kmcnt 0x063; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v0, v1, v[2:3]64; GFX1250-NEXT: s_set_pc_i64 s[30:31]65 %sext0 = sext i32 %arg0 to i6466 %sext1 = sext i32 %arg1 to i6467 %mul = mul i64 %sext0, %sext168 %mad = add i64 %mul, %arg269 ret i64 %mad70}71 72define i64 @mad_i64_i32_sextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {73; CI-LABEL: mad_i64_i32_sextops_commute:74; CI: ; %bb.0:75; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]77; CI-NEXT: s_setpc_b64 s[30:31]78;79; SI-LABEL: mad_i64_i32_sextops_commute:80; SI: ; %bb.0:81; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)82; SI-NEXT: v_mul_lo_u32 v4, v0, v183; SI-NEXT: v_mul_hi_i32 v1, v0, v184; SI-NEXT: v_add_i32_e32 v0, vcc, v2, v485; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc86; SI-NEXT: s_setpc_b64 s[30:31]87;88; GFX9-LABEL: mad_i64_i32_sextops_commute:89; GFX9: ; %bb.0:90; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)91; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]92; GFX9-NEXT: s_setpc_b64 s[30:31]93;94; GFX1100-LABEL: mad_i64_i32_sextops_commute:95; GFX1100: ; %bb.0:96; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)97; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v098; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)99; GFX1100-NEXT: v_mad_i64_i32 v[0:1], null, v5, v4, v[2:3]100; GFX1100-NEXT: s_setpc_b64 s[30:31]101;102; GFX1150-LABEL: mad_i64_i32_sextops_commute:103; GFX1150: ; %bb.0:104; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)105; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, v[2:3]106; GFX1150-NEXT: s_setpc_b64 s[30:31]107;108; GFX12-LABEL: mad_i64_i32_sextops_commute:109; GFX12: ; %bb.0:110; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0111; GFX12-NEXT: s_wait_expcnt 0x0112; GFX12-NEXT: s_wait_samplecnt 0x0113; GFX12-NEXT: s_wait_bvhcnt 0x0114; GFX12-NEXT: s_wait_kmcnt 0x0115; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, v[2:3]116; GFX12-NEXT: s_setpc_b64 s[30:31]117;118; GFX1250-LABEL: mad_i64_i32_sextops_commute:119; GFX1250: ; %bb.0:120; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0121; GFX1250-NEXT: s_wait_kmcnt 0x0122; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v0, v1, v[2:3]123; GFX1250-NEXT: s_set_pc_i64 s[30:31]124 %sext0 = sext i32 %arg0 to i64125 %sext1 = sext i32 %arg1 to i64126 %mul = mul i64 %sext0, %sext1127 %mad = add i64 %arg2, %mul128 ret i64 %mad129}130 131define i64 @mad_u64_u32_zextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {132; CI-LABEL: mad_u64_u32_zextops:133; CI: ; %bb.0:134; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)135; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]136; CI-NEXT: s_setpc_b64 s[30:31]137;138; SI-LABEL: mad_u64_u32_zextops:139; SI: ; %bb.0:140; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; SI-NEXT: v_mul_lo_u32 v4, v0, v1142; SI-NEXT: v_mul_hi_u32 v1, v0, v1143; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v2144; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc145; SI-NEXT: s_setpc_b64 s[30:31]146;147; GFX9-LABEL: mad_u64_u32_zextops:148; GFX9: ; %bb.0:149; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)150; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]151; GFX9-NEXT: s_setpc_b64 s[30:31]152;153; GFX1100-LABEL: mad_u64_u32_zextops:154; GFX1100: ; %bb.0:155; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)156; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0157; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)158; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v5, v4, v[2:3]159; GFX1100-NEXT: s_setpc_b64 s[30:31]160;161; GFX1150-LABEL: mad_u64_u32_zextops:162; GFX1150: ; %bb.0:163; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]165; GFX1150-NEXT: s_setpc_b64 s[30:31]166;167; GFX12-LABEL: mad_u64_u32_zextops:168; GFX12: ; %bb.0:169; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0170; GFX12-NEXT: s_wait_expcnt 0x0171; GFX12-NEXT: s_wait_samplecnt 0x0172; GFX12-NEXT: s_wait_bvhcnt 0x0173; GFX12-NEXT: s_wait_kmcnt 0x0174; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v1, v[2:3]175; GFX12-NEXT: s_setpc_b64 s[30:31]176;177; GFX1250-LABEL: mad_u64_u32_zextops:178; GFX1250: ; %bb.0:179; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0180; GFX1250-NEXT: s_wait_kmcnt 0x0181; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, v1, v[2:3]182; GFX1250-NEXT: s_set_pc_i64 s[30:31]183 %sext0 = zext i32 %arg0 to i64184 %sext1 = zext i32 %arg1 to i64185 %mul = mul i64 %sext0, %sext1186 %mad = add i64 %mul, %arg2187 ret i64 %mad188}189 190define i64 @mad_u64_u32_zextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {191; CI-LABEL: mad_u64_u32_zextops_commute:192; CI: ; %bb.0:193; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)194; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]195; CI-NEXT: s_setpc_b64 s[30:31]196;197; SI-LABEL: mad_u64_u32_zextops_commute:198; SI: ; %bb.0:199; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)200; SI-NEXT: v_mul_lo_u32 v4, v0, v1201; SI-NEXT: v_mul_hi_u32 v1, v0, v1202; SI-NEXT: v_add_i32_e32 v0, vcc, v2, v4203; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc204; SI-NEXT: s_setpc_b64 s[30:31]205;206; GFX9-LABEL: mad_u64_u32_zextops_commute:207; GFX9: ; %bb.0:208; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]210; GFX9-NEXT: s_setpc_b64 s[30:31]211;212; GFX1100-LABEL: mad_u64_u32_zextops_commute:213; GFX1100: ; %bb.0:214; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)215; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0216; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)217; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v5, v4, v[2:3]218; GFX1100-NEXT: s_setpc_b64 s[30:31]219;220; GFX1150-LABEL: mad_u64_u32_zextops_commute:221; GFX1150: ; %bb.0:222; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]224; GFX1150-NEXT: s_setpc_b64 s[30:31]225;226; GFX12-LABEL: mad_u64_u32_zextops_commute:227; GFX12: ; %bb.0:228; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0229; GFX12-NEXT: s_wait_expcnt 0x0230; GFX12-NEXT: s_wait_samplecnt 0x0231; GFX12-NEXT: s_wait_bvhcnt 0x0232; GFX12-NEXT: s_wait_kmcnt 0x0233; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v1, v[2:3]234; GFX12-NEXT: s_setpc_b64 s[30:31]235;236; GFX1250-LABEL: mad_u64_u32_zextops_commute:237; GFX1250: ; %bb.0:238; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0239; GFX1250-NEXT: s_wait_kmcnt 0x0240; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, v1, v[2:3]241; GFX1250-NEXT: s_set_pc_i64 s[30:31]242 %sext0 = zext i32 %arg0 to i64243 %sext1 = zext i32 %arg1 to i64244 %mul = mul i64 %sext0, %sext1245 %mad = add i64 %arg2, %mul246 ret i64 %mad247}248 249define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {250; CI-LABEL: mad_i64_i32_sextops_i32_i128:251; CI: ; %bb.0:252; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)253; CI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0254; CI-NEXT: v_ashrrev_i32_e32 v12, 31, v0255; CI-NEXT: v_mov_b32_e32 v8, 0256; CI-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v12, v1, v[7:8]257; CI-NEXT: v_ashrrev_i32_e32 v13, 31, v1258; CI-NEXT: v_mov_b32_e32 v7, v9259; CI-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v0, v13, v[7:8]260; CI-NEXT: v_add_i32_e32 v8, vcc, v10, v8261; CI-NEXT: v_mad_i64_i32 v[10:11], s[4:5], v1, v12, 0262; CI-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, vcc263; CI-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v13, v[8:9]264; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v13, v0, v[10:11]265; CI-NEXT: v_add_i32_e32 v8, vcc, v8, v0266; CI-NEXT: v_addc_u32_e32 v9, vcc, v9, v1, vcc267; CI-NEXT: v_add_i32_e32 v0, vcc, v6, v2268; CI-NEXT: v_addc_u32_e32 v1, vcc, v7, v3, vcc269; CI-NEXT: v_addc_u32_e32 v2, vcc, v8, v4, vcc270; CI-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc271; CI-NEXT: s_setpc_b64 s[30:31]272;273; SI-LABEL: mad_i64_i32_sextops_i32_i128:274; SI: ; %bb.0:275; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)276; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v0277; SI-NEXT: v_mul_lo_u32 v11, v6, v1278; SI-NEXT: v_mul_hi_u32 v12, v0, v1279; SI-NEXT: v_ashrrev_i32_e32 v7, 31, v1280; SI-NEXT: v_mul_hi_u32 v14, v6, v1281; SI-NEXT: v_mul_lo_u32 v13, v0, v7282; SI-NEXT: v_mul_hi_u32 v10, v0, v7283; SI-NEXT: v_add_i32_e32 v12, vcc, v11, v12284; SI-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc285; SI-NEXT: v_mul_hi_u32 v8, v6, v7286; SI-NEXT: v_add_i32_e32 v12, vcc, v13, v12287; SI-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc288; SI-NEXT: v_mul_i32_i24_e32 v9, v6, v7289; SI-NEXT: v_add_i32_e32 v10, vcc, v14, v10290; SI-NEXT: v_mul_hi_i32 v6, v1, v6291; SI-NEXT: v_mul_hi_i32 v7, v7, v0292; SI-NEXT: v_addc_u32_e64 v14, s[4:5], 0, 0, vcc293; SI-NEXT: v_add_i32_e32 v9, vcc, v9, v10294; SI-NEXT: v_addc_u32_e32 v8, vcc, v8, v14, vcc295; SI-NEXT: v_add_i32_e32 v10, vcc, v13, v11296; SI-NEXT: v_mul_lo_u32 v0, v0, v1297; SI-NEXT: v_addc_u32_e32 v6, vcc, v7, v6, vcc298; SI-NEXT: v_add_i32_e32 v7, vcc, v9, v10299; SI-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc300; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v2301; SI-NEXT: v_addc_u32_e32 v1, vcc, v12, v3, vcc302; SI-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc303; SI-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc304; SI-NEXT: s_setpc_b64 s[30:31]305;306; GFX9-LABEL: mad_i64_i32_sextops_i32_i128:307; GFX9: ; %bb.0:308; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)309; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0310; GFX9-NEXT: v_ashrrev_i32_e32 v12, 31, v0311; GFX9-NEXT: v_mov_b32_e32 v9, 0312; GFX9-NEXT: v_mov_b32_e32 v8, v7313; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v12, v1, v[8:9]314; GFX9-NEXT: v_ashrrev_i32_e32 v14, 31, v1315; GFX9-NEXT: v_mov_b32_e32 v8, v10316; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v14, v[8:9]317; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v9318; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, 0, vcc319; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v12, v14, v[10:11]320; GFX9-NEXT: v_mad_i64_i32 v[12:13], s[4:5], v1, v12, 0321; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[12:13]322; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v10, v0323; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v11, v1, vcc324; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2325; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc326; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc327; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v5, vcc328; GFX9-NEXT: s_setpc_b64 s[30:31]329;330; GFX1100-LABEL: mad_i64_i32_sextops_i32_i128:331; GFX1100: ; %bb.0:332; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)333; GFX1100-NEXT: v_mad_u64_u32 v[6:7], null, v0, v1, 0334; GFX1100-NEXT: v_mov_b32_e32 v8, 0335; GFX1100-NEXT: v_ashrrev_i32_e32 v14, 31, v0336; GFX1100-NEXT: v_ashrrev_i32_e32 v15, 31, v1337; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)338; GFX1100-NEXT: v_mad_u64_u32 v[9:10], null, v14, v1, v[7:8]339; GFX1100-NEXT: v_mov_b32_e32 v7, v9340; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)341; GFX1100-NEXT: v_mad_u64_u32 v[11:12], null, v0, v15, v[7:8]342; GFX1100-NEXT: v_mad_i64_i32 v[7:8], null, v1, v14, 0343; GFX1100-NEXT: v_add_co_u32 v9, s0, v10, v12344; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)345; GFX1100-NEXT: v_add_co_ci_u32_e64 v10, null, 0, 0, s0346; GFX1100-NEXT: v_mad_i64_i32 v[12:13], null, v15, v0, v[7:8]347; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)348; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v14, v15, v[9:10]349; GFX1100-NEXT: v_add_co_u32 v7, vcc_lo, v0, v12350; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)351; GFX1100-NEXT: v_add_co_ci_u32_e64 v8, null, v1, v13, vcc_lo352; GFX1100-NEXT: v_add_co_u32 v0, vcc_lo, v6, v2353; GFX1100-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v11, v3, vcc_lo354; GFX1100-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v7, v4, vcc_lo355; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4)356; GFX1100-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v8, v5, vcc_lo357; GFX1100-NEXT: s_setpc_b64 s[30:31]358;359; GFX1150-LABEL: mad_i64_i32_sextops_i32_i128:360; GFX1150: ; %bb.0:361; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)362; GFX1150-NEXT: v_mad_u64_u32 v[6:7], null, v0, v1, 0363; GFX1150-NEXT: v_mov_b32_e32 v8, 0364; GFX1150-NEXT: v_ashrrev_i32_e32 v13, 31, v0365; GFX1150-NEXT: v_ashrrev_i32_e32 v14, 31, v1366; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)367; GFX1150-NEXT: v_mad_i64_i32 v[11:12], null, v1, v13, 0368; GFX1150-NEXT: v_mad_u64_u32 v[9:10], null, v13, v1, v[7:8]369; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)370; GFX1150-NEXT: v_mov_b32_e32 v7, v9371; GFX1150-NEXT: v_mad_u64_u32 v[7:8], null, v0, v14, v[7:8]372; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)373; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v14, v0, v[11:12]374; GFX1150-NEXT: v_add_co_u32 v8, s0, v10, v8375; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)376; GFX1150-NEXT: v_add_co_ci_u32_e64 v9, null, 0, 0, s0377; GFX1150-NEXT: v_mad_u64_u32 v[8:9], null, v13, v14, v[8:9]378; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)379; GFX1150-NEXT: v_add_co_u32 v8, vcc_lo, v8, v0380; GFX1150-NEXT: v_add_co_ci_u32_e64 v9, null, v9, v1, vcc_lo381; GFX1150-NEXT: v_add_co_u32 v0, vcc_lo, v6, v2382; GFX1150-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v3, vcc_lo383; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)384; GFX1150-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v8, v4, vcc_lo385; GFX1150-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v5, vcc_lo386; GFX1150-NEXT: s_setpc_b64 s[30:31]387;388; GFX12-LABEL: mad_i64_i32_sextops_i32_i128:389; GFX12: ; %bb.0:390; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0391; GFX12-NEXT: s_wait_expcnt 0x0392; GFX12-NEXT: s_wait_samplecnt 0x0393; GFX12-NEXT: s_wait_bvhcnt 0x0394; GFX12-NEXT: s_wait_kmcnt 0x0395; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, v0, v1, 0396; GFX12-NEXT: v_mov_b32_e32 v8, 0397; GFX12-NEXT: v_ashrrev_i32_e32 v13, 31, v0398; GFX12-NEXT: v_ashrrev_i32_e32 v14, 31, v1399; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)400; GFX12-NEXT: v_mad_co_i64_i32 v[11:12], null, v1, v13, 0401; GFX12-NEXT: v_mad_co_u64_u32 v[9:10], null, v13, v1, v[7:8]402; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)403; GFX12-NEXT: v_mov_b32_e32 v7, v9404; GFX12-NEXT: v_mad_co_u64_u32 v[7:8], null, v0, v14, v[7:8]405; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)406; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v14, v0, v[11:12]407; GFX12-NEXT: v_add_co_u32 v8, s0, v10, v8408; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)409; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, 0, 0, s0410; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)411; GFX12-NEXT: v_mad_co_u64_u32 v[8:9], null, v13, v14, v[8:9]412; GFX12-NEXT: v_add_co_u32 v8, vcc_lo, v8, v0413; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)414; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)415; GFX12-NEXT: v_add_co_ci_u32_e64 v9, null, v9, v1, vcc_lo416; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v6, v2417; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)418; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v3, vcc_lo419; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)420; GFX12-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v8, v4, vcc_lo421; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)422; GFX12-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v5, vcc_lo423; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)424; GFX12-NEXT: s_setpc_b64 s[30:31]425;426; GFX1250-LABEL: mad_i64_i32_sextops_i32_i128:427; GFX1250: ; %bb.0:428; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0429; GFX1250-NEXT: s_wait_kmcnt 0x0430; GFX1250-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v9, 0431; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)432; GFX1250-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v1, v9433; GFX1250-NEXT: v_mov_b32_e32 v21, v9434; GFX1250-NEXT: v_mul_u64_e32 v[10:11], v[0:1], v[8:9]435; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)436; GFX1250-NEXT: v_dual_ashrrev_i32 v12, 31, v0 :: v_dual_mov_b32 v8, v11437; GFX1250-NEXT: v_dual_ashrrev_i32 v7, 31, v6 :: v_dual_mov_b32 v13, v12438; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)439; GFX1250-NEXT: v_mad_nc_u64_u32 v[14:15], v12, v6, v[8:9]440; GFX1250-NEXT: v_mul_u64_e32 v[16:17], v[6:7], v[12:13]441; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)442; GFX1250-NEXT: v_mov_b32_e32 v8, v14443; GFX1250-NEXT: v_mad_nc_u64_u32 v[18:19], v0, v7, v[8:9]444; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)445; GFX1250-NEXT: v_dual_mov_b32 v8, v15 :: v_dual_mov_b32 v20, v19446; GFX1250-NEXT: v_add_nc_u64_e32 v[8:9], v[8:9], v[20:21]447; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v7, v0, v[16:17]448; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)449; GFX1250-NEXT: v_mad_nc_u64_u32 v[8:9], v12, v7, v[8:9]450; GFX1250-NEXT: v_add_nc_u64_e32 v[6:7], v[8:9], v[0:1]451; GFX1250-NEXT: v_add_co_u32 v0, vcc_lo, v10, v2452; GFX1250-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v18, v3, vcc_lo453; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)454; GFX1250-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v6, v4, vcc_lo455; GFX1250-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v7, v5, vcc_lo456; GFX1250-NEXT: s_set_pc_i64 s[30:31]457 %sext0 = sext i32 %arg0 to i128458 %sext1 = sext i32 %arg1 to i128459 %mul = mul i128 %sext0, %sext1460 %mad = add i128 %mul, %arg2461 ret i128 %mad462}463 464define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {465; CI-LABEL: mad_i64_i32_sextops_i32_i63:466; CI: ; %bb.0:467; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]469; CI-NEXT: s_setpc_b64 s[30:31]470;471; SI-LABEL: mad_i64_i32_sextops_i32_i63:472; SI: ; %bb.0:473; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)474; SI-NEXT: v_mul_lo_u32 v4, v0, v1475; SI-NEXT: v_mul_hi_i32 v1, v0, v1476; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v2477; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc478; SI-NEXT: s_setpc_b64 s[30:31]479;480; GFX9-LABEL: mad_i64_i32_sextops_i32_i63:481; GFX9: ; %bb.0:482; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]484; GFX9-NEXT: s_setpc_b64 s[30:31]485;486; GFX1100-LABEL: mad_i64_i32_sextops_i32_i63:487; GFX1100: ; %bb.0:488; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)489; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0490; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)491; GFX1100-NEXT: v_mad_i64_i32 v[0:1], null, v5, v4, v[2:3]492; GFX1100-NEXT: s_setpc_b64 s[30:31]493;494; GFX1150-LABEL: mad_i64_i32_sextops_i32_i63:495; GFX1150: ; %bb.0:496; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)497; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, v[2:3]498; GFX1150-NEXT: s_setpc_b64 s[30:31]499;500; GFX12-LABEL: mad_i64_i32_sextops_i32_i63:501; GFX12: ; %bb.0:502; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0503; GFX12-NEXT: s_wait_expcnt 0x0504; GFX12-NEXT: s_wait_samplecnt 0x0505; GFX12-NEXT: s_wait_bvhcnt 0x0506; GFX12-NEXT: s_wait_kmcnt 0x0507; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, v[2:3]508; GFX12-NEXT: s_setpc_b64 s[30:31]509;510; GFX1250-LABEL: mad_i64_i32_sextops_i32_i63:511; GFX1250: ; %bb.0:512; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0513; GFX1250-NEXT: s_wait_kmcnt 0x0514; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v0, v1, v[2:3]515; GFX1250-NEXT: s_set_pc_i64 s[30:31]516 %sext0 = sext i32 %arg0 to i63517 %sext1 = sext i32 %arg1 to i63518 %mul = mul i63 %sext0, %sext1519 %mad = add i63 %mul, %arg2520 ret i63 %mad521}522 523define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {524; CI-LABEL: mad_i64_i32_sextops_i31_i63:525; CI: ; %bb.0:526; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)527; CI-NEXT: v_bfe_i32 v1, v1, 0, 31528; CI-NEXT: v_bfe_i32 v0, v0, 0, 31529; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]530; CI-NEXT: s_setpc_b64 s[30:31]531;532; SI-LABEL: mad_i64_i32_sextops_i31_i63:533; SI: ; %bb.0:534; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)535; SI-NEXT: v_bfe_i32 v0, v0, 0, 31536; SI-NEXT: v_bfe_i32 v1, v1, 0, 31537; SI-NEXT: v_mul_lo_u32 v4, v0, v1538; SI-NEXT: v_mul_hi_i32 v1, v0, v1539; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v2540; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc541; SI-NEXT: s_setpc_b64 s[30:31]542;543; GFX9-LABEL: mad_i64_i32_sextops_i31_i63:544; GFX9: ; %bb.0:545; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)546; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 31547; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 31548; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]549; GFX9-NEXT: s_setpc_b64 s[30:31]550;551; GFX1100-LABEL: mad_i64_i32_sextops_i31_i63:552; GFX1100: ; %bb.0:553; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)554; GFX1100-NEXT: v_bfe_i32 v4, v1, 0, 31555; GFX1100-NEXT: v_bfe_i32 v5, v0, 0, 31556; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)557; GFX1100-NEXT: v_mad_i64_i32 v[0:1], null, v5, v4, v[2:3]558; GFX1100-NEXT: s_setpc_b64 s[30:31]559;560; GFX1150-LABEL: mad_i64_i32_sextops_i31_i63:561; GFX1150: ; %bb.0:562; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)563; GFX1150-NEXT: v_bfe_i32 v1, v1, 0, 31564; GFX1150-NEXT: v_bfe_i32 v0, v0, 0, 31565; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)566; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, v[2:3]567; GFX1150-NEXT: s_setpc_b64 s[30:31]568;569; GFX12-LABEL: mad_i64_i32_sextops_i31_i63:570; GFX12: ; %bb.0:571; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0572; GFX12-NEXT: s_wait_expcnt 0x0573; GFX12-NEXT: s_wait_samplecnt 0x0574; GFX12-NEXT: s_wait_bvhcnt 0x0575; GFX12-NEXT: s_wait_kmcnt 0x0576; GFX12-NEXT: v_bfe_i32 v1, v1, 0, 31577; GFX12-NEXT: v_bfe_i32 v0, v0, 0, 31578; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)579; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, v[2:3]580; GFX12-NEXT: s_setpc_b64 s[30:31]581;582; GFX1250-LABEL: mad_i64_i32_sextops_i31_i63:583; GFX1250: ; %bb.0:584; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0585; GFX1250-NEXT: s_wait_kmcnt 0x0586; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 31587; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 31588; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)589; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v0, v1, v[2:3]590; GFX1250-NEXT: s_set_pc_i64 s[30:31]591 %sext0 = sext i31 %arg0 to i63592 %sext1 = sext i31 %arg1 to i63593 %mul = mul i63 %sext0, %sext1594 %mad = add i63 %mul, %arg2595 ret i63 %mad596}597 598define i64 @mad_i64_i32_extops_i32_i64(i32 %arg0, i32 %arg1, i64 %arg2) #0 {599; CI-LABEL: mad_i64_i32_extops_i32_i64:600; CI: ; %bb.0:601; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)602; CI-NEXT: v_ashrrev_i32_e32 v4, 31, v0603; CI-NEXT: v_mul_lo_u32 v4, v4, v1604; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v1, v[2:3]605; CI-NEXT: v_add_i32_e32 v1, vcc, v4, v1606; CI-NEXT: s_setpc_b64 s[30:31]607;608; SI-LABEL: mad_i64_i32_extops_i32_i64:609; SI: ; %bb.0:610; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)611; SI-NEXT: v_ashrrev_i32_e32 v4, 31, v0612; SI-NEXT: v_mul_hi_u32 v5, v0, v1613; SI-NEXT: v_mul_lo_u32 v4, v4, v1614; SI-NEXT: v_mul_lo_u32 v0, v0, v1615; SI-NEXT: v_add_i32_e32 v1, vcc, v5, v4616; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v2617; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc618; SI-NEXT: s_setpc_b64 s[30:31]619;620; GFX9-LABEL: mad_i64_i32_extops_i32_i64:621; GFX9: ; %bb.0:622; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)623; GFX9-NEXT: v_mov_b32_e32 v4, v1624; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v0625; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v4, v[2:3]626; GFX9-NEXT: v_mov_b32_e32 v2, v1627; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, v4, v[2:3]628; GFX9-NEXT: v_mov_b32_e32 v1, v2629; GFX9-NEXT: s_setpc_b64 s[30:31]630;631; GFX1100-LABEL: mad_i64_i32_extops_i32_i64:632; GFX1100: ; %bb.0:633; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)634; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0635; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)636; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v5, v4, v[2:3]637; GFX1100-NEXT: v_ashrrev_i32_e32 v5, 31, v5638; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, v5, v4, v[1:2]639; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)640; GFX1100-NEXT: v_mov_b32_e32 v1, v2641; GFX1100-NEXT: s_setpc_b64 s[30:31]642;643; GFX1150-LABEL: mad_i64_i32_extops_i32_i64:644; GFX1150: ; %bb.0:645; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)646; GFX1150-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0647; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)648; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v5, v4, v[2:3]649; GFX1150-NEXT: v_ashrrev_i32_e32 v2, 31, v5650; GFX1150-NEXT: v_mad_u64_u32 v[1:2], null, v2, v4, v[1:2]651; GFX1150-NEXT: s_setpc_b64 s[30:31]652;653; GFX12-LABEL: mad_i64_i32_extops_i32_i64:654; GFX12: ; %bb.0:655; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0656; GFX12-NEXT: s_wait_expcnt 0x0657; GFX12-NEXT: s_wait_samplecnt 0x0658; GFX12-NEXT: s_wait_bvhcnt 0x0659; GFX12-NEXT: s_wait_kmcnt 0x0660; GFX12-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0661; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)662; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v5, v4, v[2:3]663; GFX12-NEXT: v_ashrrev_i32_e32 v2, 31, v5664; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v2, v4, v[1:2]665; GFX12-NEXT: s_setpc_b64 s[30:31]666;667; GFX1250-LABEL: mad_i64_i32_extops_i32_i64:668; GFX1250: ; %bb.0:669; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0670; GFX1250-NEXT: s_wait_kmcnt 0x0671; GFX1250-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v0672; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)673; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v5, v4, v[2:3]674; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 31, v5675; GFX1250-NEXT: v_mad_u32 v1, v2, v4, v1676; GFX1250-NEXT: s_set_pc_i64 s[30:31]677 %ext0 = sext i32 %arg0 to i64678 %ext1 = zext i32 %arg1 to i64679 %mul = mul i64 %ext0, %ext1680 %mad = add i64 %mul, %arg2681 ret i64 %mad682}683 684define i64 @mad_u64_u32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {685; CI-LABEL: mad_u64_u32_bitops:686; CI: ; %bb.0:687; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)688; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[4:5]689; CI-NEXT: s_setpc_b64 s[30:31]690;691; SI-LABEL: mad_u64_u32_bitops:692; SI: ; %bb.0:693; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)694; SI-NEXT: v_mul_lo_u32 v1, v0, v2695; SI-NEXT: v_mul_hi_u32 v2, v0, v2696; SI-NEXT: v_add_i32_e32 v0, vcc, v1, v4697; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v5, vcc698; SI-NEXT: s_setpc_b64 s[30:31]699;700; GFX9-LABEL: mad_u64_u32_bitops:701; GFX9: ; %bb.0:702; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)703; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[4:5]704; GFX9-NEXT: s_setpc_b64 s[30:31]705;706; GFX1100-LABEL: mad_u64_u32_bitops:707; GFX1100: ; %bb.0:708; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)709; GFX1100-NEXT: v_mov_b32_e32 v3, v0710; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)711; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, v[4:5]712; GFX1100-NEXT: s_setpc_b64 s[30:31]713;714; GFX1150-LABEL: mad_u64_u32_bitops:715; GFX1150: ; %bb.0:716; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)717; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v0, v2, v[4:5]718; GFX1150-NEXT: s_setpc_b64 s[30:31]719;720; GFX12-LABEL: mad_u64_u32_bitops:721; GFX12: ; %bb.0:722; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0723; GFX12-NEXT: s_wait_expcnt 0x0724; GFX12-NEXT: s_wait_samplecnt 0x0725; GFX12-NEXT: s_wait_bvhcnt 0x0726; GFX12-NEXT: s_wait_kmcnt 0x0727; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v2, v[4:5]728; GFX12-NEXT: s_setpc_b64 s[30:31]729;730; GFX1250-LABEL: mad_u64_u32_bitops:731; GFX1250: ; %bb.0:732; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0733; GFX1250-NEXT: s_wait_kmcnt 0x0734; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, v2, v[4:5]735; GFX1250-NEXT: s_set_pc_i64 s[30:31]736 %trunc.lhs = and i64 %arg0, 4294967295737 %trunc.rhs = and i64 %arg1, 4294967295738 %mul = mul i64 %trunc.lhs, %trunc.rhs739 %add = add i64 %mul, %arg2740 ret i64 %add741}742 743define i64 @mad_u64_u32_bitops_lhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {744; CI-LABEL: mad_u64_u32_bitops_lhs_mask_small:745; CI: ; %bb.0:746; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)747; CI-NEXT: v_and_b32_e32 v3, 1, v1748; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[4:5]749; CI-NEXT: v_mul_lo_u32 v2, v3, v2750; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1751; CI-NEXT: s_setpc_b64 s[30:31]752;753; SI-LABEL: mad_u64_u32_bitops_lhs_mask_small:754; SI: ; %bb.0:755; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)756; SI-NEXT: v_and_b32_e32 v1, 1, v1757; SI-NEXT: v_mul_hi_u32 v3, v0, v2758; SI-NEXT: v_mul_lo_u32 v1, v1, v2759; SI-NEXT: v_mul_lo_u32 v0, v0, v2760; SI-NEXT: v_add_i32_e32 v1, vcc, v3, v1761; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v4762; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc763; SI-NEXT: s_setpc_b64 s[30:31]764;765; GFX9-LABEL: mad_u64_u32_bitops_lhs_mask_small:766; GFX9: ; %bb.0:767; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)768; GFX9-NEXT: v_and_b32_e32 v3, 1, v1769; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, v2, v[4:5]770; GFX9-NEXT: v_mov_b32_e32 v4, v1771; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v3, v2, v[4:5]772; GFX9-NEXT: v_mov_b32_e32 v1, v2773; GFX9-NEXT: s_setpc_b64 s[30:31]774;775; GFX1100-LABEL: mad_u64_u32_bitops_lhs_mask_small:776; GFX1100: ; %bb.0:777; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)778; GFX1100-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v6, v1779; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)780; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, v[4:5]781; GFX1100-NEXT: v_and_b32_e32 v5, 1, v6782; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)783; GFX1100-NEXT: v_mad_u64_u32 v[3:4], null, v5, v2, v[1:2]784; GFX1100-NEXT: v_mov_b32_e32 v1, v3785; GFX1100-NEXT: s_setpc_b64 s[30:31]786;787; GFX1150-LABEL: mad_u64_u32_bitops_lhs_mask_small:788; GFX1150: ; %bb.0:789; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)790; GFX1150-NEXT: v_mov_b32_e32 v3, v1791; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v0, v2, v[4:5]792; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)793; GFX1150-NEXT: v_and_b32_e32 v3, 1, v3794; GFX1150-NEXT: v_mad_u64_u32 v[1:2], null, v3, v2, v[1:2]795; GFX1150-NEXT: s_setpc_b64 s[30:31]796;797; GFX12-LABEL: mad_u64_u32_bitops_lhs_mask_small:798; GFX12: ; %bb.0:799; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0800; GFX12-NEXT: s_wait_expcnt 0x0801; GFX12-NEXT: s_wait_samplecnt 0x0802; GFX12-NEXT: s_wait_bvhcnt 0x0803; GFX12-NEXT: s_wait_kmcnt 0x0804; GFX12-NEXT: v_mov_b32_e32 v3, v1805; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v0, v2, v[4:5]806; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)807; GFX12-NEXT: v_and_b32_e32 v3, 1, v3808; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v3, v2, v[1:2]809; GFX12-NEXT: s_setpc_b64 s[30:31]810;811; GFX1250-LABEL: mad_u64_u32_bitops_lhs_mask_small:812; GFX1250: ; %bb.0:813; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0814; GFX1250-NEXT: s_wait_kmcnt 0x0815; GFX1250-NEXT: v_mov_b32_e32 v3, v1816; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v0, v2, v[4:5]817; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)818; GFX1250-NEXT: v_and_b32_e32 v3, 1, v3819; GFX1250-NEXT: v_mad_u32 v1, v3, v2, v1820; GFX1250-NEXT: s_set_pc_i64 s[30:31]821 %trunc.lhs = and i64 %arg0, 8589934591822 %trunc.rhs = and i64 %arg1, 4294967295823 %mul = mul i64 %trunc.lhs, %trunc.rhs824 %add = add i64 %mul, %arg2825 ret i64 %add826}827 828define i64 @mad_u64_u32_bitops_rhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {829; CI-LABEL: mad_u64_u32_bitops_rhs_mask_small:830; CI: ; %bb.0:831; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)832; CI-NEXT: v_mov_b32_e32 v6, v0833; CI-NEXT: v_and_b32_e32 v3, 1, v3834; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, v[4:5]835; CI-NEXT: v_mul_lo_u32 v2, v6, v3836; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1837; CI-NEXT: s_setpc_b64 s[30:31]838;839; SI-LABEL: mad_u64_u32_bitops_rhs_mask_small:840; SI: ; %bb.0:841; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)842; SI-NEXT: v_and_b32_e32 v1, 1, v3843; SI-NEXT: v_mul_hi_u32 v3, v0, v2844; SI-NEXT: v_mul_lo_u32 v1, v0, v1845; SI-NEXT: v_mul_lo_u32 v0, v0, v2846; SI-NEXT: v_add_i32_e32 v1, vcc, v3, v1847; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v4848; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc849; SI-NEXT: s_setpc_b64 s[30:31]850;851; GFX9-LABEL: mad_u64_u32_bitops_rhs_mask_small:852; GFX9: ; %bb.0:853; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)854; GFX9-NEXT: v_mov_b32_e32 v6, v0855; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v2, v[4:5]856; GFX9-NEXT: v_and_b32_e32 v3, 1, v3857; GFX9-NEXT: v_mov_b32_e32 v2, v1858; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v6, v3, v[2:3]859; GFX9-NEXT: v_mov_b32_e32 v1, v2860; GFX9-NEXT: s_setpc_b64 s[30:31]861;862; GFX1100-LABEL: mad_u64_u32_bitops_rhs_mask_small:863; GFX1100: ; %bb.0:864; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)865; GFX1100-NEXT: v_mov_b32_e32 v6, v0866; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)867; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v6, v2, v[4:5]868; GFX1100-NEXT: v_and_b32_e32 v4, 1, v3869; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, v6, v4, v[1:2]870; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)871; GFX1100-NEXT: v_mov_b32_e32 v1, v2872; GFX1100-NEXT: s_setpc_b64 s[30:31]873;874; GFX1150-LABEL: mad_u64_u32_bitops_rhs_mask_small:875; GFX1150: ; %bb.0:876; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)877; GFX1150-NEXT: v_mov_b32_e32 v6, v0878; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)879; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v6, v2, v[4:5]880; GFX1150-NEXT: v_and_b32_e32 v2, 1, v3881; GFX1150-NEXT: v_mad_u64_u32 v[1:2], null, v6, v2, v[1:2]882; GFX1150-NEXT: s_setpc_b64 s[30:31]883;884; GFX12-LABEL: mad_u64_u32_bitops_rhs_mask_small:885; GFX12: ; %bb.0:886; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0887; GFX12-NEXT: s_wait_expcnt 0x0888; GFX12-NEXT: s_wait_samplecnt 0x0889; GFX12-NEXT: s_wait_bvhcnt 0x0890; GFX12-NEXT: s_wait_kmcnt 0x0891; GFX12-NEXT: v_mov_b32_e32 v6, v0892; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)893; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v6, v2, v[4:5]894; GFX12-NEXT: v_and_b32_e32 v2, 1, v3895; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v6, v2, v[1:2]896; GFX12-NEXT: s_setpc_b64 s[30:31]897;898; GFX1250-LABEL: mad_u64_u32_bitops_rhs_mask_small:899; GFX1250: ; %bb.0:900; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0901; GFX1250-NEXT: s_wait_kmcnt 0x0902; GFX1250-NEXT: v_mov_b32_e32 v6, v0903; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)904; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v6, v2, v[4:5]905; GFX1250-NEXT: v_and_b32_e32 v2, 1, v3906; GFX1250-NEXT: v_mad_u32 v1, v6, v2, v1907; GFX1250-NEXT: s_set_pc_i64 s[30:31]908 %trunc.lhs = and i64 %arg0, 4294967295909 %trunc.rhs = and i64 %arg1, 8589934591910 %mul = mul i64 %trunc.lhs, %trunc.rhs911 %add = add i64 %mul, %arg2912 ret i64 %add913}914 915define i64 @mad_i64_i32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {916; CI-LABEL: mad_i64_i32_bitops:917; CI: ; %bb.0:918; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)919; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v2, v[4:5]920; CI-NEXT: s_setpc_b64 s[30:31]921;922; SI-LABEL: mad_i64_i32_bitops:923; SI: ; %bb.0:924; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)925; SI-NEXT: v_mul_lo_u32 v1, v0, v2926; SI-NEXT: v_mul_hi_i32 v2, v0, v2927; SI-NEXT: v_add_i32_e32 v0, vcc, v1, v4928; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v5, vcc929; SI-NEXT: s_setpc_b64 s[30:31]930;931; GFX9-LABEL: mad_i64_i32_bitops:932; GFX9: ; %bb.0:933; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)934; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v2, v[4:5]935; GFX9-NEXT: s_setpc_b64 s[30:31]936;937; GFX1100-LABEL: mad_i64_i32_bitops:938; GFX1100: ; %bb.0:939; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)940; GFX1100-NEXT: v_mov_b32_e32 v3, v0941; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)942; GFX1100-NEXT: v_mad_i64_i32 v[0:1], null, v3, v2, v[4:5]943; GFX1100-NEXT: s_setpc_b64 s[30:31]944;945; GFX1150-LABEL: mad_i64_i32_bitops:946; GFX1150: ; %bb.0:947; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)948; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v2, v[4:5]949; GFX1150-NEXT: s_setpc_b64 s[30:31]950;951; GFX12-LABEL: mad_i64_i32_bitops:952; GFX12: ; %bb.0:953; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0954; GFX12-NEXT: s_wait_expcnt 0x0955; GFX12-NEXT: s_wait_samplecnt 0x0956; GFX12-NEXT: s_wait_bvhcnt 0x0957; GFX12-NEXT: s_wait_kmcnt 0x0958; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v2, v[4:5]959; GFX12-NEXT: s_setpc_b64 s[30:31]960;961; GFX1250-LABEL: mad_i64_i32_bitops:962; GFX1250: ; %bb.0:963; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0964; GFX1250-NEXT: s_wait_kmcnt 0x0965; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v0, v2, v[4:5]966; GFX1250-NEXT: s_set_pc_i64 s[30:31]967 %shl.lhs = shl i64 %arg0, 32968 %trunc.lhs = ashr i64 %shl.lhs, 32969 %shl.rhs = shl i64 %arg1, 32970 %trunc.rhs = ashr i64 %shl.rhs, 32971 %mul = mul i64 %trunc.lhs, %trunc.rhs972 %add = add i64 %mul, %arg2973 ret i64 %add974}975 976; Example from bug report977define i64 @mad_i64_i32_unpack_i64ops(i64 %arg0) #0 {978; CI-LABEL: mad_i64_i32_unpack_i64ops:979; CI: ; %bb.0:980; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)981; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, v[0:1]982; CI-NEXT: s_setpc_b64 s[30:31]983;984; SI-LABEL: mad_i64_i32_unpack_i64ops:985; SI: ; %bb.0:986; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)987; SI-NEXT: v_mul_lo_u32 v2, v1, v0988; SI-NEXT: v_mul_hi_u32 v3, v1, v0989; SI-NEXT: v_add_i32_e32 v0, vcc, v2, v0990; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc991; SI-NEXT: s_setpc_b64 s[30:31]992;993; GFX9-LABEL: mad_i64_i32_unpack_i64ops:994; GFX9: ; %bb.0:995; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)996; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, v[0:1]997; GFX9-NEXT: s_setpc_b64 s[30:31]998;999; GFX1100-LABEL: mad_i64_i32_unpack_i64ops:1000; GFX1100: ; %bb.0:1001; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1002; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, v1, v0, v[0:1]1003; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)1004; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v31005; GFX1100-NEXT: s_setpc_b64 s[30:31]1006;1007; GFX1150-LABEL: mad_i64_i32_unpack_i64ops:1008; GFX1150: ; %bb.0:1009; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1010; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v1, v0, v[0:1]1011; GFX1150-NEXT: s_setpc_b64 s[30:31]1012;1013; GFX12-LABEL: mad_i64_i32_unpack_i64ops:1014; GFX12: ; %bb.0:1015; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01016; GFX12-NEXT: s_wait_expcnt 0x01017; GFX12-NEXT: s_wait_samplecnt 0x01018; GFX12-NEXT: s_wait_bvhcnt 0x01019; GFX12-NEXT: s_wait_kmcnt 0x01020; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v1, v0, v[0:1]1021; GFX12-NEXT: s_setpc_b64 s[30:31]1022;1023; GFX1250-LABEL: mad_i64_i32_unpack_i64ops:1024; GFX1250: ; %bb.0:1025; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01026; GFX1250-NEXT: s_wait_kmcnt 0x01027; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v1, v0, v[0:1]1028; GFX1250-NEXT: s_set_pc_i64 s[30:31]1029 %tmp4 = lshr i64 %arg0, 321030 %tmp5 = and i64 %arg0, 42949672951031 %mul = mul nuw i64 %tmp4, %tmp51032 %mad = add i64 %mul, %arg01033 ret i64 %mad1034}1035 1036define amdgpu_kernel void @mad_i64_i32_uniform(ptr addrspace(1) %out, i32 %arg0, i32 %arg1, i64 %arg2) #0 {1037; CI-LABEL: mad_i64_i32_uniform:1038; CI: ; %bb.0:1039; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91040; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd1041; CI-NEXT: s_mov_b32 s7, 0xf0001042; CI-NEXT: s_mov_b32 s6, -11043; CI-NEXT: s_waitcnt lgkmcnt(0)1044; CI-NEXT: v_mov_b32_e32 v2, s31045; CI-NEXT: v_mov_b32_e32 v0, s41046; CI-NEXT: v_mov_b32_e32 v1, s51047; CI-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s2, v2, v[0:1]1048; CI-NEXT: s_mov_b32 s4, s01049; CI-NEXT: s_mov_b32 s5, s11050; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01051; CI-NEXT: s_endpgm1052;1053; SI-LABEL: mad_i64_i32_uniform:1054; SI: ; %bb.0:1055; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91056; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1057; SI-NEXT: s_mov_b32 s7, 0xf0001058; SI-NEXT: s_mov_b32 s6, -11059; SI-NEXT: s_waitcnt lgkmcnt(0)1060; SI-NEXT: v_mov_b32_e32 v0, s31061; SI-NEXT: v_mul_hi_u32 v1, s2, v01062; SI-NEXT: s_mov_b32 s4, s01063; SI-NEXT: s_mul_i32 s0, s2, s31064; SI-NEXT: v_mov_b32_e32 v0, s01065; SI-NEXT: v_mov_b32_e32 v2, s91066; SI-NEXT: v_add_i32_e32 v0, vcc, s8, v01067; SI-NEXT: s_mov_b32 s5, s11068; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc1069; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01070; SI-NEXT: s_endpgm1071;1072; GFX9-LABEL: mad_i64_i32_uniform:1073; GFX9: ; %bb.0:1074; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x241075; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x341076; GFX9-NEXT: v_mov_b32_e32 v0, 01077; GFX9-NEXT: s_waitcnt lgkmcnt(0)1078; GFX9-NEXT: s_mul_hi_u32 s4, s2, s31079; GFX9-NEXT: s_mul_i32 s2, s2, s31080; GFX9-NEXT: s_add_u32 s2, s2, s61081; GFX9-NEXT: s_addc_u32 s3, s4, s71082; GFX9-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]1083; GFX9-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1]1084; GFX9-NEXT: s_endpgm1085;1086; GFX11-LABEL: mad_i64_i32_uniform:1087; GFX11: ; %bb.0:1088; GFX11-NEXT: s_clause 0x11089; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x241090; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x341091; GFX11-NEXT: s_waitcnt lgkmcnt(0)1092; GFX11-NEXT: s_mul_i32 s6, s2, s31093; GFX11-NEXT: s_mul_hi_u32 s3, s2, s31094; GFX11-NEXT: s_add_u32 s2, s6, s41095; GFX11-NEXT: s_addc_u32 s3, s3, s51096; GFX11-NEXT: v_mov_b32_e32 v0, s21097; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s31098; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]1099; GFX11-NEXT: s_endpgm1100;1101; GFX12-LABEL: mad_i64_i32_uniform:1102; GFX12: ; %bb.0:1103; GFX12-NEXT: s_clause 0x11104; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x241105; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x341106; GFX12-NEXT: s_mov_b32 s7, 01107; GFX12-NEXT: s_wait_kmcnt 0x01108; GFX12-NEXT: s_mov_b32 s6, s21109; GFX12-NEXT: s_mov_b32 s2, s31110; GFX12-NEXT: s_mov_b32 s3, s71111; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1112; GFX12-NEXT: s_mul_u64 s[2:3], s[6:7], s[2:3]1113; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]1114; GFX12-NEXT: v_mov_b32_e32 v2, 01115; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s31116; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]1117; GFX12-NEXT: s_endpgm1118;1119; GFX1250-LABEL: mad_i64_i32_uniform:1120; GFX1250: ; %bb.0:1121; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11122; GFX1250-NEXT: s_clause 0x11123; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x241124; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x341125; GFX1250-NEXT: s_wait_xcnt 0x01126; GFX1250-NEXT: s_mov_b32 s5, 01127; GFX1250-NEXT: v_mov_b32_e32 v2, 01128; GFX1250-NEXT: s_wait_kmcnt 0x01129; GFX1250-NEXT: s_mov_b32 s4, s21130; GFX1250-NEXT: s_mov_b32 s2, s31131; GFX1250-NEXT: s_mov_b32 s3, s51132; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1133; GFX1250-NEXT: s_mul_u64 s[2:3], s[4:5], s[2:3]1134; GFX1250-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[6:7]1135; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1136; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[2:3]1137; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]1138; GFX1250-NEXT: s_endpgm1139 %ext0 = zext i32 %arg0 to i641140 %ext1 = zext i32 %arg1 to i641141 %mul = mul i64 %ext0, %ext11142 %mad = add i64 %mul, %arg21143 store i64 %mad, ptr addrspace(1) %out1144 ret void1145}1146 1147define i64 @mad_i64_i32_twice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0 {1148; CI-LABEL: mad_i64_i32_twice:1149; CI: ; %bb.0:1150; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1151; CI-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]1152; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[4:5]1153; CI-NEXT: v_xor_b32_e32 v1, v3, v11154; CI-NEXT: v_xor_b32_e32 v0, v2, v01155; CI-NEXT: s_setpc_b64 s[30:31]1156;1157; SI-LABEL: mad_i64_i32_twice:1158; SI: ; %bb.0:1159; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1160; SI-NEXT: v_mul_lo_u32 v6, v0, v11161; SI-NEXT: v_mul_hi_i32 v0, v0, v11162; SI-NEXT: v_add_i32_e32 v2, vcc, v6, v21163; SI-NEXT: v_addc_u32_e32 v1, vcc, v0, v3, vcc1164; SI-NEXT: v_add_i32_e32 v3, vcc, v6, v41165; SI-NEXT: v_addc_u32_e32 v0, vcc, v0, v5, vcc1166; SI-NEXT: v_xor_b32_e32 v1, v1, v01167; SI-NEXT: v_xor_b32_e32 v0, v2, v31168; SI-NEXT: s_setpc_b64 s[30:31]1169;1170; GFX9-LABEL: mad_i64_i32_twice:1171; GFX9: ; %bb.0:1172; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1173; GFX9-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]1174; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[4:5]1175; GFX9-NEXT: v_xor_b32_e32 v1, v3, v11176; GFX9-NEXT: v_xor_b32_e32 v0, v2, v01177; GFX9-NEXT: s_setpc_b64 s[30:31]1178;1179; GFX1100-LABEL: mad_i64_i32_twice:1180; GFX1100: ; %bb.0:1181; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1182; GFX1100-NEXT: v_mad_i64_i32 v[6:7], null, v0, v1, v[2:3]1183; GFX1100-NEXT: v_mad_i64_i32 v[2:3], null, v0, v1, v[4:5]1184; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1185; GFX1100-NEXT: v_xor_b32_e32 v0, v6, v21186; GFX1100-NEXT: v_xor_b32_e32 v1, v7, v31187; GFX1100-NEXT: s_setpc_b64 s[30:31]1188;1189; GFX1150-LABEL: mad_i64_i32_twice:1190; GFX1150: ; %bb.0:1191; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1192; GFX1150-NEXT: v_mad_i64_i32 v[2:3], null, v0, v1, v[2:3]1193; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, v[4:5]1194; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1195; GFX1150-NEXT: v_xor_b32_e32 v0, v2, v01196; GFX1150-NEXT: v_xor_b32_e32 v1, v3, v11197; GFX1150-NEXT: s_setpc_b64 s[30:31]1198;1199; GFX12-LABEL: mad_i64_i32_twice:1200; GFX12: ; %bb.0:1201; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01202; GFX12-NEXT: s_wait_expcnt 0x01203; GFX12-NEXT: s_wait_samplecnt 0x01204; GFX12-NEXT: s_wait_bvhcnt 0x01205; GFX12-NEXT: s_wait_kmcnt 0x01206; GFX12-NEXT: v_mad_co_i64_i32 v[2:3], null, v0, v1, v[2:3]1207; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, v[4:5]1208; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1209; GFX12-NEXT: v_xor_b32_e32 v0, v2, v01210; GFX12-NEXT: v_xor_b32_e32 v1, v3, v11211; GFX12-NEXT: s_setpc_b64 s[30:31]1212;1213; GFX1250-LABEL: mad_i64_i32_twice:1214; GFX1250: ; %bb.0:1215; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01216; GFX1250-NEXT: s_wait_kmcnt 0x01217; GFX1250-NEXT: v_mad_nc_i64_i32 v[2:3], v0, v1, v[2:3]1218; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], v0, v1, v[4:5]1219; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1220; GFX1250-NEXT: v_xor_b32_e32 v0, v2, v01221; GFX1250-NEXT: v_xor_b32_e32 v1, v3, v11222; GFX1250-NEXT: s_set_pc_i64 s[30:31]1223 %sext0 = sext i32 %arg0 to i641224 %sext1 = sext i32 %arg1 to i641225 %mul = mul i64 %sext0, %sext11226 %mad1 = add i64 %mul, %arg21227 %mad2 = add i64 %mul, %arg31228 %out = xor i64 %mad1, %mad21229 ret i64 %out1230}1231 1232define i64 @mad_i64_i32_thrice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3, i64 %arg4) #0 {1233; CI-LABEL: mad_i64_i32_thrice:1234; CI: ; %bb.0:1235; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1236; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, 01237; CI-NEXT: v_add_i32_e32 v2, vcc, v0, v21238; CI-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc1239; CI-NEXT: v_add_i32_e32 v4, vcc, v0, v41240; CI-NEXT: v_addc_u32_e32 v5, vcc, v1, v5, vcc1241; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v61242; CI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc1243; CI-NEXT: v_xor_b32_e32 v3, v3, v51244; CI-NEXT: v_xor_b32_e32 v2, v2, v41245; CI-NEXT: v_xor_b32_e32 v1, v3, v11246; CI-NEXT: v_xor_b32_e32 v0, v2, v01247; CI-NEXT: s_setpc_b64 s[30:31]1248;1249; SI-LABEL: mad_i64_i32_thrice:1250; SI: ; %bb.0:1251; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1252; SI-NEXT: v_mul_lo_u32 v8, v0, v11253; SI-NEXT: v_mul_hi_i32 v0, v0, v11254; SI-NEXT: v_add_i32_e32 v1, vcc, v8, v21255; SI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc1256; SI-NEXT: v_add_i32_e32 v3, vcc, v8, v41257; SI-NEXT: v_addc_u32_e32 v4, vcc, v0, v5, vcc1258; SI-NEXT: v_add_i32_e32 v5, vcc, v8, v61259; SI-NEXT: v_addc_u32_e32 v0, vcc, v0, v7, vcc1260; SI-NEXT: v_xor_b32_e32 v2, v2, v41261; SI-NEXT: v_xor_b32_e32 v3, v1, v31262; SI-NEXT: v_xor_b32_e32 v1, v2, v01263; SI-NEXT: v_xor_b32_e32 v0, v3, v51264; SI-NEXT: s_setpc_b64 s[30:31]1265;1266; GFX9-LABEL: mad_i64_i32_thrice:1267; GFX9: ; %bb.0:1268; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1269; GFX9-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]1270; GFX9-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, v[4:5]1271; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[6:7]1272; GFX9-NEXT: v_xor_b32_e32 v3, v3, v51273; GFX9-NEXT: v_xor_b32_e32 v2, v2, v41274; GFX9-NEXT: v_xor_b32_e32 v1, v3, v11275; GFX9-NEXT: v_xor_b32_e32 v0, v2, v01276; GFX9-NEXT: s_setpc_b64 s[30:31]1277;1278; GFX1100-LABEL: mad_i64_i32_thrice:1279; GFX1100: ; %bb.0:1280; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1281; GFX1100-NEXT: v_mad_i64_i32 v[8:9], null, v0, v1, 01282; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1283; GFX1100-NEXT: v_add_co_u32 v0, vcc_lo, v8, v21284; GFX1100-NEXT: v_add_co_ci_u32_e64 v1, null, v9, v3, vcc_lo1285; GFX1100-NEXT: v_add_co_u32 v2, vcc_lo, v8, v41286; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1287; GFX1100-NEXT: v_add_co_ci_u32_e64 v3, null, v9, v5, vcc_lo1288; GFX1100-NEXT: v_add_co_u32 v4, vcc_lo, v8, v61289; GFX1100-NEXT: v_add_co_ci_u32_e64 v5, null, v9, v7, vcc_lo1290; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1291; GFX1100-NEXT: v_xor_b32_e32 v0, v0, v21292; GFX1100-NEXT: v_xor_b32_e32 v1, v1, v31293; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1294; GFX1100-NEXT: v_xor_b32_e32 v0, v0, v41295; GFX1100-NEXT: v_xor_b32_e32 v1, v1, v51296; GFX1100-NEXT: s_setpc_b64 s[30:31]1297;1298; GFX1150-LABEL: mad_i64_i32_thrice:1299; GFX1150: ; %bb.0:1300; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1301; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, 01302; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1303; GFX1150-NEXT: v_add_co_u32 v2, vcc_lo, v0, v21304; GFX1150-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo1305; GFX1150-NEXT: v_add_co_u32 v4, vcc_lo, v0, v41306; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1307; GFX1150-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v5, vcc_lo1308; GFX1150-NEXT: v_add_co_u32 v0, vcc_lo, v0, v61309; GFX1150-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v7, vcc_lo1310; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1311; GFX1150-NEXT: v_xor_b32_e32 v2, v2, v41312; GFX1150-NEXT: v_xor_b32_e32 v3, v3, v51313; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1314; GFX1150-NEXT: v_xor_b32_e32 v0, v2, v01315; GFX1150-NEXT: v_xor_b32_e32 v1, v3, v11316; GFX1150-NEXT: s_setpc_b64 s[30:31]1317;1318; GFX12-LABEL: mad_i64_i32_thrice:1319; GFX12: ; %bb.0:1320; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01321; GFX12-NEXT: s_wait_expcnt 0x01322; GFX12-NEXT: s_wait_samplecnt 0x01323; GFX12-NEXT: s_wait_bvhcnt 0x01324; GFX12-NEXT: s_wait_kmcnt 0x01325; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, 01326; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1327; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v21328; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)1329; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo1330; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, v0, v41331; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)1332; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, v1, v5, vcc_lo1333; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v61334; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)1335; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v7, vcc_lo1336; GFX12-NEXT: v_xor_b32_e32 v2, v2, v41337; GFX12-NEXT: v_xor_b32_e32 v3, v3, v51338; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1339; GFX12-NEXT: v_xor_b32_e32 v0, v2, v01340; GFX12-NEXT: v_xor_b32_e32 v1, v3, v11341; GFX12-NEXT: s_setpc_b64 s[30:31]1342;1343; GFX1250-LABEL: mad_i64_i32_thrice:1344; GFX1250: ; %bb.0:1345; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01346; GFX1250-NEXT: s_wait_kmcnt 0x01347; GFX1250-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_ashrrev_i32 v1, 31, v01348; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1349; GFX1250-NEXT: v_ashrrev_i32_e32 v9, 31, v81350; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[0:1], v[8:9]1351; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)1352; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], v[0:1], v[2:3]1353; GFX1250-NEXT: v_add_nc_u64_e32 v[4:5], v[0:1], v[4:5]1354; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[6:7]1355; GFX1250-NEXT: v_xor_b32_e32 v2, v2, v41356; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1357; GFX1250-NEXT: v_xor_b32_e32 v3, v3, v51358; GFX1250-NEXT: v_xor_b32_e32 v0, v2, v01359; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)1360; GFX1250-NEXT: v_xor_b32_e32 v1, v3, v11361; GFX1250-NEXT: s_set_pc_i64 s[30:31]1362 %sext0 = sext i32 %arg0 to i641363 %sext1 = sext i32 %arg1 to i641364 %mul = mul i64 %sext0, %sext11365 %mad1 = add i64 %mul, %arg21366 %mad2 = add i64 %mul, %arg31367 %mad3 = add i64 %mul, %arg41368 %out.p = xor i64 %mad1, %mad21369 %out = xor i64 %out.p, %mad31370 ret i64 %out1371}1372 1373define i64 @mad_i64_i32_secondary_use(i32 %arg0, i32 %arg1, i64 %arg2) #0 {1374; CI-LABEL: mad_i64_i32_secondary_use:1375; CI: ; %bb.0:1376; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1377; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, 01378; CI-NEXT: v_add_i32_e32 v2, vcc, v0, v21379; CI-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc1380; CI-NEXT: v_xor_b32_e32 v1, v3, v11381; CI-NEXT: v_xor_b32_e32 v0, v2, v01382; CI-NEXT: s_setpc_b64 s[30:31]1383;1384; SI-LABEL: mad_i64_i32_secondary_use:1385; SI: ; %bb.0:1386; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1387; SI-NEXT: v_mul_lo_u32 v4, v0, v11388; SI-NEXT: v_mul_hi_i32 v0, v0, v11389; SI-NEXT: v_add_i32_e32 v2, vcc, v4, v21390; SI-NEXT: v_addc_u32_e32 v1, vcc, v0, v3, vcc1391; SI-NEXT: v_xor_b32_e32 v1, v1, v01392; SI-NEXT: v_xor_b32_e32 v0, v2, v41393; SI-NEXT: s_setpc_b64 s[30:31]1394;1395; GFX9-LABEL: mad_i64_i32_secondary_use:1396; GFX9: ; %bb.0:1397; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1398; GFX9-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, 01399; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]1400; GFX9-NEXT: v_xor_b32_e32 v1, v1, v51401; GFX9-NEXT: v_xor_b32_e32 v0, v0, v41402; GFX9-NEXT: s_setpc_b64 s[30:31]1403;1404; GFX1100-LABEL: mad_i64_i32_secondary_use:1405; GFX1100: ; %bb.0:1406; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1407; GFX1100-NEXT: v_mad_i64_i32 v[4:5], null, v0, v1, 01408; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1409; GFX1100-NEXT: v_add_co_u32 v0, vcc_lo, v4, v21410; GFX1100-NEXT: v_add_co_ci_u32_e64 v1, null, v5, v3, vcc_lo1411; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1412; GFX1100-NEXT: v_xor_b32_e32 v0, v0, v41413; GFX1100-NEXT: v_xor_b32_e32 v1, v1, v51414; GFX1100-NEXT: s_setpc_b64 s[30:31]1415;1416; GFX1150-LABEL: mad_i64_i32_secondary_use:1417; GFX1150: ; %bb.0:1418; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1419; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, v0, v1, 01420; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1421; GFX1150-NEXT: v_add_co_u32 v2, vcc_lo, v0, v21422; GFX1150-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo1423; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1424; GFX1150-NEXT: v_xor_b32_e32 v0, v2, v01425; GFX1150-NEXT: v_xor_b32_e32 v1, v3, v11426; GFX1150-NEXT: s_setpc_b64 s[30:31]1427;1428; GFX12-LABEL: mad_i64_i32_secondary_use:1429; GFX12: ; %bb.0:1430; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01431; GFX12-NEXT: s_wait_expcnt 0x01432; GFX12-NEXT: s_wait_samplecnt 0x01433; GFX12-NEXT: s_wait_bvhcnt 0x01434; GFX12-NEXT: s_wait_kmcnt 0x01435; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, v0, v1, 01436; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1437; GFX12-NEXT: v_add_co_u32 v2, vcc_lo, v0, v21438; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)1439; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v3, vcc_lo1440; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1441; GFX12-NEXT: v_xor_b32_e32 v0, v2, v01442; GFX12-NEXT: v_xor_b32_e32 v1, v3, v11443; GFX12-NEXT: s_setpc_b64 s[30:31]1444;1445; GFX1250-LABEL: mad_i64_i32_secondary_use:1446; GFX1250: ; %bb.0:1447; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01448; GFX1250-NEXT: s_wait_kmcnt 0x01449; GFX1250-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_ashrrev_i32 v1, 31, v01450; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1451; GFX1250-NEXT: v_ashrrev_i32_e32 v5, 31, v41452; GFX1250-NEXT: v_mul_u64_e32 v[0:1], v[0:1], v[4:5]1453; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1454; GFX1250-NEXT: v_add_nc_u64_e32 v[2:3], v[0:1], v[2:3]1455; GFX1250-NEXT: v_xor_b32_e32 v0, v2, v01456; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)1457; GFX1250-NEXT: v_xor_b32_e32 v1, v3, v11458; GFX1250-NEXT: s_set_pc_i64 s[30:31]1459 %sext0 = sext i32 %arg0 to i641460 %sext1 = sext i32 %arg1 to i641461 %mul = mul i64 %sext0, %sext11462 %mad = add i64 %mul, %arg21463 %out = xor i64 %mad, %mul1464 ret i64 %out1465}1466 1467define i48 @mad_i48_i48(i48 %arg0, i48 %arg1, i48 %arg2) #0 {1468; CI-LABEL: mad_i48_i48:1469; CI: ; %bb.0:1470; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1471; CI-NEXT: v_mov_b32_e32 v6, v11472; CI-NEXT: v_mov_b32_e32 v7, v01473; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v2, v[4:5]1474; CI-NEXT: v_mul_lo_u32 v2, v6, v21475; CI-NEXT: v_mul_lo_u32 v3, v7, v31476; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v11477; CI-NEXT: v_add_i32_e32 v1, vcc, v3, v11478; CI-NEXT: s_setpc_b64 s[30:31]1479;1480; SI-LABEL: mad_i48_i48:1481; SI: ; %bb.0:1482; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1483; SI-NEXT: v_mul_lo_u32 v3, v0, v31484; SI-NEXT: v_mul_hi_u32 v6, v0, v21485; SI-NEXT: v_mul_lo_u32 v1, v1, v21486; SI-NEXT: v_mul_lo_u32 v0, v0, v21487; SI-NEXT: v_add_i32_e32 v3, vcc, v6, v31488; SI-NEXT: v_add_i32_e32 v1, vcc, v3, v11489; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v41490; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc1491; SI-NEXT: s_setpc_b64 s[30:31]1492;1493; GFX9-LABEL: mad_i48_i48:1494; GFX9: ; %bb.0:1495; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1496; GFX9-NEXT: v_mov_b32_e32 v6, v11497; GFX9-NEXT: v_mov_b32_e32 v7, v01498; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v2, v[4:5]1499; GFX9-NEXT: v_mul_lo_u32 v3, v7, v31500; GFX9-NEXT: v_mul_lo_u32 v2, v6, v21501; GFX9-NEXT: v_add3_u32 v1, v2, v1, v31502; GFX9-NEXT: s_setpc_b64 s[30:31]1503;1504; GFX11-LABEL: mad_i48_i48:1505; GFX11: ; %bb.0:1506; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1507; GFX11-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v01508; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)1509; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v7, v2, v[4:5]1510; GFX11-NEXT: v_mul_lo_u32 v3, v7, v31511; GFX11-NEXT: v_mul_lo_u32 v2, v6, v21512; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1513; GFX11-NEXT: v_add3_u32 v1, v2, v1, v31514; GFX11-NEXT: s_setpc_b64 s[30:31]1515;1516; GFX12-LABEL: mad_i48_i48:1517; GFX12: ; %bb.0:1518; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01519; GFX12-NEXT: s_wait_expcnt 0x01520; GFX12-NEXT: s_wait_samplecnt 0x01521; GFX12-NEXT: s_wait_bvhcnt 0x01522; GFX12-NEXT: s_wait_kmcnt 0x01523; GFX12-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v01524; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)1525; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v7, v2, v[4:5]1526; GFX12-NEXT: v_mul_lo_u32 v3, v7, v31527; GFX12-NEXT: v_mul_lo_u32 v2, v6, v21528; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1529; GFX12-NEXT: v_add3_u32 v1, v2, v1, v31530; GFX12-NEXT: s_setpc_b64 s[30:31]1531;1532; GFX1250-LABEL: mad_i48_i48:1533; GFX1250: ; %bb.0:1534; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01535; GFX1250-NEXT: s_wait_kmcnt 0x01536; GFX1250-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v11537; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1538; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], v6, v2, v[4:5]1539; GFX1250-NEXT: v_mad_u32 v1, v7, v2, v11540; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1541; GFX1250-NEXT: v_mad_u32 v1, v6, v3, v11542; GFX1250-NEXT: s_set_pc_i64 s[30:31]1543 %m = mul i48 %arg0, %arg11544 %a = add i48 %m, %arg21545 ret i48 %a1546}1547 1548define i64 @lshr_mad_i64_1(i64 %arg0, i64 %arg1) #0 {1549; CI-LABEL: lshr_mad_i64_1:1550; CI: ; %bb.0:1551; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1552; CI-NEXT: v_mov_b32_e32 v2, v11553; CI-NEXT: v_mov_b32_e32 v1, 01554; CI-NEXT: s_movk_i32 s4, 0xfc191555; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1556; CI-NEXT: s_setpc_b64 s[30:31]1557;1558; SI-LABEL: lshr_mad_i64_1:1559; SI: ; %bb.0:1560; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1561; SI-NEXT: s_movk_i32 s4, 0xfc191562; SI-NEXT: v_mul_hi_u32 v2, v1, s41563; SI-NEXT: v_mul_lo_u32 v3, v1, s41564; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v11565; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v01566; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc1567; SI-NEXT: s_setpc_b64 s[30:31]1568;1569; GFX9-LABEL: lshr_mad_i64_1:1570; GFX9: ; %bb.0:1571; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1572; GFX9-NEXT: v_mov_b32_e32 v2, v11573; GFX9-NEXT: v_mov_b32_e32 v1, 01574; GFX9-NEXT: s_movk_i32 s4, 0xfc191575; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1576; GFX9-NEXT: s_setpc_b64 s[30:31]1577;1578; GFX1100-LABEL: lshr_mad_i64_1:1579; GFX1100: ; %bb.0:1580; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1581; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, 01582; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1583; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, 0xfffffc19, v4, v[0:1]1584; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v31585; GFX1100-NEXT: s_setpc_b64 s[30:31]1586;1587; GFX1150-LABEL: lshr_mad_i64_1:1588; GFX1150: ; %bb.0:1589; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1590; GFX1150-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01591; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)1592; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, 0xfffffc19, v2, v[0:1]1593; GFX1150-NEXT: s_setpc_b64 s[30:31]1594;1595; GFX12-LABEL: lshr_mad_i64_1:1596; GFX12: ; %bb.0:1597; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01598; GFX12-NEXT: s_wait_expcnt 0x01599; GFX12-NEXT: s_wait_samplecnt 0x01600; GFX12-NEXT: s_wait_bvhcnt 0x01601; GFX12-NEXT: s_wait_kmcnt 0x01602; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01603; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1604; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, 0xfffffc19, v2, v[0:1]1605; GFX12-NEXT: s_setpc_b64 s[30:31]1606;1607; GFX1250-LABEL: lshr_mad_i64_1:1608; GFX1250: ; %bb.0:1609; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01610; GFX1250-NEXT: s_wait_kmcnt 0x01611; GFX1250-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01612; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1613; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], 0xfffffc19, v2, v[0:1]1614; GFX1250-NEXT: s_set_pc_i64 s[30:31]1615 %lsh = lshr i64 %arg0, 321616 %mul = mul i64 %lsh, s0xfffffffffffffc191617 %mad = add i64 %mul, %arg01618 1619 ret i64 %mad1620}1621 1622define i64 @lshr_mad_i64_2(i64 %arg0) #0 {1623; CI-LABEL: lshr_mad_i64_2:1624; CI: ; %bb.0:1625; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1626; CI-NEXT: v_mov_b32_e32 v2, v11627; CI-NEXT: v_mov_b32_e32 v1, 01628; CI-NEXT: s_movk_i32 s4, 0xd11629; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1630; CI-NEXT: s_setpc_b64 s[30:31]1631;1632; SI-LABEL: lshr_mad_i64_2:1633; SI: ; %bb.0:1634; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1635; SI-NEXT: s_movk_i32 s4, 0xd11636; SI-NEXT: v_mul_hi_u32 v2, v1, s41637; SI-NEXT: v_mul_lo_u32 v3, v1, s41638; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v11639; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v01640; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc1641; SI-NEXT: s_setpc_b64 s[30:31]1642;1643; GFX9-LABEL: lshr_mad_i64_2:1644; GFX9: ; %bb.0:1645; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1646; GFX9-NEXT: v_mov_b32_e32 v2, v11647; GFX9-NEXT: v_mov_b32_e32 v1, 01648; GFX9-NEXT: s_movk_i32 s4, 0xd11649; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1650; GFX9-NEXT: s_setpc_b64 s[30:31]1651;1652; GFX1100-LABEL: lshr_mad_i64_2:1653; GFX1100: ; %bb.0:1654; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1655; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, 01656; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1657; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, 0xd1, v4, v[0:1]1658; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v31659; GFX1100-NEXT: s_setpc_b64 s[30:31]1660;1661; GFX1150-LABEL: lshr_mad_i64_2:1662; GFX1150: ; %bb.0:1663; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1664; GFX1150-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01665; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)1666; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, 0xd1, v2, v[0:1]1667; GFX1150-NEXT: s_setpc_b64 s[30:31]1668;1669; GFX12-LABEL: lshr_mad_i64_2:1670; GFX12: ; %bb.0:1671; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01672; GFX12-NEXT: s_wait_expcnt 0x01673; GFX12-NEXT: s_wait_samplecnt 0x01674; GFX12-NEXT: s_wait_bvhcnt 0x01675; GFX12-NEXT: s_wait_kmcnt 0x01676; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01677; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1678; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, 0xd1, v2, v[0:1]1679; GFX12-NEXT: s_setpc_b64 s[30:31]1680;1681; GFX1250-LABEL: lshr_mad_i64_2:1682; GFX1250: ; %bb.0:1683; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01684; GFX1250-NEXT: s_wait_kmcnt 0x01685; GFX1250-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01686; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1687; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], 0xd1, v2, v[0:1]1688; GFX1250-NEXT: s_set_pc_i64 s[30:31]1689 %lsh = lshr i64 %arg0, 321690 %mul = mul i64 %lsh, s0xffffffff000000d11691 %mad = add i64 %mul, %arg01692 1693 ret i64 %mad1694}1695 1696define i64 @lshr_mad_i64_3(i64 %arg0) #0 {1697; CI-LABEL: lshr_mad_i64_3:1698; CI: ; %bb.0:1699; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1700; CI-NEXT: v_mov_b32_e32 v2, v11701; CI-NEXT: v_mov_b32_e32 v1, 01702; CI-NEXT: s_movk_i32 s4, 0xfc881703; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1704; CI-NEXT: s_setpc_b64 s[30:31]1705;1706; SI-LABEL: lshr_mad_i64_3:1707; SI: ; %bb.0:1708; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1709; SI-NEXT: s_movk_i32 s4, 0xfc881710; SI-NEXT: v_mul_hi_u32 v2, v1, s41711; SI-NEXT: v_mul_lo_u32 v3, v1, s41712; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v11713; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v01714; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc1715; SI-NEXT: s_setpc_b64 s[30:31]1716;1717; GFX9-LABEL: lshr_mad_i64_3:1718; GFX9: ; %bb.0:1719; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1720; GFX9-NEXT: v_mov_b32_e32 v2, v11721; GFX9-NEXT: v_mov_b32_e32 v1, 01722; GFX9-NEXT: s_movk_i32 s4, 0xfc881723; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1724; GFX9-NEXT: s_setpc_b64 s[30:31]1725;1726; GFX1100-LABEL: lshr_mad_i64_3:1727; GFX1100: ; %bb.0:1728; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1729; GFX1100-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v1, 01730; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1731; GFX1100-NEXT: v_mad_u64_u32 v[2:3], null, 0xfffffc88, v4, v[0:1]1732; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v31733; GFX1100-NEXT: s_setpc_b64 s[30:31]1734;1735; GFX1150-LABEL: lshr_mad_i64_3:1736; GFX1150: ; %bb.0:1737; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1738; GFX1150-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01739; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)1740; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, 0xfffffc88, v2, v[0:1]1741; GFX1150-NEXT: s_setpc_b64 s[30:31]1742;1743; GFX12-LABEL: lshr_mad_i64_3:1744; GFX12: ; %bb.0:1745; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01746; GFX12-NEXT: s_wait_expcnt 0x01747; GFX12-NEXT: s_wait_samplecnt 0x01748; GFX12-NEXT: s_wait_bvhcnt 0x01749; GFX12-NEXT: s_wait_kmcnt 0x01750; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01751; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1752; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, 0xfffffc88, v2, v[0:1]1753; GFX12-NEXT: s_setpc_b64 s[30:31]1754;1755; GFX1250-LABEL: lshr_mad_i64_3:1756; GFX1250: ; %bb.0:1757; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01758; GFX1250-NEXT: s_wait_kmcnt 0x01759; GFX1250-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 01760; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1761; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], 0xfffffc88, v2, v[0:1]1762; GFX1250-NEXT: s_set_pc_i64 s[30:31]1763 %lsh = lshr i64 %arg0, 321764 %mul = mul i64 s0xfffffffffffffc88, %lsh1765 %mad = add i64 %mul, %arg01766 1767 ret i64 %mad1768}1769 1770define i64 @lshr_mad_i64_4(i32 %arg0, i64 %arg1) #0 {1771; CI-LABEL: lshr_mad_i64_4:1772; CI: ; %bb.0:1773; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1774; CI-NEXT: v_mul_lo_u32 v2, v2, v01775; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 01776; CI-NEXT: s_movk_i32 s4, 0xfc881777; CI-NEXT: v_add_i32_e32 v2, vcc, v1, v21778; CI-NEXT: v_mov_b32_e32 v1, 01779; CI-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, s4, v[0:1]1780; CI-NEXT: s_setpc_b64 s[30:31]1781;1782; SI-LABEL: lshr_mad_i64_4:1783; SI: ; %bb.0:1784; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1785; SI-NEXT: v_mul_lo_u32 v2, v2, v01786; SI-NEXT: v_mul_hi_u32 v3, v1, v01787; SI-NEXT: s_movk_i32 s4, 0xfc881788; SI-NEXT: v_mul_lo_u32 v0, v1, v01789; SI-NEXT: v_add_i32_e32 v2, vcc, v3, v21790; SI-NEXT: v_mul_hi_u32 v3, v2, s41791; SI-NEXT: v_mul_lo_u32 v1, v2, s41792; SI-NEXT: v_sub_i32_e32 v3, vcc, v3, v21793; SI-NEXT: v_add_i32_e32 v0, vcc, v1, v01794; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc1795; SI-NEXT: s_setpc_b64 s[30:31]1796;1797; GFX9-LABEL: lshr_mad_i64_4:1798; GFX9: ; %bb.0:1799; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1800; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v0, 01801; GFX9-NEXT: v_mov_b32_e32 v6, v51802; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, v[6:7]1803; GFX9-NEXT: v_mov_b32_e32 v5, 01804; GFX9-NEXT: s_movk_i32 s4, 0xfc881805; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v0, s4, v[4:5]1806; GFX9-NEXT: s_setpc_b64 s[30:31]1807;1808; GFX1100-LABEL: lshr_mad_i64_4:1809; GFX1100: ; %bb.0:1810; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1811; GFX1100-NEXT: v_mad_u64_u32 v[3:4], null, v1, v0, 01812; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1813; GFX1100-NEXT: v_mad_u64_u32 v[5:6], null, v2, v0, v[4:5]1814; GFX1100-NEXT: v_mov_b32_e32 v4, 01815; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, 0xfffffc88, v5, v[3:4]1816; GFX1100-NEXT: s_setpc_b64 s[30:31]1817;1818; GFX1150-LABEL: lshr_mad_i64_4:1819; GFX1150: ; %bb.0:1820; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1821; GFX1150-NEXT: v_mad_u64_u32 v[3:4], null, v1, v0, 01822; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1823; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v2, v0, v[4:5]1824; GFX1150-NEXT: v_mov_b32_e32 v4, 01825; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, 0xfffffc88, v0, v[3:4]1826; GFX1150-NEXT: s_setpc_b64 s[30:31]1827;1828; GFX12-LABEL: lshr_mad_i64_4:1829; GFX12: ; %bb.0:1830; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01831; GFX12-NEXT: s_wait_expcnt 0x01832; GFX12-NEXT: s_wait_samplecnt 0x01833; GFX12-NEXT: s_wait_bvhcnt 0x01834; GFX12-NEXT: s_wait_kmcnt 0x01835; GFX12-NEXT: v_mad_co_u64_u32 v[3:4], null, v1, v0, 01836; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)1837; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v2, v0, v[4:5]1838; GFX12-NEXT: v_mov_b32_e32 v4, 01839; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, 0xfffffc88, v0, v[3:4]1840; GFX12-NEXT: s_setpc_b64 s[30:31]1841;1842; GFX1250-LABEL: lshr_mad_i64_4:1843; GFX1250: ; %bb.0:1844; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01845; GFX1250-NEXT: s_wait_kmcnt 0x01846; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v11847; GFX1250-NEXT: v_mov_b32_e32 v1, 01848; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1849; GFX1250-NEXT: v_mul_u64_e32 v[2:3], v[2:3], v[0:1]1850; GFX1250-NEXT: v_mov_b32_e32 v0, v21851; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1852; GFX1250-NEXT: v_mad_nc_u64_u32 v[0:1], 0xfffffc88, v3, v[0:1]1853; GFX1250-NEXT: s_set_pc_i64 s[30:31]1854 %ext = zext i32 %arg0 to i641855 %mul1 = mul i64 %arg1, %ext1856 %lsh = lshr i64 %mul1, 321857 %mul2 = mul i64 %lsh, s0xfffffffffffffc881858 %mad = add i64 %mul2, %mul11859 ret i64 %mad1860}1861 1862define i64 @lshr_mad_i64_negative_1(i64 %arg0) #0 {1863; CI-LABEL: lshr_mad_i64_negative_1:1864; CI: ; %bb.0:1865; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1866; CI-NEXT: v_lshrrev_b32_e32 v2, 4, v11867; CI-NEXT: s_movk_i32 s4, 0xfc191868; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v2, s4, v[0:1]1869; CI-NEXT: s_setpc_b64 s[30:31]1870;1871; SI-LABEL: lshr_mad_i64_negative_1:1872; SI: ; %bb.0:1873; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1874; SI-NEXT: v_lshrrev_b32_e32 v2, 4, v11875; SI-NEXT: s_movk_i32 s4, 0xfc191876; SI-NEXT: v_mul_lo_u32 v3, v2, s41877; SI-NEXT: v_mul_hi_i32 v2, v2, s41878; SI-NEXT: v_add_i32_e32 v0, vcc, v3, v01879; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc1880; SI-NEXT: s_setpc_b64 s[30:31]1881;1882; GFX9-LABEL: lshr_mad_i64_negative_1:1883; GFX9: ; %bb.0:1884; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1885; GFX9-NEXT: v_lshrrev_b32_e32 v2, 4, v11886; GFX9-NEXT: s_movk_i32 s4, 0xfc191887; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v2, s4, v[0:1]1888; GFX9-NEXT: s_setpc_b64 s[30:31]1889;1890; GFX1100-LABEL: lshr_mad_i64_negative_1:1891; GFX1100: ; %bb.0:1892; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1893; GFX1100-NEXT: v_lshrrev_b32_e32 v4, 4, v11894; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1895; GFX1100-NEXT: v_mad_i64_i32 v[2:3], null, 0xfffffc19, v4, v[0:1]1896; GFX1100-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v31897; GFX1100-NEXT: s_setpc_b64 s[30:31]1898;1899; GFX1150-LABEL: lshr_mad_i64_negative_1:1900; GFX1150: ; %bb.0:1901; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1902; GFX1150-NEXT: v_lshrrev_b32_e32 v2, 4, v11903; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1)1904; GFX1150-NEXT: v_mad_i64_i32 v[0:1], null, 0xfffffc19, v2, v[0:1]1905; GFX1150-NEXT: s_setpc_b64 s[30:31]1906;1907; GFX12-LABEL: lshr_mad_i64_negative_1:1908; GFX12: ; %bb.0:1909; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01910; GFX12-NEXT: s_wait_expcnt 0x01911; GFX12-NEXT: s_wait_samplecnt 0x01912; GFX12-NEXT: s_wait_bvhcnt 0x01913; GFX12-NEXT: s_wait_kmcnt 0x01914; GFX12-NEXT: v_lshrrev_b32_e32 v2, 4, v11915; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1916; GFX12-NEXT: v_mad_co_i64_i32 v[0:1], null, 0xfffffc19, v2, v[0:1]1917; GFX12-NEXT: s_setpc_b64 s[30:31]1918;1919; GFX1250-LABEL: lshr_mad_i64_negative_1:1920; GFX1250: ; %bb.0:1921; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01922; GFX1250-NEXT: s_wait_kmcnt 0x01923; GFX1250-NEXT: v_lshrrev_b32_e32 v2, 4, v11924; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1925; GFX1250-NEXT: v_mad_nc_i64_i32 v[0:1], 0xfffffc19, v2, v[0:1]1926; GFX1250-NEXT: s_set_pc_i64 s[30:31]1927 %lsh = lshr i64 %arg0, 361928 %mul = mul i64 %lsh, s0xfffffffffffffc191929 %mad = add i64 %mul, %arg01930 1931 ret i64 %mad1932}1933 1934define i64 @lshr_mad_i64_negative_2(i64 %arg0) #0 {1935; CI-LABEL: lshr_mad_i64_negative_2:1936; CI: ; %bb.0:1937; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1938; CI-NEXT: s_movk_i32 s4, 0xd11939; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1]1940; CI-NEXT: v_lshlrev_b32_e32 v0, 8, v11941; CI-NEXT: v_sub_i32_e32 v1, vcc, v3, v01942; CI-NEXT: v_mov_b32_e32 v0, v21943; CI-NEXT: s_setpc_b64 s[30:31]1944;1945; SI-LABEL: lshr_mad_i64_negative_2:1946; SI: ; %bb.0:1947; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1948; SI-NEXT: s_movk_i32 s4, 0xd11949; SI-NEXT: v_mul_hi_u32 v2, v1, s41950; SI-NEXT: v_mul_lo_u32 v4, v1, s41951; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v11952; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v31953; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v01954; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc1955; SI-NEXT: s_setpc_b64 s[30:31]1956;1957; GFX9-LABEL: lshr_mad_i64_negative_2:1958; GFX9: ; %bb.0:1959; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1960; GFX9-NEXT: s_movk_i32 s4, 0xd11961; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, s4, v[0:1]1962; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v11963; GFX9-NEXT: v_sub_u32_e32 v1, v3, v01964; GFX9-NEXT: v_mov_b32_e32 v0, v21965; GFX9-NEXT: s_setpc_b64 s[30:31]1966;1967; GFX11-LABEL: lshr_mad_i64_negative_2:1968; GFX11: ; %bb.0:1969; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1970; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, 0xd1, v1, v[0:1]1971; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v11972; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)1973; GFX11-NEXT: v_sub_nc_u32_e32 v1, v3, v01974; GFX11-NEXT: v_mov_b32_e32 v0, v21975; GFX11-NEXT: s_setpc_b64 s[30:31]1976;1977; GFX12-LABEL: lshr_mad_i64_negative_2:1978; GFX12: ; %bb.0:1979; GFX12-NEXT: s_wait_loadcnt_dscnt 0x01980; GFX12-NEXT: s_wait_expcnt 0x01981; GFX12-NEXT: s_wait_samplecnt 0x01982; GFX12-NEXT: s_wait_bvhcnt 0x01983; GFX12-NEXT: s_wait_kmcnt 0x01984; GFX12-NEXT: v_mad_co_u64_u32 v[2:3], null, 0xd1, v1, v[0:1]1985; GFX12-NEXT: v_lshlrev_b32_e32 v0, 8, v11986; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)1987; GFX12-NEXT: v_sub_nc_u32_e32 v1, v3, v01988; GFX12-NEXT: v_mov_b32_e32 v0, v21989; GFX12-NEXT: s_setpc_b64 s[30:31]1990;1991; GFX1250-LABEL: lshr_mad_i64_negative_2:1992; GFX1250: ; %bb.0:1993; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x01994; GFX1250-NEXT: s_wait_kmcnt 0x01995; GFX1250-NEXT: v_mad_nc_u64_u32 v[2:3], 0xd1, v1, v[0:1]1996; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 8, v11997; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)1998; GFX1250-NEXT: v_dual_mov_b32 v0, v2 :: v_dual_sub_nc_u32 v1, v3, v01999; GFX1250-NEXT: s_set_pc_i64 s[30:31]2000 %lsh = lshr i64 %arg0, 322001 %mul = mul i64 %lsh, s0xffffff00000000d12002 %mad = add i64 %mul, %arg02003 2004 ret i64 %mad2005}2006 2007define i64 @lshr_mad_i64_negative_3(i64 %arg0) #0 {2008; CI-LABEL: lshr_mad_i64_negative_3:2009; CI: ; %bb.0:2010; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2011; CI-NEXT: v_lshr_b64 v[2:3], v[0:1], 222012; CI-NEXT: v_and_b32_e32 v2, 0xfffffc00, v22013; CI-NEXT: v_sub_i32_e32 v0, vcc, v0, v22014; CI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc2015; CI-NEXT: v_add_i32_e32 v0, vcc, 1, v02016; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2017; CI-NEXT: s_setpc_b64 s[30:31]2018;2019; SI-LABEL: lshr_mad_i64_negative_3:2020; SI: ; %bb.0:2021; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2022; SI-NEXT: v_lshr_b64 v[2:3], v[0:1], 222023; SI-NEXT: v_and_b32_e32 v2, 0xfffffc00, v22024; SI-NEXT: v_sub_i32_e32 v0, vcc, v0, v22025; SI-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc2026; SI-NEXT: v_add_i32_e32 v0, vcc, 1, v02027; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2028; SI-NEXT: s_setpc_b64 s[30:31]2029;2030; GFX9-LABEL: lshr_mad_i64_negative_3:2031; GFX9: ; %bb.0:2032; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2033; GFX9-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1]2034; GFX9-NEXT: v_and_b32_e32 v2, 0xfffffc00, v22035; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v22036; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc2037; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v02038; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc2039; GFX9-NEXT: s_setpc_b64 s[30:31]2040;2041; GFX11-LABEL: lshr_mad_i64_negative_3:2042; GFX11: ; %bb.0:2043; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2044; GFX11-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1]2045; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2046; GFX11-NEXT: v_and_b32_e32 v2, 0xfffffc00, v22047; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v22048; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2049; GFX11-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo2050; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 12051; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2052; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo2053; GFX11-NEXT: s_setpc_b64 s[30:31]2054;2055; GFX12-LABEL: lshr_mad_i64_negative_3:2056; GFX12: ; %bb.0:2057; GFX12-NEXT: s_wait_loadcnt_dscnt 0x02058; GFX12-NEXT: s_wait_expcnt 0x02059; GFX12-NEXT: s_wait_samplecnt 0x02060; GFX12-NEXT: s_wait_bvhcnt 0x02061; GFX12-NEXT: s_wait_kmcnt 0x02062; GFX12-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1]2063; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2064; GFX12-NEXT: v_and_b32_e32 v2, 0xfffffc00, v22065; GFX12-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v22066; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)2067; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2068; GFX12-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo2069; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 12070; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)2071; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)2072; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo2073; GFX12-NEXT: s_setpc_b64 s[30:31]2074;2075; GFX1250-LABEL: lshr_mad_i64_negative_3:2076; GFX1250: ; %bb.0:2077; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02078; GFX1250-NEXT: s_wait_kmcnt 0x02079; GFX1250-NEXT: v_lshrrev_b64 v[2:3], 22, v[0:1]2080; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2081; GFX1250-NEXT: v_and_b32_e32 v2, 0xfffffc00, v22082; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[0:1], v[2:3]2083; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2084; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 1, v[0:1]2085; GFX1250-NEXT: s_set_pc_i64 s[30:31]2086 %op = add i64 %arg0, 12087 %lsh = lshr i64 %arg0, 322088 %mul = mul i64 %lsh, s0xfffffffffffffc002089 %mad = add i64 %mul, %op2090 2091 ret i64 %mad2092}2093 2094define i64 @lshr_mad_i64_negative_4(i64 %arg0) #0 {2095; CI-LABEL: lshr_mad_i64_negative_4:2096; CI: ; %bb.0:2097; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2098; CI-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v0, v[0:1]2099; CI-NEXT: v_mul_lo_u32 v0, v1, v12100; CI-NEXT: v_add_i32_e32 v1, vcc, v0, v32101; CI-NEXT: v_mov_b32_e32 v0, v22102; CI-NEXT: s_setpc_b64 s[30:31]2103;2104; SI-LABEL: lshr_mad_i64_negative_4:2105; SI: ; %bb.0:2106; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2107; SI-NEXT: v_mul_hi_u32 v2, v1, v02108; SI-NEXT: v_mul_lo_u32 v3, v1, v12109; SI-NEXT: v_mul_lo_u32 v4, v1, v02110; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v32111; SI-NEXT: v_add_i32_e32 v0, vcc, v4, v02112; SI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc2113; SI-NEXT: s_setpc_b64 s[30:31]2114;2115; GFX9-LABEL: lshr_mad_i64_negative_4:2116; GFX9: ; %bb.0:2117; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2118; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v1, v0, v[0:1]2119; GFX9-NEXT: v_mov_b32_e32 v0, v32120; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v1, v[0:1]2121; GFX9-NEXT: v_mov_b32_e32 v0, v22122; GFX9-NEXT: v_mov_b32_e32 v1, v42123; GFX9-NEXT: s_setpc_b64 s[30:31]2124;2125; GFX1100-LABEL: lshr_mad_i64_negative_4:2126; GFX1100: ; %bb.0:2127; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2128; GFX1100-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v02129; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2130; GFX1100-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, v[2:3]2131; GFX1100-NEXT: v_mad_u64_u32 v[4:5], null, v3, v3, v[1:2]2132; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)2133; GFX1100-NEXT: v_mov_b32_e32 v1, v42134; GFX1100-NEXT: s_setpc_b64 s[30:31]2135;2136; GFX1150-LABEL: lshr_mad_i64_negative_4:2137; GFX1150: ; %bb.0:2138; GFX1150-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2139; GFX1150-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, v02140; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2141; GFX1150-NEXT: v_mad_u64_u32 v[0:1], null, v2, v1, v[1:2]2142; GFX1150-NEXT: v_mad_u64_u32 v[1:2], null, v2, v2, v[1:2]2143; GFX1150-NEXT: s_setpc_b64 s[30:31]2144;2145; GFX12-LABEL: lshr_mad_i64_negative_4:2146; GFX12: ; %bb.0:2147; GFX12-NEXT: s_wait_loadcnt_dscnt 0x02148; GFX12-NEXT: s_wait_expcnt 0x02149; GFX12-NEXT: s_wait_samplecnt 0x02150; GFX12-NEXT: s_wait_bvhcnt 0x02151; GFX12-NEXT: s_wait_kmcnt 0x02152; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, v02153; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2154; GFX12-NEXT: v_mad_co_u64_u32 v[0:1], null, v2, v1, v[1:2]2155; GFX12-NEXT: v_mad_co_u64_u32 v[1:2], null, v2, v2, v[1:2]2156; GFX12-NEXT: s_setpc_b64 s[30:31]2157;2158; GFX1250-LABEL: lshr_mad_i64_negative_4:2159; GFX1250: ; %bb.0:2160; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02161; GFX1250-NEXT: s_wait_kmcnt 0x02162; GFX1250-NEXT: v_mad_nc_u64_u32 v[2:3], v1, v0, v[0:1]2163; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2164; GFX1250-NEXT: v_mad_u32 v1, v1, v1, v32165; GFX1250-NEXT: v_mov_b32_e32 v0, v22166; GFX1250-NEXT: s_set_pc_i64 s[30:31]2167 %lsh = lshr i64 %arg0, 322168 %mul = mul i64 %lsh, %arg02169 %mad = add i64 %mul, %arg02170 2171 ret i64 %mad2172}2173 2174define amdgpu_ps i64 @lshr_mad_i64_sgpr(i64 inreg %arg0) #0 {2175; CI-LABEL: lshr_mad_i64_sgpr:2176; CI: ; %bb.0:2177; CI-NEXT: v_mov_b32_e32 v0, s02178; CI-NEXT: v_mov_b32_e32 v1, 02179; CI-NEXT: v_mov_b32_e32 v2, 0xffff1c182180; CI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s1, v2, v[0:1]2181; CI-NEXT: v_readfirstlane_b32 s0, v02182; CI-NEXT: v_readfirstlane_b32 s1, v12183; CI-NEXT: ; return to shader part epilog2184;2185; SI-LABEL: lshr_mad_i64_sgpr:2186; SI: ; %bb.0:2187; SI-NEXT: v_mov_b32_e32 v0, 0xffff1c182188; SI-NEXT: v_mul_hi_u32 v0, s1, v02189; SI-NEXT: s_mul_i32 s2, s1, 0xffff1c182190; SI-NEXT: v_mov_b32_e32 v1, s22191; SI-NEXT: v_mov_b32_e32 v2, s12192; SI-NEXT: v_subrev_i32_e32 v0, vcc, s1, v02193; SI-NEXT: v_add_i32_e32 v1, vcc, s0, v12194; SI-NEXT: v_addc_u32_e32 v0, vcc, v0, v2, vcc2195; SI-NEXT: v_readfirstlane_b32 s0, v12196; SI-NEXT: v_readfirstlane_b32 s1, v02197; SI-NEXT: ; return to shader part epilog2198;2199; GFX9-LABEL: lshr_mad_i64_sgpr:2200; GFX9: ; %bb.0:2201; GFX9-NEXT: s_mul_hi_u32 s2, s1, 0xffff1c182202; GFX9-NEXT: s_sub_i32 s2, s2, s12203; GFX9-NEXT: s_mul_i32 s3, s1, 0xffff1c182204; GFX9-NEXT: s_add_u32 s0, s3, s02205; GFX9-NEXT: s_addc_u32 s1, s2, s12206; GFX9-NEXT: ; return to shader part epilog2207;2208; GFX11-LABEL: lshr_mad_i64_sgpr:2209; GFX11: ; %bb.0:2210; GFX11-NEXT: s_mul_hi_u32 s2, s1, 0xffff1c182211; GFX11-NEXT: s_mul_i32 s3, s1, 0xffff1c182212; GFX11-NEXT: s_sub_i32 s2, s2, s12213; GFX11-NEXT: s_add_u32 s0, s3, s02214; GFX11-NEXT: s_addc_u32 s1, s2, s12215; GFX11-NEXT: ; return to shader part epilog2216;2217; GFX12-LABEL: lshr_mad_i64_sgpr:2218; GFX12: ; %bb.0:2219; GFX12-NEXT: s_mov_b32 s4, 0xffff1c182220; GFX12-NEXT: s_mov_b32 s3, 02221; GFX12-NEXT: s_mov_b32 s2, s12222; GFX12-NEXT: s_mov_b32 s5, -12223; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)2224; GFX12-NEXT: s_mul_u64 s[2:3], s[2:3], s[4:5]2225; GFX12-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]2226; GFX12-NEXT: ; return to shader part epilog2227;2228; GFX1250-LABEL: lshr_mad_i64_sgpr:2229; GFX1250: ; %bb.0:2230; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12231; GFX1250-NEXT: s_mov_b32 s3, 02232; GFX1250-NEXT: s_mov_b32 s2, s12233; GFX1250-NEXT: s_mov_b64 s[4:5], 0xffffffffffff1c182234; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)2235; GFX1250-NEXT: s_mul_u64 s[2:3], s[2:3], s[4:5]2236; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1]2237; GFX1250-NEXT: ; return to shader part epilog2238 %lsh = lshr i64 %arg0, 322239 %mul = mul i64 %lsh, s0xffffffffffff1c182240 %mad = add i64 %mul, %arg02241 2242 ret i64 %mad2243}2244 2245define <2 x i64> @lshr_mad_i64_vec(<2 x i64> %arg0) #0 {2246; CI-LABEL: lshr_mad_i64_vec:2247; CI: ; %bb.0:2248; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2249; CI-NEXT: s_mov_b32 s4, 0xffff1c182250; CI-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[0:1]2251; CI-NEXT: s_mov_b32 s4, 0xffff11182252; CI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v3, s4, v[2:3]2253; CI-NEXT: v_sub_i32_e32 v1, vcc, v5, v12254; CI-NEXT: v_sub_i32_e32 v3, vcc, v7, v32255; CI-NEXT: v_mov_b32_e32 v0, v42256; CI-NEXT: v_mov_b32_e32 v2, v62257; CI-NEXT: s_setpc_b64 s[30:31]2258;2259; SI-LABEL: lshr_mad_i64_vec:2260; SI: ; %bb.0:2261; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2262; SI-NEXT: s_mov_b32 s4, 0xffff11182263; SI-NEXT: v_mul_lo_u32 v4, v3, s42264; SI-NEXT: v_mul_hi_u32 v5, v3, s42265; SI-NEXT: s_mov_b32 s4, 0xffff1c182266; SI-NEXT: v_mul_hi_u32 v6, v1, s42267; SI-NEXT: v_mul_lo_u32 v7, v1, s42268; SI-NEXT: v_sub_i32_e32 v5, vcc, v5, v32269; SI-NEXT: v_sub_i32_e32 v6, vcc, v6, v12270; SI-NEXT: v_add_i32_e32 v0, vcc, v7, v02271; SI-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc2272; SI-NEXT: v_add_i32_e32 v2, vcc, v4, v22273; SI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc2274; SI-NEXT: s_setpc_b64 s[30:31]2275;2276; GFX9-LABEL: lshr_mad_i64_vec:2277; GFX9: ; %bb.0:2278; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2279; GFX9-NEXT: s_mov_b32 s4, 0xffff1c182280; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[0:1]2281; GFX9-NEXT: s_mov_b32 s4, 0xffff11182282; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v3, s4, v[2:3]2283; GFX9-NEXT: v_sub_u32_e32 v1, v5, v12284; GFX9-NEXT: v_sub_u32_e32 v3, v7, v32285; GFX9-NEXT: v_mov_b32_e32 v0, v42286; GFX9-NEXT: v_mov_b32_e32 v2, v62287; GFX9-NEXT: s_setpc_b64 s[30:31]2288;2289; GFX11-LABEL: lshr_mad_i64_vec:2290; GFX11: ; %bb.0:2291; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2292; GFX11-NEXT: v_mad_u64_u32 v[4:5], null, 0xffff1c18, v1, v[0:1]2293; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, 0xffff1118, v3, v[2:3]2294; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)2295; GFX11-NEXT: v_sub_nc_u32_e32 v1, v5, v12296; GFX11-NEXT: v_mov_b32_e32 v0, v42297; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2298; GFX11-NEXT: v_sub_nc_u32_e32 v3, v7, v32299; GFX11-NEXT: v_mov_b32_e32 v2, v62300; GFX11-NEXT: s_setpc_b64 s[30:31]2301;2302; GFX12-LABEL: lshr_mad_i64_vec:2303; GFX12: ; %bb.0:2304; GFX12-NEXT: s_wait_loadcnt_dscnt 0x02305; GFX12-NEXT: s_wait_expcnt 0x02306; GFX12-NEXT: s_wait_samplecnt 0x02307; GFX12-NEXT: s_wait_bvhcnt 0x02308; GFX12-NEXT: s_wait_kmcnt 0x02309; GFX12-NEXT: v_mad_co_u64_u32 v[4:5], null, 0xffff1c18, v1, v[0:1]2310; GFX12-NEXT: v_mad_co_u64_u32 v[6:7], null, 0xffff1118, v3, v[2:3]2311; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)2312; GFX12-NEXT: v_sub_nc_u32_e32 v1, v5, v12313; GFX12-NEXT: v_mov_b32_e32 v0, v42314; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2315; GFX12-NEXT: v_sub_nc_u32_e32 v3, v7, v32316; GFX12-NEXT: v_mov_b32_e32 v2, v62317; GFX12-NEXT: s_setpc_b64 s[30:31]2318;2319; GFX1250-LABEL: lshr_mad_i64_vec:2320; GFX1250: ; %bb.0:2321; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x02322; GFX1250-NEXT: s_wait_kmcnt 0x02323; GFX1250-NEXT: v_mad_nc_u64_u32 v[4:5], 0xffff1c18, v1, v[0:1]2324; GFX1250-NEXT: v_mad_nc_u64_u32 v[6:7], 0xffff1118, v3, v[2:3]2325; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)2326; GFX1250-NEXT: v_dual_sub_nc_u32 v1, v5, v1 :: v_dual_sub_nc_u32 v3, v7, v32327; GFX1250-NEXT: v_dual_mov_b32 v0, v4 :: v_dual_mov_b32 v2, v62328; GFX1250-NEXT: s_set_pc_i64 s[30:31]2329 %lsh = lshr <2 x i64> %arg0, <i64 32, i64 32>2330 %mul = mul <2 x i64> %lsh, <i64 s0xffffffffffff1c18, i64 s0xffffffffffff1118>2331 %mad = add <2 x i64> %mul, %arg02332 2333 ret <2 x i64> %mad2334}2335 2336attributes #0 = { nounwind }2337attributes #1 = { nounwind readnone speculatable }2338