371 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -mtriple=amdgcn| FileCheck %s --check-prefixes=GCN3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=VI4; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG,R600,RW5; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=EG,R600,CM6 7; Signed 24-bit multiply is not supported on pre-Cayman GPUs.8define amdgpu_kernel void @i32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {9; GCN-LABEL: i32_mad24:10; GCN: ; %bb.0: ; %entry11; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb12; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x913; GCN-NEXT: s_mov_b32 s7, 0xf00014; GCN-NEXT: s_waitcnt lgkmcnt(0)15; GCN-NEXT: s_bfe_i32 s0, s0, 0x18000016; GCN-NEXT: s_bfe_i32 s1, s1, 0x18000017; GCN-NEXT: s_mul_i32 s0, s0, s118; GCN-NEXT: s_add_i32 s0, s0, s219; GCN-NEXT: s_mov_b32 s6, -120; GCN-NEXT: v_mov_b32_e32 v0, s021; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 022; GCN-NEXT: s_endpgm23;24; VI-LABEL: i32_mad24:25; VI: ; %bb.0: ; %entry26; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c27; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2428; VI-NEXT: s_mov_b32 s7, 0xf00029; VI-NEXT: s_mov_b32 s6, -130; VI-NEXT: s_waitcnt lgkmcnt(0)31; VI-NEXT: s_bfe_i32 s0, s0, 0x18000032; VI-NEXT: s_bfe_i32 s1, s1, 0x18000033; VI-NEXT: s_mul_i32 s0, s0, s134; VI-NEXT: s_add_i32 s0, s0, s235; VI-NEXT: v_mov_b32_e32 v0, s036; VI-NEXT: buffer_store_dword v0, off, s[4:7], 037; VI-NEXT: s_endpgm38;39; RW-LABEL: i32_mad24:40; RW: ; %bb.0: ; %entry41; RW-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]42; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 143; RW-NEXT: CF_END44; RW-NEXT: PAD45; RW-NEXT: ALU clause starting at 4:46; RW-NEXT: LSHL T0.W, KC0[2].Z, literal.x,47; RW-NEXT: LSHL * T1.W, KC0[2].W, literal.x,48; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)49; RW-NEXT: ASHR T1.W, PS, literal.x,50; RW-NEXT: ASHR * T0.W, PV.W, literal.x,51; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)52; RW-NEXT: MULLO_INT * T0.X, PS, PV.W,53; RW-NEXT: ADD_INT T0.X, PS, KC0[3].X,54; RW-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,55; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00)56;57; CM-LABEL: i32_mad24:58; CM: ; %bb.0: ; %entry59; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]60; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X61; CM-NEXT: CF_END62; CM-NEXT: PAD63; CM-NEXT: ALU clause starting at 4:64; CM-NEXT: LSHL T0.Z, KC0[2].Z, literal.x,65; CM-NEXT: LSHL * T0.W, KC0[2].W, literal.x,66; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)67; CM-NEXT: ASHR T1.Z, PV.W, literal.x,68; CM-NEXT: ASHR * T0.W, PV.Z, literal.x,69; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)70; CM-NEXT: MULLO_INT T0.X, T0.W, T1.Z,71; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z,72; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Z,73; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z,74; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X,75; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,76; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)77entry:78 %0 = shl i32 %a, 879 %a_24 = ashr i32 %0, 880 %1 = shl i32 %b, 881 %b_24 = ashr i32 %1, 882 %2 = mul i32 %a_24, %b_2483 %3 = add i32 %2, %c84 store i32 %3, ptr addrspace(1) %out85 ret void86}87 88define i32 @mad24_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {89; GCN-LABEL: mad24_known_bits_destroyed:90; GCN: ; %bb.0:91; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v293; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v094; GCN-NEXT: s_setpc_b64 s[30:31]95;96; VI-LABEL: mad24_known_bits_destroyed:97; VI: ; %bb.0:98; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)99; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2100; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0101; VI-NEXT: s_setpc_b64 s[30:31]102;103; EG-LABEL: mad24_known_bits_destroyed:104; EG: ; %bb.0:105; EG-NEXT: CF_END106; EG-NEXT: PAD107 %shl.0 = shl i32 %a, 8108 %sra.0 = ashr i32 %shl.0, 8109 %shl.1 = shl i32 %b, 8110 %sra.1 = ashr i32 %shl.1, 8111 112 %mul0 = mul nsw i32 %sra.0, %sra.1113 %add0 = add nsw i32 %mul0, %c114 115 %shl.2 = shl i32 %add0, 8116 %sra.2 = ashr i32 %shl.2, 8117 118 %shl.3 = shl i32 %sra.0, 8119 %sra.3 = ashr i32 %shl.3, 8120 121 %mul1 = mul nsw i32 %sra.2, %sra.3122 ret i32 %mul1123}124 125define i32 @mad24_intrin_known_bits_destroyed(i32 %a, i32 %b, i32 %c) {126; GCN-LABEL: mad24_intrin_known_bits_destroyed:127; GCN: ; %bb.0:128; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; GCN-NEXT: v_mad_i32_i24 v1, v0, v1, v2130; GCN-NEXT: v_mul_i32_i24_e32 v0, v1, v0131; GCN-NEXT: s_setpc_b64 s[30:31]132;133; VI-LABEL: mad24_intrin_known_bits_destroyed:134; VI: ; %bb.0:135; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)136; VI-NEXT: v_mad_i32_i24 v1, v0, v1, v2137; VI-NEXT: v_mul_i32_i24_e32 v0, v1, v0138; VI-NEXT: s_setpc_b64 s[30:31]139;140; EG-LABEL: mad24_intrin_known_bits_destroyed:141; EG: ; %bb.0:142; EG-NEXT: CF_END143; EG-NEXT: PAD144 %shl.0 = shl i32 %a, 8145 %sra.0 = ashr i32 %shl.0, 8146 %shl.1 = shl i32 %b, 8147 %sra.1 = ashr i32 %shl.1, 8148 149 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1)150 %add0 = add nsw i32 %mul0, %c151 152 %shl.2 = shl i32 %add0, 8153 %sra.2 = ashr i32 %shl.2, 8154 155 %shl.3 = shl i32 %sra.0, 8156 %sra.3 = ashr i32 %shl.3, 8157 158 %mul1 = mul nsw i32 %sra.2, %sra.3159 ret i32 %mul1160}161 162; Make sure no unnecessary BFEs are emitted in the loop.163define void @mad24_destroyed_knownbits_2(i32 %arg, i32 %arg1, i32 %arg2, ptr addrspace(1) %arg3) {164; GCN-LABEL: mad24_destroyed_knownbits_2:165; GCN: ; %bb.0: ; %bb166; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)167; GCN-NEXT: v_mov_b32_e32 v5, 1168; GCN-NEXT: s_mov_b64 s[4:5], 0169; GCN-NEXT: .LBB3_1: ; %bb6170; GCN-NEXT: ; =>This Inner Loop Header: Depth=1171; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v5172; GCN-NEXT: v_add_i32_e32 v1, vcc, -1, v1173; GCN-NEXT: v_mad_i32_i24 v5, v0, v5, v0174; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1175; GCN-NEXT: v_mad_i32_i24 v0, v5, v0, v5176; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]177; GCN-NEXT: v_mad_i32_i24 v0, v0, v5, v0178; GCN-NEXT: v_mov_b32_e32 v5, v2179; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]180; GCN-NEXT: s_cbranch_execnz .LBB3_1181; GCN-NEXT: ; %bb.2: ; %bb5182; GCN-NEXT: s_or_b64 exec, exec, s[4:5]183; GCN-NEXT: s_mov_b32 s6, 0184; GCN-NEXT: s_mov_b32 s7, 0xf000185; GCN-NEXT: s_mov_b32 s4, s6186; GCN-NEXT: s_mov_b32 s5, s6187; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64188; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)189; GCN-NEXT: s_setpc_b64 s[30:31]190;191; VI-LABEL: mad24_destroyed_knownbits_2:192; VI: ; %bb.0: ; %bb193; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)194; VI-NEXT: v_mov_b32_e32 v5, 1195; VI-NEXT: s_mov_b64 s[4:5], 0196; VI-NEXT: .LBB3_1: ; %bb6197; VI-NEXT: ; =>This Inner Loop Header: Depth=1198; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v5199; VI-NEXT: v_mad_i32_i24 v5, v0, v5, v0200; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v1201; VI-NEXT: v_mad_i32_i24 v0, v5, v0, v5202; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1203; VI-NEXT: v_mad_i32_i24 v0, v0, v5, v0204; VI-NEXT: s_or_b64 s[4:5], vcc, s[4:5]205; VI-NEXT: v_mov_b32_e32 v5, v2206; VI-NEXT: s_andn2_b64 exec, exec, s[4:5]207; VI-NEXT: s_cbranch_execnz .LBB3_1208; VI-NEXT: ; %bb.2: ; %bb5209; VI-NEXT: s_or_b64 exec, exec, s[4:5]210; VI-NEXT: flat_store_dword v[3:4], v0211; VI-NEXT: s_waitcnt vmcnt(0)212; VI-NEXT: s_setpc_b64 s[30:31]213;214; RW-LABEL: mad24_destroyed_knownbits_2:215; RW: ; %bb.0: ; %bb216; RW-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]217; RW-NEXT: LOOP_START_DX10 @7218; RW-NEXT: ALU_PUSH_BEFORE 30, @16, KC0[], KC1[]219; RW-NEXT: JUMP @6 POP:1220; RW-NEXT: LOOP_BREAK @6221; RW-NEXT: POP @6 POP:1222; RW-NEXT: END_LOOP @2223; RW-NEXT: ALU 1, @47, KC0[], KC1[]224; RW-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1225; RW-NEXT: CF_END226; RW-NEXT: ALU clause starting at 10:227; RW-NEXT: MOV T0.X, KC0[2].Y,228; RW-NEXT: MOV T0.Y, KC0[2].Z,229; RW-NEXT: MOV * T0.Z, KC0[2].W,230; RW-NEXT: MOV T0.W, KC0[3].X,231; RW-NEXT: MOV * T1.W, literal.x,232; RW-NEXT: 1(1.401298e-45), 0(0.000000e+00)233; RW-NEXT: ALU clause starting at 16:234; RW-NEXT: LSHL T2.W, T1.W, literal.x,235; RW-NEXT: LSHL * T3.W, T0.X, literal.x,236; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)237; RW-NEXT: ASHR T3.W, PS, literal.x,238; RW-NEXT: ASHR * T2.W, PV.W, literal.x,239; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)240; RW-NEXT: MULLO_INT * T0.X, PV.W, PS,241; RW-NEXT: ADD_INT * T1.W, PS, T1.W,242; RW-NEXT: LSHL * T3.W, PV.W, literal.x,243; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)244; RW-NEXT: ASHR * T3.W, PV.W, literal.x,245; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)246; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W,247; RW-NEXT: ADD_INT * T1.W, PS, T1.W,248; RW-NEXT: LSHL * T2.W, PV.W, literal.x,249; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)250; RW-NEXT: ASHR * T2.W, PV.W, literal.x,251; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)252; RW-NEXT: MULLO_INT * T0.X, PV.W, T3.W,253; RW-NEXT: ADD_INT * T1.W, PS, T1.W,254; RW-NEXT: LSHL * T3.W, PV.W, literal.x,255; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)256; RW-NEXT: ASHR * T3.W, PV.W, literal.x,257; RW-NEXT: 8(1.121039e-44), 0(0.000000e+00)258; RW-NEXT: ADD_INT T0.Y, T0.Y, literal.x,259; RW-NEXT: MULLO_INT * T0.X, PV.W, T2.W,260; RW-NEXT: -1(nan), 0(0.000000e+00)261; RW-NEXT: ADD_INT T0.X, PS, T1.W,262; RW-NEXT: SETE_INT T2.W, PV.Y, 0.0,263; RW-NEXT: MOV * T1.W, T0.Z,264; RW-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,265; RW-NEXT: ALU clause starting at 47:266; RW-NEXT: LSHR * T1.X, T0.W, literal.x,267; RW-NEXT: 2(2.802597e-45), 0(0.000000e+00)268;269; CM-LABEL: mad24_destroyed_knownbits_2:270; CM: ; %bb.0: ; %bb271; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]272; CM-NEXT: LOOP_START_DX10 @7273; CM-NEXT: ALU_PUSH_BEFORE 41, @16, KC0[], KC1[]274; CM-NEXT: JUMP @6 POP:1275; CM-NEXT: LOOP_BREAK @6276; CM-NEXT: POP @6 POP:1277; CM-NEXT: END_LOOP @2278; CM-NEXT: ALU 1, @58, KC0[], KC1[]279; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X280; CM-NEXT: CF_END281; CM-NEXT: ALU clause starting at 10:282; CM-NEXT: MOV * T1.X, KC0[2].Y,283; CM-NEXT: MOV T0.X, KC0[2].Z,284; CM-NEXT: MOV T0.Y, KC0[2].W,285; CM-NEXT: MOV T0.Z, KC0[3].X,286; CM-NEXT: MOV * T0.W, literal.x,287; CM-NEXT: 1(1.401298e-45), 0(0.000000e+00)288; CM-NEXT: ALU clause starting at 16:289; CM-NEXT: LSHL T1.Z, T0.W, literal.x,290; CM-NEXT: LSHL * T1.W, T1.X, literal.x,291; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)292; CM-NEXT: ASHR T2.Z, PV.W, literal.x,293; CM-NEXT: ASHR * T1.W, PV.Z, literal.x,294; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)295; CM-NEXT: MULLO_INT T1.X, T2.Z, T1.W,296; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.Z, T1.W,297; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.Z, T1.W,298; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.Z, T1.W,299; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W,300; CM-NEXT: LSHL * T2.W, PV.W, literal.x,301; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)302; CM-NEXT: ASHR * T2.W, PV.W, literal.x,303; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)304; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W,305; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W,306; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W,307; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W,308; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W,309; CM-NEXT: LSHL * T1.W, PV.W, literal.x,310; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)311; CM-NEXT: ASHR * T1.W, PV.W, literal.x,312; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)313; CM-NEXT: MULLO_INT T1.X, T1.W, T2.W,314; CM-NEXT: MULLO_INT T1.Y (MASKED), T1.W, T2.W,315; CM-NEXT: MULLO_INT T1.Z (MASKED), T1.W, T2.W,316; CM-NEXT: MULLO_INT * T1.W (MASKED), T1.W, T2.W,317; CM-NEXT: ADD_INT * T0.W, PV.X, T0.W,318; CM-NEXT: LSHL * T2.W, PV.W, literal.x,319; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)320; CM-NEXT: ADD_INT T0.X, T0.X, literal.x,321; CM-NEXT: ASHR * T2.W, PV.W, literal.y,322; CM-NEXT: -1(nan), 8(1.121039e-44)323; CM-NEXT: MULLO_INT T1.X, T2.W, T1.W,324; CM-NEXT: MULLO_INT T1.Y (MASKED), T2.W, T1.W,325; CM-NEXT: MULLO_INT T1.Z (MASKED), T2.W, T1.W,326; CM-NEXT: MULLO_INT * T1.W (MASKED), T2.W, T1.W,327; CM-NEXT: ADD_INT T1.X, PV.X, T0.W,328; CM-NEXT: SETE_INT T1.Z, T0.X, 0.0,329; CM-NEXT: MOV * T0.W, T0.Y,330; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.Z, 0.0,331; CM-NEXT: ALU clause starting at 58:332; CM-NEXT: LSHR * T0.X, T0.Z, literal.x,333; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)334bb:335 br label %bb6336 337bb5: ; preds = %bb6338 ret void339 340bb6: ; preds = %bb6, %bb341 %tmp = phi i32 [ %tmp27, %bb6 ], [ 0, %bb ]342 %tmp7 = phi i32 [ %arg2, %bb6 ], [ 1, %bb ]343 %tmp8 = phi i32 [ %tmp26, %bb6 ], [ %arg, %bb ]344 %tmp9 = shl i32 %tmp7, 8345 %tmp10 = ashr exact i32 %tmp9, 8346 %tmp11 = shl i32 %tmp8, 8347 %tmp12 = ashr exact i32 %tmp11, 8348 %tmp13 = mul nsw i32 %tmp12, %tmp10349 %tmp14 = add nsw i32 %tmp13, %tmp7350 %tmp15 = shl i32 %tmp14, 8351 %tmp16 = ashr exact i32 %tmp15, 8352 %tmp17 = mul nsw i32 %tmp16, %tmp10353 %tmp18 = add nsw i32 %tmp17, %tmp14354 %tmp19 = shl i32 %tmp18, 8355 %tmp20 = ashr exact i32 %tmp19, 8356 %tmp21 = mul nsw i32 %tmp20, %tmp16357 %tmp22 = add nsw i32 %tmp21, %tmp18358 %tmp23 = shl i32 %tmp22, 8359 %tmp24 = ashr exact i32 %tmp23, 8360 %tmp25 = mul nsw i32 %tmp24, %tmp20361 %tmp26 = add nsw i32 %tmp25, %tmp22362 store i32 %tmp26, ptr addrspace(1) %arg3363 %tmp27 = add nuw i32 %tmp, 1364 %tmp28 = icmp eq i32 %tmp27, %arg1365 br i1 %tmp28, label %bb5, label %bb6366}367 368declare i32 @llvm.amdgcn.mul.i24(i32, i32)369;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:370; R600: {{.*}}371