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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX9 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefixes=GFX10 %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GFX10 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefixes=GFX11 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX1250 %s8 9define amdgpu_ps float @mad_i32_vvv(i32 %a, i32 %b, i32 %c) {10; GFX9-LABEL: mad_i32_vvv:11; GFX9: ; %bb.0:12; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]13; GFX9-NEXT: ; return to shader part epilog14;15; GFX10-LABEL: mad_i32_vvv:16; GFX10: ; %bb.0:17; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, v[2:3]18; GFX10-NEXT: ; return to shader part epilog19;20; GFX11-LABEL: mad_i32_vvv:21; GFX11: ; %bb.0:22; GFX11-NEXT: v_mov_b32_e32 v3, v123; GFX11-NEXT: v_mov_b32_e32 v4, v024; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v3, v[2:3]25; GFX11-NEXT: ; return to shader part epilog26;27; GFX1250-LABEL: mad_i32_vvv:28; GFX1250: ; %bb.0:29; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 130; GFX1250-NEXT: v_mad_u32 v0, v0, v1, v231; GFX1250-NEXT: ; return to shader part epilog32 %mul = mul i32 %a, %b33 %add = add i32 %mul, %c34 %cast = bitcast i32 %add to float35 ret float %cast36}37 38define amdgpu_ps float @mad_i32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {39; GFX9-LABEL: mad_i32_sss:40; GFX9: ; %bb.0:41; GFX9-NEXT: s_mul_i32 s0, s0, s142; GFX9-NEXT: s_add_i32 s0, s0, s243; GFX9-NEXT: v_mov_b32_e32 v0, s044; GFX9-NEXT: ; return to shader part epilog45;46; GFX10-LABEL: mad_i32_sss:47; GFX10: ; %bb.0:48; GFX10-NEXT: s_mul_i32 s0, s0, s149; GFX10-NEXT: s_add_i32 s0, s0, s250; GFX10-NEXT: v_mov_b32_e32 v0, s051; GFX10-NEXT: ; return to shader part epilog52;53; GFX11-LABEL: mad_i32_sss:54; GFX11: ; %bb.0:55; GFX11-NEXT: s_mul_i32 s0, s0, s156; GFX11-NEXT: s_add_i32 s0, s0, s257; GFX11-NEXT: v_mov_b32_e32 v0, s058; GFX11-NEXT: ; return to shader part epilog59;60; GFX1250-LABEL: mad_i32_sss:61; GFX1250: ; %bb.0:62; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 163; GFX1250-NEXT: s_mul_i32 s0, s0, s164; GFX1250-NEXT: s_add_co_i32 s0, s0, s265; GFX1250-NEXT: v_mov_b32_e32 v0, s066; GFX1250-NEXT: ; return to shader part epilog67 %mul = mul i32 %a, %b68 %add = add i32 %mul, %c69 %cast = bitcast i32 %add to float70 ret float %cast71}72 73define amdgpu_ps float @mad_i32_vvc(i32 %a, i32 %b) {74; GFX9-LABEL: mad_i32_vvc:75; GFX9: ; %bb.0:76; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, 4277; GFX9-NEXT: ; return to shader part epilog78;79; GFX10-LABEL: mad_i32_vvc:80; GFX10: ; %bb.0:81; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, 4282; GFX10-NEXT: ; return to shader part epilog83;84; GFX11-LABEL: mad_i32_vvc:85; GFX11: ; %bb.0:86; GFX11-NEXT: v_mov_b32_e32 v2, v187; GFX11-NEXT: v_mov_b32_e32 v3, v088; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, 4289; GFX11-NEXT: ; return to shader part epilog90;91; GFX1250-LABEL: mad_i32_vvc:92; GFX1250: ; %bb.0:93; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 194; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 4295; GFX1250-NEXT: ; return to shader part epilog96 %mul = mul i32 %a, %b97 %add = add i32 %mul, 4298 %cast = bitcast i32 %add to float99 ret float %cast100}101 102define amdgpu_ps float @mad_i32_vvi(i32 %a, i32 %b) {103; GFX9-LABEL: mad_i32_vvi:104; GFX9: ; %bb.0:105; GFX9-NEXT: v_mov_b32_e32 v2, 0x12d687106; GFX9-NEXT: v_mov_b32_e32 v3, 0107; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]108; GFX9-NEXT: ; return to shader part epilog109;110; GFX10-LABEL: mad_i32_vvi:111; GFX10: ; %bb.0:112; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, 0x12d687113; GFX10-NEXT: ; return to shader part epilog114;115; GFX11-LABEL: mad_i32_vvi:116; GFX11: ; %bb.0:117; GFX11-NEXT: v_mov_b32_e32 v2, v1118; GFX11-NEXT: v_mov_b32_e32 v3, v0119; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, 0x12d687120; GFX11-NEXT: ; return to shader part epilog121;122; GFX1250-LABEL: mad_i32_vvi:123; GFX1250: ; %bb.0:124; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1125; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 0x12d687126; GFX1250-NEXT: ; return to shader part epilog127 %mul = mul i32 %a, %b128 %add = add i32 %mul, 1234567129 %cast = bitcast i32 %add to float130 ret float %cast131}132 133define amdgpu_ps float @mad_i32_vvi_neg(i32 %a, i32 %b) {134; GFX9-LABEL: mad_i32_vvi_neg:135; GFX9: ; %bb.0:136; GFX9-NEXT: v_mov_b32_e32 v2, 0xffed2979137; GFX9-NEXT: v_mov_b32_e32 v3, -1138; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]139; GFX9-NEXT: ; return to shader part epilog140;141; GFX10-LABEL: mad_i32_vvi_neg:142; GFX10: ; %bb.0:143; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, 0xffffffffffed2979144; GFX10-NEXT: ; return to shader part epilog145;146; GFX11-LABEL: mad_i32_vvi_neg:147; GFX11: ; %bb.0:148; GFX11-NEXT: v_mov_b32_e32 v2, v1149; GFX11-NEXT: v_mov_b32_e32 v3, v0150; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, 0xffffffffffed2979151; GFX11-NEXT: ; return to shader part epilog152;153; GFX1250-LABEL: mad_i32_vvi_neg:154; GFX1250: ; %bb.0:155; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1156; GFX1250-NEXT: v_mad_u32 v0, v0, v1, 0xffed2979157; GFX1250-NEXT: ; return to shader part epilog158 %mul = mul i32 %a, %b159 %add = add i32 %mul, -1234567160 %cast = bitcast i32 %add to float161 ret float %cast162}163 164define amdgpu_ps float @mad_i32_vcv(i32 %a, i32 %c) {165; GFX9-LABEL: mad_i32_vcv:166; GFX9: ; %bb.0:167; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 42, v[1:2]168; GFX9-NEXT: ; return to shader part epilog169;170; GFX10-LABEL: mad_i32_vcv:171; GFX10: ; %bb.0:172; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 42, v[1:2]173; GFX10-NEXT: ; return to shader part epilog174;175; GFX11-LABEL: mad_i32_vcv:176; GFX11: ; %bb.0:177; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, 42, v[1:2]178; GFX11-NEXT: v_mov_b32_e32 v0, v2179; GFX11-NEXT: ; return to shader part epilog180;181; GFX1250-LABEL: mad_i32_vcv:182; GFX1250: ; %bb.0:183; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1184; GFX1250-NEXT: v_mad_u32 v0, v0, 42, v1185; GFX1250-NEXT: ; return to shader part epilog186 %mul = mul i32 %a, 42187 %add = add i32 %mul, %c188 %cast = bitcast i32 %add to float189 ret float %cast190}191 192define amdgpu_ps float @mad_i32_vcc(i32 %a) {193; GFX9-LABEL: mad_i32_vcc:194; GFX9: ; %bb.0:195; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 42, 43196; GFX9-NEXT: ; return to shader part epilog197;198; GFX10-LABEL: mad_i32_vcc:199; GFX10: ; %bb.0:200; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, 42, 43201; GFX10-NEXT: ; return to shader part epilog202;203; GFX11-LABEL: mad_i32_vcc:204; GFX11: ; %bb.0:205; GFX11-NEXT: v_mov_b32_e32 v2, v0206; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, 42, 43207; GFX11-NEXT: ; return to shader part epilog208;209; GFX1250-LABEL: mad_i32_vcc:210; GFX1250: ; %bb.0:211; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1212; GFX1250-NEXT: v_mad_u32 v0, v0, 42, 43213; GFX1250-NEXT: ; return to shader part epilog214 %mul = mul i32 %a, 42215 %add = add i32 %mul, 43216 %cast = bitcast i32 %add to float217 ret float %cast218}219 220define amdgpu_ps float @mad_i32_vvs(i32 %a, i32 %b, i32 inreg %c) {221; GFX9-LABEL: mad_i32_vvs:222; GFX9: ; %bb.0:223; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, v1, s[0:1]224; GFX9-NEXT: ; return to shader part epilog225;226; GFX10-LABEL: mad_i32_vvs:227; GFX10: ; %bb.0:228; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, v1, s[0:1]229; GFX10-NEXT: ; return to shader part epilog230;231; GFX11-LABEL: mad_i32_vvs:232; GFX11: ; %bb.0:233; GFX11-NEXT: v_mov_b32_e32 v2, v1234; GFX11-NEXT: v_mov_b32_e32 v3, v0235; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v3, v2, s[0:1]236; GFX11-NEXT: ; return to shader part epilog237;238; GFX1250-LABEL: mad_i32_vvs:239; GFX1250: ; %bb.0:240; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1241; GFX1250-NEXT: v_mad_u32 v0, v0, v1, s0242; GFX1250-NEXT: ; return to shader part epilog243 %mul = mul i32 %a, %b244 %add = add i32 %mul, %c245 %cast = bitcast i32 %add to float246 ret float %cast247}248 249define amdgpu_ps float @mad_i32_vsv(i32 %a, i32 inreg %b, i32 %c) {250; GFX9-LABEL: mad_i32_vsv:251; GFX9: ; %bb.0:252; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, s0, v[1:2]253; GFX9-NEXT: ; return to shader part epilog254;255; GFX10-LABEL: mad_i32_vsv:256; GFX10: ; %bb.0:257; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s0, v[1:2]258; GFX10-NEXT: ; return to shader part epilog259;260; GFX11-LABEL: mad_i32_vsv:261; GFX11: ; %bb.0:262; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]263; GFX11-NEXT: v_mov_b32_e32 v0, v2264; GFX11-NEXT: ; return to shader part epilog265;266; GFX1250-LABEL: mad_i32_vsv:267; GFX1250: ; %bb.0:268; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1269; GFX1250-NEXT: v_mad_u32 v0, v0, s0, v1270; GFX1250-NEXT: ; return to shader part epilog271 %mul = mul i32 %a, %b272 %add = add i32 %mul, %c273 %cast = bitcast i32 %add to float274 ret float %cast275}276 277define amdgpu_ps float @mad_i32_svv(i32 inreg %a, i32 %b, i32 %c) {278; GFX9-LABEL: mad_i32_svv:279; GFX9: ; %bb.0:280; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s0, v0, v[1:2]281; GFX9-NEXT: ; return to shader part epilog282;283; GFX10-LABEL: mad_i32_svv:284; GFX10: ; %bb.0:285; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, v0, v[1:2]286; GFX10-NEXT: ; return to shader part epilog287;288; GFX11-LABEL: mad_i32_svv:289; GFX11: ; %bb.0:290; GFX11-NEXT: v_mad_u64_u32 v[2:3], null, s0, v0, v[1:2]291; GFX11-NEXT: v_mov_b32_e32 v0, v2292; GFX11-NEXT: ; return to shader part epilog293;294; GFX1250-LABEL: mad_i32_svv:295; GFX1250: ; %bb.0:296; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1297; GFX1250-NEXT: v_mad_u32 v0, s0, v0, v1298; GFX1250-NEXT: ; return to shader part epilog299 %mul = mul i32 %a, %b300 %add = add i32 %mul, %c301 %cast = bitcast i32 %add to float302 ret float %cast303}304 305define amdgpu_ps float @mad_i32_vss(i32 %a, i32 inreg %b, i32 inreg %c) {306; GFX9-LABEL: mad_i32_vss:307; GFX9: ; %bb.0:308; GFX9-NEXT: v_mul_lo_u32 v0, v0, s0309; GFX9-NEXT: v_add_u32_e32 v0, s1, v0310; GFX9-NEXT: ; return to shader part epilog311;312; GFX10-LABEL: mad_i32_vss:313; GFX10: ; %bb.0:314; GFX10-NEXT: s_mov_b32 s2, s1315; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, v0, s0, s[2:3]316; GFX10-NEXT: ; return to shader part epilog317;318; GFX11-LABEL: mad_i32_vss:319; GFX11: ; %bb.0:320; GFX11-NEXT: v_mov_b32_e32 v2, v0321; GFX11-NEXT: s_mov_b32 s2, s1322; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v2, s0, s[2:3]323; GFX11-NEXT: ; return to shader part epilog324;325; GFX1250-LABEL: mad_i32_vss:326; GFX1250: ; %bb.0:327; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1328; GFX1250-NEXT: v_mad_u32 v0, v0, s0, s1329; GFX1250-NEXT: ; return to shader part epilog330 %mul = mul i32 %a, %b331 %add = add i32 %mul, %c332 %cast = bitcast i32 %add to float333 ret float %cast334}335 336define amdgpu_ps float @mad_i32_svs(i32 inreg %a, i32 %b, i32 inreg %c) {337; GFX9-LABEL: mad_i32_svs:338; GFX9: ; %bb.0:339; GFX9-NEXT: v_mul_lo_u32 v0, s0, v0340; GFX9-NEXT: v_add_u32_e32 v0, s1, v0341; GFX9-NEXT: ; return to shader part epilog342;343; GFX10-LABEL: mad_i32_svs:344; GFX10: ; %bb.0:345; GFX10-NEXT: s_mov_b32 s2, s1346; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, v0, s[2:3]347; GFX10-NEXT: ; return to shader part epilog348;349; GFX11-LABEL: mad_i32_svs:350; GFX11: ; %bb.0:351; GFX11-NEXT: v_mov_b32_e32 v2, v0352; GFX11-NEXT: s_mov_b32 s2, s1353; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, s0, v2, s[2:3]354; GFX11-NEXT: ; return to shader part epilog355;356; GFX1250-LABEL: mad_i32_svs:357; GFX1250: ; %bb.0:358; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1359; GFX1250-NEXT: v_mad_u32 v0, s0, v0, s1360; GFX1250-NEXT: ; return to shader part epilog361 %mul = mul i32 %a, %b362 %add = add i32 %mul, %c363 %cast = bitcast i32 %add to float364 ret float %cast365}366 367define amdgpu_ps float @mad_i32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {368; GFX9-LABEL: mad_i32_ssv:369; GFX9: ; %bb.0:370; GFX9-NEXT: s_mul_i32 s0, s0, s1371; GFX9-NEXT: v_add_u32_e32 v0, s0, v0372; GFX9-NEXT: ; return to shader part epilog373;374; GFX10-LABEL: mad_i32_ssv:375; GFX10: ; %bb.0:376; GFX10-NEXT: v_mad_u64_u32 v[0:1], null, s0, s1, v[0:1]377; GFX10-NEXT: ; return to shader part epilog378;379; GFX11-LABEL: mad_i32_ssv:380; GFX11: ; %bb.0:381; GFX11-NEXT: v_mad_u64_u32 v[1:2], null, s0, s1, v[0:1]382; GFX11-NEXT: v_mov_b32_e32 v0, v1383; GFX11-NEXT: ; return to shader part epilog384;385; GFX1250-LABEL: mad_i32_ssv:386; GFX1250: ; %bb.0:387; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1388; GFX1250-NEXT: v_mad_u32 v0, s0, s1, v0389; GFX1250-NEXT: ; return to shader part epilog390 %mul = mul i32 %a, %b391 %add = add i32 %mul, %c392 %cast = bitcast i32 %add to float393 ret float %cast394}395 396define amdgpu_ps float @mad_i32_vvv_multiuse(i32 %a, i32 %b, i32 %c) {397; GFX9-LABEL: mad_i32_vvv_multiuse:398; GFX9: ; %bb.0:399; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1400; GFX9-NEXT: v_add_u32_e32 v0, v1, v2401; GFX9-NEXT: flat_store_dword v[0:1], v1402; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)403; GFX9-NEXT: ; return to shader part epilog404;405; GFX10-LABEL: mad_i32_vvv_multiuse:406; GFX10: ; %bb.0:407; GFX10-NEXT: v_mul_lo_u32 v1, v0, v1408; GFX10-NEXT: v_add_nc_u32_e32 v0, v1, v2409; GFX10-NEXT: flat_store_dword v[0:1], v1410; GFX10-NEXT: s_waitcnt lgkmcnt(0)411; GFX10-NEXT: ; return to shader part epilog412;413; GFX11-LABEL: mad_i32_vvv_multiuse:414; GFX11: ; %bb.0:415; GFX11-NEXT: v_mul_lo_u32 v1, v0, v1416; GFX11-NEXT: v_add_nc_u32_e32 v0, v1, v2417; GFX11-NEXT: flat_store_b32 v[0:1], v1418; GFX11-NEXT: s_waitcnt lgkmcnt(0)419; GFX11-NEXT: ; return to shader part epilog420;421; GFX1250-LABEL: mad_i32_vvv_multiuse:422; GFX1250: ; %bb.0:423; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1424; GFX1250-NEXT: v_mul_lo_u32 v1, v0, v1425; GFX1250-NEXT: v_add_nc_u32_e32 v0, v1, v2426; GFX1250-NEXT: flat_store_b32 v[0:1], v1427; GFX1250-NEXT: s_wait_dscnt 0x0428; GFX1250-NEXT: ; return to shader part epilog429 %mul = mul i32 %a, %b430 %add = add i32 %mul, %c431 store i32 %mul, ptr poison432 %cast = bitcast i32 %add to float433 ret float %cast434}435