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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=EG3; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s --check-prefixes=CM4; RUN: llc < %s -mtriple=amdgcn | FileCheck %s --check-prefixes=GCN5; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX8,SI6; RUN: llc < %s -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global | FileCheck %s --check-prefixes=GFX8,VI7 8declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone9 10define amdgpu_kernel void @u32_mad24(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {11; EG-LABEL: u32_mad24:12; EG: ; %bb.0: ; %entry13; EG-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]14; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 115; EG-NEXT: CF_END16; EG-NEXT: PAD17; EG-NEXT: ALU clause starting at 4:18; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,19; EG-NEXT: AND_INT * T1.W, KC0[2].Z, literal.x,20; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)21; EG-NEXT: MULLO_INT * T0.X, PS, PV.W,22; EG-NEXT: ADD_INT T0.X, PS, KC0[3].X,23; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,24; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)25;26; CM-LABEL: u32_mad24:27; CM: ; %bb.0: ; %entry28; CM-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]29; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X30; CM-NEXT: CF_END31; CM-NEXT: PAD32; CM-NEXT: ALU clause starting at 4:33; CM-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,34; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,35; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)36; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z,37; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z,38; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z,39; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z,40; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].X,41; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,42; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)43;44; GCN-LABEL: u32_mad24:45; GCN: ; %bb.0: ; %entry46; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb47; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x948; GCN-NEXT: s_mov_b32 s7, 0xf00049; GCN-NEXT: s_waitcnt lgkmcnt(0)50; GCN-NEXT: s_and_b32 s0, s0, 0xffffff51; GCN-NEXT: s_and_b32 s1, s1, 0xffffff52; GCN-NEXT: s_mul_i32 s0, s0, s153; GCN-NEXT: s_add_i32 s0, s0, s254; GCN-NEXT: s_mov_b32 s6, -155; GCN-NEXT: v_mov_b32_e32 v0, s056; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 057; GCN-NEXT: s_endpgm58;59; GFX8-LABEL: u32_mad24:60; GFX8: ; %bb.0: ; %entry61; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c62; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x2463; GFX8-NEXT: s_mov_b32 s7, 0xf00064; GFX8-NEXT: s_mov_b32 s6, -165; GFX8-NEXT: s_waitcnt lgkmcnt(0)66; GFX8-NEXT: s_and_b32 s0, s0, 0xffffff67; GFX8-NEXT: s_and_b32 s1, s1, 0xffffff68; GFX8-NEXT: s_mul_i32 s0, s0, s169; GFX8-NEXT: s_add_i32 s0, s0, s270; GFX8-NEXT: v_mov_b32_e32 v0, s071; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 072; GFX8-NEXT: s_endpgm73entry:74 %0 = shl i32 %a, 875 %a_24 = lshr i32 %0, 876 %1 = shl i32 %b, 877 %b_24 = lshr i32 %1, 878 %2 = mul i32 %a_24, %b_2479 %3 = add i32 %2, %c80 store i32 %3, ptr addrspace(1) %out81 ret void82}83 84; The order of A and B does not matter.85; The result must be sign-extended86define amdgpu_kernel void @i16_mad24(ptr addrspace(1) %out, i16 %a, i16 %b, i16 %c) {87; EG-LABEL: i16_mad24:88; EG: ; %bb.0: ; %entry89; EG-NEXT: ALU 0, @12, KC0[], KC1[]90; EG-NEXT: TEX 2 @691; EG-NEXT: ALU 4, @13, KC0[CB0:0-32], KC1[]92; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 193; EG-NEXT: CF_END94; EG-NEXT: PAD95; EG-NEXT: Fetch clause starting at 6:96; EG-NEXT: VTX_READ_16 T1.X, T0.X, 40, #397; EG-NEXT: VTX_READ_16 T2.X, T0.X, 42, #398; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #399; EG-NEXT: ALU clause starting at 12:100; EG-NEXT: MOV * T0.X, 0.0,101; EG-NEXT: ALU clause starting at 13:102; EG-NEXT: MULLO_INT * T0.Y, T1.X, T2.X,103; EG-NEXT: ADD_INT * T0.W, PS, T0.X,104; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x,105; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,106; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)107;108; CM-LABEL: i16_mad24:109; CM: ; %bb.0: ; %entry110; CM-NEXT: ALU 0, @12, KC0[], KC1[]111; CM-NEXT: TEX 2 @6112; CM-NEXT: ALU 8, @13, KC0[CB0:0-32], KC1[]113; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X114; CM-NEXT: CF_END115; CM-NEXT: PAD116; CM-NEXT: Fetch clause starting at 6:117; CM-NEXT: VTX_READ_16 T1.X, T0.X, 40, #3118; CM-NEXT: VTX_READ_16 T2.X, T0.X, 42, #3119; CM-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3120; CM-NEXT: ALU clause starting at 12:121; CM-NEXT: MOV * T0.X, 0.0,122; CM-NEXT: ALU clause starting at 13:123; CM-NEXT: MULLO_INT T0.X (MASKED), T1.X, T2.X,124; CM-NEXT: MULLO_INT T0.Y, T1.X, T2.X,125; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.X, T2.X,126; CM-NEXT: MULLO_INT * T0.W (MASKED), T1.X, T2.X,127; CM-NEXT: ADD_INT * T0.W, PV.Y, T0.X,128; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x,129; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)130; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,131; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)132;133; GCN-LABEL: i16_mad24:134; GCN: ; %bb.0: ; %entry135; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9136; GCN-NEXT: s_waitcnt lgkmcnt(0)137; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]138; GCN-NEXT: s_mov_b32 s3, 0xf000139; GCN-NEXT: s_lshr_b32 s2, s4, 16140; GCN-NEXT: s_mul_i32 s2, s4, s2141; GCN-NEXT: s_add_i32 s2, s2, s5142; GCN-NEXT: s_sext_i32_i16 s4, s2143; GCN-NEXT: s_mov_b32 s2, -1144; GCN-NEXT: v_mov_b32_e32 v0, s4145; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0146; GCN-NEXT: s_endpgm147;148; GFX8-LABEL: i16_mad24:149; GFX8: ; %bb.0: ; %entry150; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24151; GFX8-NEXT: s_waitcnt lgkmcnt(0)152; GFX8-NEXT: s_mov_b64 s[4:5], s[2:3]153; GFX8-NEXT: s_lshr_b32 s6, s4, 16154; GFX8-NEXT: s_mul_i32 s4, s4, s6155; GFX8-NEXT: s_add_i32 s4, s4, s5156; GFX8-NEXT: s_sext_i32_i16 s4, s4157; GFX8-NEXT: s_mov_b32 s3, 0xf000158; GFX8-NEXT: s_mov_b32 s2, -1159; GFX8-NEXT: v_mov_b32_e32 v0, s4160; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0161; GFX8-NEXT: s_endpgm162entry:163 %0 = mul i16 %a, %b164 %1 = add i16 %0, %c165 %2 = sext i16 %1 to i32166 store i32 %2, ptr addrspace(1) %out167 ret void168}169 170; FIXME: Need to handle non-uniform case for function below (load without gep).171; The result must be sign-extended172define amdgpu_kernel void @i8_mad24(ptr addrspace(1) %out, i8 %a, i8 %b, i8 %c) {173; EG-LABEL: i8_mad24:174; EG: ; %bb.0: ; %entry175; EG-NEXT: ALU 0, @12, KC0[], KC1[]176; EG-NEXT: TEX 2 @6177; EG-NEXT: ALU 4, @13, KC0[CB0:0-32], KC1[]178; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1179; EG-NEXT: CF_END180; EG-NEXT: PAD181; EG-NEXT: Fetch clause starting at 6:182; EG-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3183; EG-NEXT: VTX_READ_8 T2.X, T0.X, 41, #3184; EG-NEXT: VTX_READ_8 T0.X, T0.X, 42, #3185; EG-NEXT: ALU clause starting at 12:186; EG-NEXT: MOV * T0.X, 0.0,187; EG-NEXT: ALU clause starting at 13:188; EG-NEXT: MULLO_INT * T0.Y, T1.X, T2.X,189; EG-NEXT: ADD_INT * T0.W, PS, T0.X,190; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x,191; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,192; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)193;194; CM-LABEL: i8_mad24:195; CM: ; %bb.0: ; %entry196; CM-NEXT: ALU 0, @12, KC0[], KC1[]197; CM-NEXT: TEX 2 @6198; CM-NEXT: ALU 8, @13, KC0[CB0:0-32], KC1[]199; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X200; CM-NEXT: CF_END201; CM-NEXT: PAD202; CM-NEXT: Fetch clause starting at 6:203; CM-NEXT: VTX_READ_8 T1.X, T0.X, 40, #3204; CM-NEXT: VTX_READ_8 T2.X, T0.X, 41, #3205; CM-NEXT: VTX_READ_8 T0.X, T0.X, 42, #3206; CM-NEXT: ALU clause starting at 12:207; CM-NEXT: MOV * T0.X, 0.0,208; CM-NEXT: ALU clause starting at 13:209; CM-NEXT: MULLO_INT T0.X (MASKED), T1.X, T2.X,210; CM-NEXT: MULLO_INT T0.Y, T1.X, T2.X,211; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.X, T2.X,212; CM-NEXT: MULLO_INT * T0.W (MASKED), T1.X, T2.X,213; CM-NEXT: ADD_INT * T0.W, PV.Y, T0.X,214; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x,215; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)216; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,217; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)218;219; GCN-LABEL: i8_mad24:220; GCN: ; %bb.0: ; %entry221; GCN-NEXT: s_load_dword s2, s[4:5], 0xb222; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9223; GCN-NEXT: s_mov_b32 s3, 0xf000224; GCN-NEXT: s_waitcnt lgkmcnt(0)225; GCN-NEXT: s_lshr_b32 s4, s2, 8226; GCN-NEXT: s_lshr_b32 s5, s2, 16227; GCN-NEXT: s_mul_i32 s2, s2, s4228; GCN-NEXT: s_add_i32 s2, s2, s5229; GCN-NEXT: s_sext_i32_i8 s4, s2230; GCN-NEXT: s_mov_b32 s2, -1231; GCN-NEXT: v_mov_b32_e32 v0, s4232; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0233; GCN-NEXT: s_endpgm234;235; GFX8-LABEL: i8_mad24:236; GFX8: ; %bb.0: ; %entry237; GFX8-NEXT: s_load_dword s6, s[4:5], 0x2c238; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24239; GFX8-NEXT: s_mov_b32 s3, 0xf000240; GFX8-NEXT: s_mov_b32 s2, -1241; GFX8-NEXT: s_waitcnt lgkmcnt(0)242; GFX8-NEXT: s_lshr_b32 s4, s6, 8243; GFX8-NEXT: s_lshr_b32 s5, s6, 16244; GFX8-NEXT: s_mul_i32 s4, s6, s4245; GFX8-NEXT: s_add_i32 s4, s4, s5246; GFX8-NEXT: s_sext_i32_i8 s4, s4247; GFX8-NEXT: v_mov_b32_e32 v0, s4248; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0249; GFX8-NEXT: s_endpgm250entry:251 %0 = mul i8 %a, %b252 %1 = add i8 %0, %c253 %2 = sext i8 %1 to i32254 store i32 %2, ptr addrspace(1) %out255 ret void256}257 258; This tests for a bug where the mad_u24 pattern matcher would call259; SimplifyDemandedBits on the first operand of the mul instruction260; assuming that the pattern would be matched to a 24-bit mad. This261; led to some instructions being incorrectly erased when the entire262; 24-bit mad pattern wasn't being matched.263 264; Check that the select instruction is not deleted.265define amdgpu_kernel void @i24_i32_i32_mad(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {266; EG-LABEL: i24_i32_i32_mad:267; EG: ; %bb.0: ; %entry268; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]269; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1270; EG-NEXT: CF_END271; EG-NEXT: PAD272; EG-NEXT: ALU clause starting at 4:273; EG-NEXT: ASHR * T0.W, KC0[2].Z, literal.x,274; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)275; EG-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W,276; EG-NEXT: 34(4.764415e-44), 0(0.000000e+00)277; EG-NEXT: MULLO_INT * T0.X, PV.W, KC0[3].X,278; EG-NEXT: ADD_INT T0.X, PS, KC0[3].Y,279; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,280; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)281;282; CM-LABEL: i24_i32_i32_mad:283; CM: ; %bb.0: ; %entry284; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]285; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X286; CM-NEXT: CF_END287; CM-NEXT: PAD288; CM-NEXT: ALU clause starting at 4:289; CM-NEXT: ASHR * T0.W, KC0[2].Z, literal.x,290; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)291; CM-NEXT: CNDE_INT * T0.W, KC0[3].X, literal.x, PV.W,292; CM-NEXT: 34(4.764415e-44), 0(0.000000e+00)293; CM-NEXT: MULLO_INT T0.X, T0.W, KC0[3].X,294; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, KC0[3].X,295; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, KC0[3].X,296; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, KC0[3].X,297; CM-NEXT: ADD_INT * T0.X, PV.X, KC0[3].Y,298; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,299; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)300;301; GCN-LABEL: i24_i32_i32_mad:302; GCN: ; %bb.0: ; %entry303; GCN-NEXT: s_load_dword s2, s[4:5], 0xb304; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd305; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9306; GCN-NEXT: s_mov_b32 s3, 0xf000307; GCN-NEXT: s_waitcnt lgkmcnt(0)308; GCN-NEXT: s_ashr_i32 s2, s2, 8309; GCN-NEXT: s_cmp_lg_u32 s6, 0310; GCN-NEXT: s_cselect_b32 s2, s2, 34311; GCN-NEXT: s_mul_i32 s2, s2, s6312; GCN-NEXT: s_add_i32 s4, s2, s7313; GCN-NEXT: s_mov_b32 s2, -1314; GCN-NEXT: v_mov_b32_e32 v0, s4315; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0316; GCN-NEXT: s_endpgm317;318; GFX8-LABEL: i24_i32_i32_mad:319; GFX8: ; %bb.0: ; %entry320; GFX8-NEXT: s_load_dword s8, s[4:5], 0x2c321; GFX8-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34322; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24323; GFX8-NEXT: s_mov_b32 s3, 0xf000324; GFX8-NEXT: s_mov_b32 s2, -1325; GFX8-NEXT: s_waitcnt lgkmcnt(0)326; GFX8-NEXT: s_ashr_i32 s4, s8, 8327; GFX8-NEXT: s_cmp_lg_u32 s6, 0328; GFX8-NEXT: s_cselect_b32 s4, s4, 34329; GFX8-NEXT: s_mul_i32 s4, s4, s6330; GFX8-NEXT: s_add_i32 s4, s4, s7331; GFX8-NEXT: v_mov_b32_e32 v0, s4332; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0333; GFX8-NEXT: s_endpgm334entry:335 %0 = ashr i32 %a, 8336 %1 = icmp ne i32 %c, 0337 %2 = select i1 %1, i32 %0, i32 34338 %3 = mul i32 %2, %c339 %4 = add i32 %3, %d340 store i32 %4, ptr addrspace(1) %out341 ret void342}343 344define amdgpu_kernel void @extra_and(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) {345; EG-LABEL: extra_and:346; EG: ; %bb.0: ; %bb347; EG-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]348; EG-NEXT: LOOP_START_DX10 @7349; EG-NEXT: ALU_PUSH_BEFORE 12, @16, KC0[], KC1[]350; EG-NEXT: JUMP @6 POP:1351; EG-NEXT: LOOP_BREAK @6352; EG-NEXT: POP @6 POP:1353; EG-NEXT: END_LOOP @2354; EG-NEXT: ALU 1, @29, KC0[], KC1[]355; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1356; EG-NEXT: CF_END357; EG-NEXT: ALU clause starting at 10:358; EG-NEXT: MOV * T1.W, literal.x,359; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)360; EG-NEXT: MOV * T3.W, PV.W,361; EG-NEXT: MOV T0.Z, KC0[2].Y,362; EG-NEXT: MOV T0.W, KC0[2].Z,363; EG-NEXT: MOV * T2.W, KC0[2].W,364; EG-NEXT: ALU clause starting at 16:365; EG-NEXT: AND_INT T1.W, T1.W, literal.x,366; EG-NEXT: AND_INT * T4.W, T3.W, literal.x,367; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)368; EG-NEXT: AND_INT T3.W, T3.W, literal.x,369; EG-NEXT: MULLO_INT * T0.X, PS, PV.W,370; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)371; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W,372; EG-NEXT: ADD_INT T3.W, T2.W, PS,373; EG-NEXT: ADD_INT * T1.W, T0.W, T0.X,374; EG-NEXT: ADD_INT * T0.X, PS, PV.W,375; EG-NEXT: SETNE_INT * T4.W, PV.X, literal.x,376; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)377; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,378; EG-NEXT: ALU clause starting at 29:379; EG-NEXT: LSHR * T1.X, T0.Z, literal.x,380; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)381;382; CM-LABEL: extra_and:383; CM: ; %bb.0: ; %bb384; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]385; CM-NEXT: LOOP_START_DX10 @7386; CM-NEXT: ALU_PUSH_BEFORE 17, @16, KC0[], KC1[]387; CM-NEXT: JUMP @6 POP:1388; CM-NEXT: LOOP_BREAK @6389; CM-NEXT: POP @6 POP:1390; CM-NEXT: END_LOOP @2391; CM-NEXT: ALU 1, @34, KC0[], KC1[]392; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X393; CM-NEXT: CF_END394; CM-NEXT: ALU clause starting at 10:395; CM-NEXT: MOV * T0.W, literal.x,396; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)397; CM-NEXT: MOV * T1.Z, PV.W,398; CM-NEXT: MOV T0.Y, KC0[2].Y,399; CM-NEXT: MOV T0.Z, KC0[2].Z,400; CM-NEXT: MOV * T1.W, KC0[2].W,401; CM-NEXT: ALU clause starting at 16:402; CM-NEXT: AND_INT T1.Y, T1.Z, literal.x,403; CM-NEXT: AND_INT T2.Z, T0.W, literal.x,404; CM-NEXT: AND_INT * T0.W, T1.Z, literal.x,405; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)406; CM-NEXT: MULLO_INT T0.X, T0.W, T2.Z,407; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T2.Z,408; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T2.Z,409; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T2.Z,410; CM-NEXT: MULLO_INT T0.X (MASKED), T1.Y, T2.Z,411; CM-NEXT: MULLO_INT T0.Y (MASKED), T1.Y, T2.Z,412; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.Y, T2.Z,413; CM-NEXT: MULLO_INT * T0.W, T1.Y, T2.Z,414; CM-NEXT: ADD_INT T1.Z, T1.W, PV.W,415; CM-NEXT: ADD_INT * T0.W, T0.Z, T0.X,416; CM-NEXT: ADD_INT * T0.X, PV.W, PV.Z,417; CM-NEXT: SETNE_INT * T2.W, PV.X, literal.x,418; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)419; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,420; CM-NEXT: ALU clause starting at 34:421; CM-NEXT: LSHR * T1.X, T0.Y, literal.x,422; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)423;424; GCN-LABEL: extra_and:425; GCN: ; %bb.0: ; %bb426; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb427; GCN-NEXT: s_mov_b32 s2, 0428; GCN-NEXT: s_mov_b32 s6, 0429; GCN-NEXT: .LBB4_1: ; %bb4430; GCN-NEXT: ; =>This Inner Loop Header: Depth=1431; GCN-NEXT: s_and_b32 s3, s6, 0xffffff432; GCN-NEXT: s_and_b32 s6, s6, 0xffffff433; GCN-NEXT: s_and_b32 s2, s2, 0xffffff434; GCN-NEXT: s_mul_i32 s3, s3, s2435; GCN-NEXT: s_mul_i32 s6, s6, s2436; GCN-NEXT: s_waitcnt lgkmcnt(0)437; GCN-NEXT: s_add_i32 s2, s0, s3438; GCN-NEXT: s_add_i32 s6, s1, s6439; GCN-NEXT: s_add_i32 s3, s2, s6440; GCN-NEXT: s_cmp_lg_u32 s3, 8441; GCN-NEXT: s_cbranch_scc1 .LBB4_1442; GCN-NEXT: ; %bb.2: ; %bb18443; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9444; GCN-NEXT: s_mov_b32 s7, 0xf000445; GCN-NEXT: s_mov_b32 s6, -1446; GCN-NEXT: v_mov_b32_e32 v0, s3447; GCN-NEXT: s_waitcnt lgkmcnt(0)448; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0449; GCN-NEXT: s_endpgm450;451; GFX8-LABEL: extra_and:452; GFX8: ; %bb.0: ; %bb453; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c454; GFX8-NEXT: s_mov_b32 s2, 0455; GFX8-NEXT: s_mov_b32 s6, 0456; GFX8-NEXT: .LBB4_1: ; %bb4457; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1458; GFX8-NEXT: s_and_b32 s3, s6, 0xffffff459; GFX8-NEXT: s_and_b32 s6, s6, 0xffffff460; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff461; GFX8-NEXT: s_mul_i32 s3, s3, s2462; GFX8-NEXT: s_mul_i32 s6, s6, s2463; GFX8-NEXT: s_waitcnt lgkmcnt(0)464; GFX8-NEXT: s_add_i32 s2, s0, s3465; GFX8-NEXT: s_add_i32 s6, s1, s6466; GFX8-NEXT: s_add_i32 s3, s2, s6467; GFX8-NEXT: s_cmp_lg_u32 s3, 8468; GFX8-NEXT: s_cbranch_scc1 .LBB4_1469; GFX8-NEXT: ; %bb.2: ; %bb18470; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24471; GFX8-NEXT: s_mov_b32 s7, 0xf000472; GFX8-NEXT: s_mov_b32 s6, -1473; GFX8-NEXT: v_mov_b32_e32 v0, s3474; GFX8-NEXT: s_waitcnt lgkmcnt(0)475; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0476; GFX8-NEXT: s_endpgm477bb:478 br label %bb4479 480bb4: ; preds = %bb4, %bb481 %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]482 %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]483 %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]484 %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]485 %tmp8 = and i32 %tmp7, 16777215486 %tmp9 = and i32 %tmp6, 16777215487 %tmp10 = and i32 %tmp5, 16777215488 %tmp11 = and i32 %tmp, 16777215489 %tmp12 = mul i32 %tmp8, %tmp11490 %tmp13 = add i32 %arg2, %tmp12491 %tmp14 = mul i32 %tmp9, %tmp11492 %tmp15 = add i32 %arg3, %tmp14493 %tmp16 = add nuw nsw i32 %tmp13, %tmp15494 %tmp17 = icmp eq i32 %tmp16, 8495 br i1 %tmp17, label %bb18, label %bb4496 497bb18: ; preds = %bb4498 store i32 %tmp16, ptr addrspace(1) %arg499 ret void500}501 502define amdgpu_kernel void @dont_remove_shift(ptr addrspace(1) %arg, i32 %arg2, i32 %arg3) {503; EG-LABEL: dont_remove_shift:504; EG: ; %bb.0: ; %bb505; EG-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]506; EG-NEXT: LOOP_START_DX10 @7507; EG-NEXT: ALU_PUSH_BEFORE 12, @16, KC0[], KC1[]508; EG-NEXT: JUMP @6 POP:1509; EG-NEXT: LOOP_BREAK @6510; EG-NEXT: POP @6 POP:1511; EG-NEXT: END_LOOP @2512; EG-NEXT: ALU 1, @29, KC0[], KC1[]513; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1514; EG-NEXT: CF_END515; EG-NEXT: ALU clause starting at 10:516; EG-NEXT: MOV * T1.W, literal.x,517; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)518; EG-NEXT: MOV * T3.W, PV.W,519; EG-NEXT: MOV T0.Z, KC0[2].Y,520; EG-NEXT: MOV T0.W, KC0[2].Z,521; EG-NEXT: MOV * T2.W, KC0[2].W,522; EG-NEXT: ALU clause starting at 16:523; EG-NEXT: LSHR T1.W, T1.W, literal.x,524; EG-NEXT: LSHR * T4.W, T3.W, literal.x,525; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)526; EG-NEXT: LSHR T3.W, T3.W, literal.x,527; EG-NEXT: MULLO_INT * T0.X, PS, PV.W,528; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)529; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W,530; EG-NEXT: ADD_INT T3.W, T2.W, PS,531; EG-NEXT: ADD_INT * T1.W, T0.W, T0.X,532; EG-NEXT: ADD_INT * T0.X, PS, PV.W,533; EG-NEXT: SETNE_INT * T4.W, PV.X, literal.x,534; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)535; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,536; EG-NEXT: ALU clause starting at 29:537; EG-NEXT: LSHR * T1.X, T0.Z, literal.x,538; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)539;540; CM-LABEL: dont_remove_shift:541; CM: ; %bb.0: ; %bb542; CM-NEXT: ALU 5, @10, KC0[CB0:0-32], KC1[]543; CM-NEXT: LOOP_START_DX10 @7544; CM-NEXT: ALU_PUSH_BEFORE 17, @16, KC0[], KC1[]545; CM-NEXT: JUMP @6 POP:1546; CM-NEXT: LOOP_BREAK @6547; CM-NEXT: POP @6 POP:1548; CM-NEXT: END_LOOP @2549; CM-NEXT: ALU 1, @34, KC0[], KC1[]550; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X551; CM-NEXT: CF_END552; CM-NEXT: ALU clause starting at 10:553; CM-NEXT: MOV * T0.W, literal.x,554; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)555; CM-NEXT: MOV * T1.Z, PV.W,556; CM-NEXT: MOV T0.Y, KC0[2].Y,557; CM-NEXT: MOV T0.Z, KC0[2].Z,558; CM-NEXT: MOV * T1.W, KC0[2].W,559; CM-NEXT: ALU clause starting at 16:560; CM-NEXT: LSHR T1.Y, T1.Z, literal.x,561; CM-NEXT: LSHR T2.Z, T0.W, literal.x,562; CM-NEXT: LSHR * T0.W, T1.Z, literal.x,563; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)564; CM-NEXT: MULLO_INT T0.X, T0.W, T2.Z,565; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T2.Z,566; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T2.Z,567; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T2.Z,568; CM-NEXT: MULLO_INT T0.X (MASKED), T1.Y, T2.Z,569; CM-NEXT: MULLO_INT T0.Y (MASKED), T1.Y, T2.Z,570; CM-NEXT: MULLO_INT T0.Z (MASKED), T1.Y, T2.Z,571; CM-NEXT: MULLO_INT * T0.W, T1.Y, T2.Z,572; CM-NEXT: ADD_INT T1.Z, T1.W, PV.W,573; CM-NEXT: ADD_INT * T0.W, T0.Z, T0.X,574; CM-NEXT: ADD_INT * T0.X, PV.W, PV.Z,575; CM-NEXT: SETNE_INT * T2.W, PV.X, literal.x,576; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)577; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,578; CM-NEXT: ALU clause starting at 34:579; CM-NEXT: LSHR * T1.X, T0.Y, literal.x,580; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)581;582; GCN-LABEL: dont_remove_shift:583; GCN: ; %bb.0: ; %bb584; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb585; GCN-NEXT: s_mov_b32 s2, 0586; GCN-NEXT: s_mov_b32 s6, 0587; GCN-NEXT: .LBB5_1: ; %bb4588; GCN-NEXT: ; =>This Inner Loop Header: Depth=1589; GCN-NEXT: s_lshr_b32 s3, s6, 8590; GCN-NEXT: s_lshr_b32 s6, s6, 8591; GCN-NEXT: s_lshr_b32 s2, s2, 8592; GCN-NEXT: s_mul_i32 s3, s3, s2593; GCN-NEXT: s_mul_i32 s6, s6, s2594; GCN-NEXT: s_waitcnt lgkmcnt(0)595; GCN-NEXT: s_add_i32 s2, s0, s3596; GCN-NEXT: s_add_i32 s6, s1, s6597; GCN-NEXT: s_add_i32 s3, s2, s6598; GCN-NEXT: s_cmp_lg_u32 s3, 8599; GCN-NEXT: s_cbranch_scc1 .LBB5_1600; GCN-NEXT: ; %bb.2: ; %bb18601; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9602; GCN-NEXT: s_mov_b32 s7, 0xf000603; GCN-NEXT: s_mov_b32 s6, -1604; GCN-NEXT: v_mov_b32_e32 v0, s3605; GCN-NEXT: s_waitcnt lgkmcnt(0)606; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0607; GCN-NEXT: s_endpgm608;609; GFX8-LABEL: dont_remove_shift:610; GFX8: ; %bb.0: ; %bb611; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c612; GFX8-NEXT: s_mov_b32 s2, 0613; GFX8-NEXT: s_mov_b32 s6, 0614; GFX8-NEXT: .LBB5_1: ; %bb4615; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1616; GFX8-NEXT: s_lshr_b32 s3, s6, 8617; GFX8-NEXT: s_lshr_b32 s6, s6, 8618; GFX8-NEXT: s_lshr_b32 s2, s2, 8619; GFX8-NEXT: s_mul_i32 s3, s3, s2620; GFX8-NEXT: s_mul_i32 s6, s6, s2621; GFX8-NEXT: s_waitcnt lgkmcnt(0)622; GFX8-NEXT: s_add_i32 s2, s0, s3623; GFX8-NEXT: s_add_i32 s6, s1, s6624; GFX8-NEXT: s_add_i32 s3, s2, s6625; GFX8-NEXT: s_cmp_lg_u32 s3, 8626; GFX8-NEXT: s_cbranch_scc1 .LBB5_1627; GFX8-NEXT: ; %bb.2: ; %bb18628; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24629; GFX8-NEXT: s_mov_b32 s7, 0xf000630; GFX8-NEXT: s_mov_b32 s6, -1631; GFX8-NEXT: v_mov_b32_e32 v0, s3632; GFX8-NEXT: s_waitcnt lgkmcnt(0)633; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0634; GFX8-NEXT: s_endpgm635bb:636 br label %bb4637 638bb4: ; preds = %bb4, %bb639 %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]640 %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]641 %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]642 %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]643 %tmp8 = lshr i32 %tmp7, 8644 %tmp9 = lshr i32 %tmp6, 8645 %tmp10 = lshr i32 %tmp5, 8646 %tmp11 = lshr i32 %tmp, 8647 %tmp12 = mul i32 %tmp8, %tmp11648 %tmp13 = add i32 %arg2, %tmp12649 %tmp14 = mul i32 %tmp9, %tmp11650 %tmp15 = add i32 %arg3, %tmp14651 %tmp16 = add nuw nsw i32 %tmp13, %tmp15652 %tmp17 = icmp eq i32 %tmp16, 8653 br i1 %tmp17, label %bb18, label %bb4654 655bb18: ; preds = %bb4656 store i32 %tmp16, ptr addrspace(1) %arg657 ret void658}659 660define amdgpu_kernel void @i8_mad_sat_16(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %in2, ptr addrspace(5) %idx) {661; EG-LABEL: i8_mad_sat_16:662; EG: ; %bb.0: ; %entry663; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[]664; EG-NEXT: TEX 0 @8665; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[]666; EG-NEXT: TEX 1 @10667; EG-NEXT: ALU 24, @21, KC0[CB0:0-32], KC1[]668; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X669; EG-NEXT: CF_END670; EG-NEXT: PAD671; EG-NEXT: Fetch clause starting at 8:672; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1673; EG-NEXT: Fetch clause starting at 10:674; EG-NEXT: VTX_READ_8 T3.X, T3.X, 0, #1675; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1676; EG-NEXT: ALU clause starting at 14:677; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x,678; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)679; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W,680; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+,681; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X,682; EG-NEXT: ALU clause starting at 19:683; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X,684; EG-NEXT: ADD_INT * T3.X, KC0[3].X, T0.X,685; EG-NEXT: ALU clause starting at 21:686; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,687; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212688; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)689; EG-NEXT: BFE_INT T1.W, T3.X, 0.0, literal.x,690; EG-NEXT: MULLO_INT * T0.Y, PV.Z, PV.W,691; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)692; EG-NEXT: ADD_INT * T0.W, PS, PV.W,693; EG-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x,694; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)695; EG-NEXT: MAX_INT T0.W, PV.W, literal.x,696; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, T0.X,697; EG-NEXT: -128(nan), 0(0.000000e+00)698; EG-NEXT: AND_INT T2.W, PS, literal.x,699; EG-NEXT: MIN_INT * T0.W, PV.W, literal.y,700; EG-NEXT: 3(4.203895e-45), 127(1.779649e-43)701; EG-NEXT: AND_INT T0.W, PS, literal.x,702; EG-NEXT: LSHL * T2.W, PV.W, literal.y,703; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)704; EG-NEXT: LSHL T0.X, PV.W, PS,705; EG-NEXT: LSHL * T0.W, literal.x, PS,706; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)707; EG-NEXT: MOV T0.Y, 0.0,708; EG-NEXT: MOV * T0.Z, 0.0,709; EG-NEXT: LSHR * T1.X, T1.W, literal.x,710; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)711;712; CM-LABEL: i8_mad_sat_16:713; CM: ; %bb.0: ; %entry714; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[]715; CM-NEXT: TEX 0 @8716; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[]717; CM-NEXT: TEX 1 @10718; CM-NEXT: ALU 26, @21, KC0[CB0:0-32], KC1[]719; CM-NEXT: MEM_RAT MSKOR T1.XW, T0.X720; CM-NEXT: CF_END721; CM-NEXT: PAD722; CM-NEXT: Fetch clause starting at 8:723; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1724; CM-NEXT: Fetch clause starting at 10:725; CM-NEXT: VTX_READ_8 T3.X, T3.X, 0, #1726; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1727; CM-NEXT: ALU clause starting at 14:728; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x,729; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)730; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W,731; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+,732; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X,733; CM-NEXT: ALU clause starting at 19:734; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X,735; CM-NEXT: ADD_INT * T3.X, KC0[2].Z, T0.X,736; CM-NEXT: ALU clause starting at 21:737; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x,738; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212739; CM-NEXT: BFE_INT * T0.W, T3.X, 0.0, literal.x, BS:VEC_201740; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)741; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Z, T0.W,742; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.Z, T0.W,743; CM-NEXT: MULLO_INT T0.Z, T0.Z, T0.W,744; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Z, T0.W,745; CM-NEXT: ADD_INT * T0.W, PV.Z, T0.Y,746; CM-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x,747; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)748; CM-NEXT: MAX_INT T0.Z, PV.W, literal.x,749; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.X,750; CM-NEXT: -128(nan), 0(0.000000e+00)751; CM-NEXT: AND_INT T1.Z, PV.W, literal.x,752; CM-NEXT: MIN_INT * T1.W, PV.Z, literal.y,753; CM-NEXT: 3(4.203895e-45), 127(1.779649e-43)754; CM-NEXT: AND_INT T0.Z, PV.W, literal.x,755; CM-NEXT: LSHL * T1.W, PV.Z, literal.y,756; CM-NEXT: 255(3.573311e-43), 3(4.203895e-45)757; CM-NEXT: LSHL T1.X, PV.Z, PV.W,758; CM-NEXT: LSHL * T1.W, literal.x, PV.W,759; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)760; CM-NEXT: MOV T1.Y, 0.0,761; CM-NEXT: MOV * T1.Z, 0.0,762; CM-NEXT: LSHR * T0.X, T0.W, literal.x,763; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)764;765; GCN-LABEL: i8_mad_sat_16:766; GCN: ; %bb.0: ; %entry767; GCN-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0768; GCN-NEXT: s_mov_b32 s21, SCRATCH_RSRC_DWORD1769; GCN-NEXT: s_mov_b32 s22, -1770; GCN-NEXT: s_mov_b32 s23, 0xe8f000771; GCN-NEXT: s_add_u32 s20, s20, s11772; GCN-NEXT: s_addc_u32 s21, s21, 0773; GCN-NEXT: s_load_dword s8, s[4:5], 0x11774; GCN-NEXT: s_waitcnt lgkmcnt(0)775; GCN-NEXT: s_add_i32 s9, s8, 4776; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9777; GCN-NEXT: v_mov_b32_e32 v0, s8778; GCN-NEXT: v_mov_b32_e32 v1, s9779; GCN-NEXT: buffer_load_dword v1, v1, s[20:23], 0 offen780; GCN-NEXT: buffer_load_dword v0, v0, s[20:23], 0 offen781; GCN-NEXT: s_mov_b32 s11, 0xf000782; GCN-NEXT: s_mov_b32 s10, 0783; GCN-NEXT: s_mov_b64 s[14:15], s[10:11]784; GCN-NEXT: s_mov_b64 s[18:19], s[10:11]785; GCN-NEXT: s_waitcnt lgkmcnt(0)786; GCN-NEXT: s_mov_b64 s[8:9], s[2:3]787; GCN-NEXT: s_mov_b64 s[12:13], s[4:5]788; GCN-NEXT: s_mov_b64 s[16:17], s[6:7]789; GCN-NEXT: s_waitcnt vmcnt(0)790; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr64791; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[8:11], 0 addr64792; GCN-NEXT: buffer_load_sbyte v4, v[0:1], s[16:19], 0 addr64793; GCN-NEXT: s_movk_i32 s2, 0xff80794; GCN-NEXT: s_waitcnt vmcnt(2)795; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2796; GCN-NEXT: s_waitcnt vmcnt(1)797; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3798; GCN-NEXT: s_waitcnt vmcnt(0)799; GCN-NEXT: v_mad_u32_u24 v2, v2, v3, v4800; GCN-NEXT: v_bfe_i32 v2, v2, 0, 16801; GCN-NEXT: v_mov_b32_e32 v3, 0x7f802; GCN-NEXT: v_med3_i32 v2, v2, s2, v3803; GCN-NEXT: s_mov_b64 s[2:3], s[10:11]804; GCN-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64805; GCN-NEXT: s_endpgm806;807; SI-LABEL: i8_mad_sat_16:808; SI: ; %bb.0: ; %entry809; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD0810; SI-NEXT: s_load_dword s0, s[4:5], 0x44811; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD1812; SI-NEXT: s_mov_b32 s90, -1813; SI-NEXT: s_mov_b32 s91, 0xe80000814; SI-NEXT: s_add_u32 s88, s88, s11815; SI-NEXT: s_addc_u32 s89, s89, 0816; SI-NEXT: s_waitcnt lgkmcnt(0)817; SI-NEXT: s_add_i32 s1, s0, 4818; SI-NEXT: v_mov_b32_e32 v0, s0819; SI-NEXT: buffer_load_dword v6, v0, s[88:91], 0 offen820; SI-NEXT: v_mov_b32_e32 v0, s1821; SI-NEXT: buffer_load_dword v7, v0, s[88:91], 0 offen822; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24823; SI-NEXT: s_waitcnt lgkmcnt(0)824; SI-NEXT: v_mov_b32_e32 v1, s3825; SI-NEXT: v_mov_b32_e32 v3, s5826; SI-NEXT: v_mov_b32_e32 v5, s7827; SI-NEXT: s_waitcnt vmcnt(1)828; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v6829; SI-NEXT: s_waitcnt vmcnt(0)830; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc831; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v6832; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc833; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v6834; SI-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc835; SI-NEXT: flat_load_sbyte v0, v[0:1]836; SI-NEXT: flat_load_sbyte v1, v[2:3]837; SI-NEXT: flat_load_sbyte v2, v[4:5]838; SI-NEXT: v_mov_b32_e32 v3, s1839; SI-NEXT: s_waitcnt vmcnt(0)840; SI-NEXT: v_mad_u16 v0, v1, v0, v2841; SI-NEXT: v_max_i16_e32 v0, 0xff80, v0842; SI-NEXT: v_min_i16_e32 v2, 0x7f, v0843; SI-NEXT: v_add_u32_e32 v0, vcc, s0, v6844; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v7, vcc845; SI-NEXT: flat_store_byte v[0:1], v2846; SI-NEXT: s_endpgm847;848; VI-LABEL: i8_mad_sat_16:849; VI: ; %bb.0: ; %entry850; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0851; VI-NEXT: s_load_dword s0, s[4:5], 0x44852; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1853; VI-NEXT: s_mov_b32 s14, -1854; VI-NEXT: s_mov_b32 s15, 0xe80000855; VI-NEXT: s_add_u32 s12, s12, s11856; VI-NEXT: s_addc_u32 s13, s13, 0857; VI-NEXT: s_waitcnt lgkmcnt(0)858; VI-NEXT: s_add_i32 s1, s0, 4859; VI-NEXT: v_mov_b32_e32 v0, s0860; VI-NEXT: buffer_load_dword v6, v0, s[12:15], 0 offen861; VI-NEXT: v_mov_b32_e32 v0, s1862; VI-NEXT: buffer_load_dword v7, v0, s[12:15], 0 offen863; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24864; VI-NEXT: s_waitcnt lgkmcnt(0)865; VI-NEXT: v_mov_b32_e32 v1, s3866; VI-NEXT: v_mov_b32_e32 v3, s5867; VI-NEXT: v_mov_b32_e32 v5, s7868; VI-NEXT: s_waitcnt vmcnt(1)869; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v6870; VI-NEXT: s_waitcnt vmcnt(0)871; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc872; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v6873; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc874; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v6875; VI-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc876; VI-NEXT: flat_load_sbyte v0, v[0:1]877; VI-NEXT: flat_load_sbyte v1, v[2:3]878; VI-NEXT: flat_load_sbyte v2, v[4:5]879; VI-NEXT: v_mov_b32_e32 v3, s1880; VI-NEXT: s_waitcnt vmcnt(0)881; VI-NEXT: v_mad_u16 v0, v1, v0, v2882; VI-NEXT: v_max_i16_e32 v0, 0xff80, v0883; VI-NEXT: v_min_i16_e32 v2, 0x7f, v0884; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v6885; VI-NEXT: v_addc_u32_e32 v1, vcc, v3, v7, vcc886; VI-NEXT: flat_store_byte v[0:1], v2887; VI-NEXT: s_endpgm888entry:889 %retval.0.i = load i64, ptr addrspace(5) %idx890 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 %retval.0.i891 %arrayidx2 = getelementptr inbounds i8, ptr addrspace(1) %in1, i64 %retval.0.i892 %arrayidx4 = getelementptr inbounds i8, ptr addrspace(1) %in2, i64 %retval.0.i893 %l1 = load i8, ptr addrspace(1) %arrayidx, align 1894 %l2 = load i8, ptr addrspace(1) %arrayidx2, align 1895 %l3 = load i8, ptr addrspace(1) %arrayidx4, align 1896 %conv1.i = sext i8 %l1 to i16897 %conv3.i = sext i8 %l2 to i16898 %conv5.i = sext i8 %l3 to i16899 %mul.i.i.i = mul nsw i16 %conv3.i, %conv1.i900 %add.i.i = add i16 %mul.i.i.i, %conv5.i901 %c4 = icmp sgt i16 %add.i.i, -128902 %cond.i.i = select i1 %c4, i16 %add.i.i, i16 -128903 %c5 = icmp slt i16 %cond.i.i, 127904 %cond13.i.i = select i1 %c5, i16 %cond.i.i, i16 127905 %conv8.i = trunc i16 %cond13.i.i to i8906 %arrayidx7 = getelementptr inbounds i8, ptr addrspace(1) %out, i64 %retval.0.i907 store i8 %conv8.i, ptr addrspace(1) %arrayidx7, align 1908 ret void909}910 911define amdgpu_kernel void @i8_mad_32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) {912; EG-LABEL: i8_mad_32:913; EG: ; %bb.0: ; %entry914; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[]915; EG-NEXT: TEX 0 @8916; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[]917; EG-NEXT: TEX 1 @10918; EG-NEXT: ALU 9, @21, KC0[CB0:0-32], KC1[]919; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1920; EG-NEXT: CF_END921; EG-NEXT: PAD922; EG-NEXT: Fetch clause starting at 8:923; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1924; EG-NEXT: Fetch clause starting at 10:925; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1926; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1927; EG-NEXT: ALU clause starting at 14:928; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x,929; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)930; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W,931; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+,932; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X,933; EG-NEXT: ALU clause starting at 19:934; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X,935; EG-NEXT: ADD_INT * T0.X, KC0[3].X, T0.X,936; EG-NEXT: ALU clause starting at 21:937; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,938; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212939; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)940; EG-NEXT: BFE_INT T1.W, T0.X, 0.0, literal.x,941; EG-NEXT: MULLO_INT * T0.X, PV.W, PV.Z,942; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)943; EG-NEXT: ADD_INT * T0.W, PS, PV.W,944; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x,945; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,946; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)947;948; CM-LABEL: i8_mad_32:949; CM: ; %bb.0: ; %entry950; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[]951; CM-NEXT: TEX 0 @8952; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[]953; CM-NEXT: TEX 1 @10954; CM-NEXT: ALU 12, @21, KC0[CB0:0-32], KC1[]955; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X956; CM-NEXT: CF_END957; CM-NEXT: PAD958; CM-NEXT: Fetch clause starting at 8:959; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1960; CM-NEXT: Fetch clause starting at 10:961; CM-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1962; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #1963; CM-NEXT: ALU clause starting at 14:964; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x,965; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)966; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W,967; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+,968; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X,969; CM-NEXT: ALU clause starting at 19:970; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X,971; CM-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,972; CM-NEXT: ALU clause starting at 21:973; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x,974; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_212975; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_201976; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)977; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z,978; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z,979; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z,980; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z,981; CM-NEXT: ADD_INT * T0.W, PV.X, T0.Y,982; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x,983; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)984; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,985; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)986;987; GCN-LABEL: i8_mad_32:988; GCN: ; %bb.0: ; %entry989; GCN-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0990; GCN-NEXT: s_mov_b32 s25, SCRATCH_RSRC_DWORD1991; GCN-NEXT: s_mov_b32 s26, -1992; GCN-NEXT: s_mov_b32 s27, 0xe8f000993; GCN-NEXT: s_add_u32 s24, s24, s11994; GCN-NEXT: s_addc_u32 s25, s25, 0995; GCN-NEXT: s_load_dword s8, s[4:5], 0x11996; GCN-NEXT: s_waitcnt lgkmcnt(0)997; GCN-NEXT: s_add_i32 s9, s8, 4998; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9999; GCN-NEXT: v_mov_b32_e32 v0, s81000; GCN-NEXT: v_mov_b32_e32 v1, s91001; GCN-NEXT: buffer_load_dword v1, v1, s[24:27], 0 offen1002; GCN-NEXT: buffer_load_dword v0, v0, s[24:27], 0 offen1003; GCN-NEXT: s_mov_b32 s11, 0xf0001004; GCN-NEXT: s_mov_b32 s14, 01005; GCN-NEXT: s_mov_b32 s15, s111006; GCN-NEXT: s_mov_b64 s[18:19], s[14:15]1007; GCN-NEXT: s_mov_b64 s[22:23], s[14:15]1008; GCN-NEXT: s_waitcnt lgkmcnt(0)1009; GCN-NEXT: s_mov_b64 s[12:13], s[2:3]1010; GCN-NEXT: s_mov_b64 s[16:17], s[4:5]1011; GCN-NEXT: s_mov_b64 s[20:21], s[6:7]1012; GCN-NEXT: s_waitcnt vmcnt(0)1013; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr641014; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[16:19], 0 addr641015; GCN-NEXT: buffer_load_sbyte v0, v[0:1], s[20:23], 0 addr641016; GCN-NEXT: s_mov_b32 s10, -11017; GCN-NEXT: s_mov_b32 s8, s01018; GCN-NEXT: s_mov_b32 s9, s11019; GCN-NEXT: s_waitcnt vmcnt(2)1020; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v21021; GCN-NEXT: s_waitcnt vmcnt(1)1022; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v31023; GCN-NEXT: s_waitcnt vmcnt(0)1024; GCN-NEXT: v_mad_u32_u24 v0, v1, v2, v01025; GCN-NEXT: v_bfe_i32 v0, v0, 0, 161026; GCN-NEXT: buffer_store_dword v0, off, s[8:11], 01027; GCN-NEXT: s_endpgm1028;1029; SI-LABEL: i8_mad_32:1030; SI: ; %bb.0: ; %entry1031; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD01032; SI-NEXT: s_load_dword s0, s[4:5], 0x441033; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD11034; SI-NEXT: s_mov_b32 s90, -11035; SI-NEXT: s_mov_b32 s91, 0xe800001036; SI-NEXT: s_add_u32 s88, s88, s111037; SI-NEXT: s_addc_u32 s89, s89, 01038; SI-NEXT: s_waitcnt lgkmcnt(0)1039; SI-NEXT: s_add_i32 s1, s0, 41040; SI-NEXT: v_mov_b32_e32 v0, s01041; SI-NEXT: buffer_load_dword v4, v0, s[88:91], 0 offen1042; SI-NEXT: v_mov_b32_e32 v0, s11043; SI-NEXT: buffer_load_dword v5, v0, s[88:91], 0 offen1044; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x241045; SI-NEXT: s_waitcnt lgkmcnt(0)1046; SI-NEXT: v_mov_b32_e32 v1, s31047; SI-NEXT: v_mov_b32_e32 v3, s51048; SI-NEXT: v_mov_b32_e32 v6, s71049; SI-NEXT: s_mov_b32 s3, 0xf0001050; SI-NEXT: s_waitcnt vmcnt(1)1051; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v41052; SI-NEXT: s_waitcnt vmcnt(0)1053; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc1054; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v41055; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc1056; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v41057; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc1058; SI-NEXT: flat_load_sbyte v0, v[0:1]1059; SI-NEXT: flat_load_sbyte v1, v[2:3]1060; SI-NEXT: flat_load_sbyte v2, v[4:5]1061; SI-NEXT: s_mov_b32 s2, -11062; SI-NEXT: s_waitcnt vmcnt(0)1063; SI-NEXT: v_mad_u16 v0, v0, v1, v21064; SI-NEXT: v_bfe_i32 v0, v0, 0, 161065; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01066; SI-NEXT: s_endpgm1067;1068; VI-LABEL: i8_mad_32:1069; VI: ; %bb.0: ; %entry1070; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD01071; VI-NEXT: s_load_dword s0, s[4:5], 0x441072; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD11073; VI-NEXT: s_mov_b32 s14, -11074; VI-NEXT: s_mov_b32 s15, 0xe800001075; VI-NEXT: s_add_u32 s12, s12, s111076; VI-NEXT: s_addc_u32 s13, s13, 01077; VI-NEXT: s_waitcnt lgkmcnt(0)1078; VI-NEXT: s_add_i32 s1, s0, 41079; VI-NEXT: v_mov_b32_e32 v0, s01080; VI-NEXT: buffer_load_dword v4, v0, s[12:15], 0 offen1081; VI-NEXT: v_mov_b32_e32 v0, s11082; VI-NEXT: buffer_load_dword v5, v0, s[12:15], 0 offen1083; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x241084; VI-NEXT: s_waitcnt lgkmcnt(0)1085; VI-NEXT: v_mov_b32_e32 v1, s31086; VI-NEXT: v_mov_b32_e32 v3, s51087; VI-NEXT: v_mov_b32_e32 v6, s71088; VI-NEXT: s_mov_b32 s3, 0xf0001089; VI-NEXT: s_waitcnt vmcnt(1)1090; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41091; VI-NEXT: s_waitcnt vmcnt(0)1092; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc1093; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41094; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc1095; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v41096; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc1097; VI-NEXT: flat_load_sbyte v0, v[0:1]1098; VI-NEXT: flat_load_sbyte v1, v[2:3]1099; VI-NEXT: flat_load_sbyte v2, v[4:5]1100; VI-NEXT: s_mov_b32 s2, -11101; VI-NEXT: s_waitcnt vmcnt(0)1102; VI-NEXT: v_mad_u16 v0, v0, v1, v21103; VI-NEXT: v_bfe_i32 v0, v0, 0, 161104; VI-NEXT: buffer_store_dword v0, off, s[0:3], 01105; VI-NEXT: s_endpgm1106entry:1107 %retval.0.i = load i64, ptr addrspace(5) %idx1108 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i1109 %arrayidx2 = getelementptr inbounds i8, ptr addrspace(1) %b, i64 %retval.0.i1110 %arrayidx4 = getelementptr inbounds i8, ptr addrspace(1) %c, i64 %retval.0.i1111 %la = load i8, ptr addrspace(1) %arrayidx, align 11112 %lb = load i8, ptr addrspace(1) %arrayidx2, align 11113 %lc = load i8, ptr addrspace(1) %arrayidx4, align 11114 %exta = sext i8 %la to i161115 %extb = sext i8 %lb to i161116 %extc = sext i8 %lc to i161117 %mul = mul i16 %exta, %extb1118 %mad = add i16 %mul, %extc1119 %mad_ext = sext i16 %mad to i321120 store i32 %mad_ext, ptr addrspace(1) %out1121 ret void1122}1123 1124define amdgpu_kernel void @i8_mad_64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(5) %idx) {1125; EG-LABEL: i8_mad_64:1126; EG: ; %bb.0: ; %entry1127; EG-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[]1128; EG-NEXT: TEX 0 @81129; EG-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[]1130; EG-NEXT: TEX 1 @101131; EG-NEXT: ALU 11, @21, KC0[CB0:0-32], KC1[]1132; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11133; EG-NEXT: CF_END1134; EG-NEXT: PAD1135; EG-NEXT: Fetch clause starting at 8:1136; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #11137; EG-NEXT: Fetch clause starting at 10:1138; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11139; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #11140; EG-NEXT: ALU clause starting at 14:1141; EG-NEXT: LSHR * T0.W, KC0[3].Y, literal.x,1142; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1143; EG-NEXT: MOVA_INT * AR.x (MASKED), PV.W,1144; EG-NEXT: MOV * T0.X, T(0 + AR.x).X+,1145; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.X,1146; EG-NEXT: ALU clause starting at 19:1147; EG-NEXT: ADD_INT T2.X, KC0[2].Z, T0.X,1148; EG-NEXT: ADD_INT * T0.X, KC0[3].X, T0.X,1149; EG-NEXT: ALU clause starting at 21:1150; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,1151; EG-NEXT: BFE_INT * T0.W, T2.X, 0.0, literal.x, BS:VEC_120/SCL_2121152; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)1153; EG-NEXT: BFE_INT T1.W, T0.X, 0.0, literal.x,1154; EG-NEXT: MULLO_INT * T0.X, PV.W, PV.Z,1155; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)1156; EG-NEXT: ADD_INT * T0.W, PS, PV.W,1157; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, literal.x,1158; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1159; EG-NEXT: 16(2.242078e-44), 2(2.802597e-45)1160; EG-NEXT: ASHR * T0.Y, PV.X, literal.x,1161; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)1162;1163; CM-LABEL: i8_mad_64:1164; CM: ; %bb.0: ; %entry1165; CM-NEXT: ALU 4, @14, KC0[CB0:0-32], KC1[]1166; CM-NEXT: TEX 0 @81167; CM-NEXT: ALU 1, @19, KC0[CB0:0-32], KC1[]1168; CM-NEXT: TEX 1 @101169; CM-NEXT: ALU 13, @21, KC0[CB0:0-32], KC1[]1170; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1171; CM-NEXT: CF_END1172; CM-NEXT: PAD1173; CM-NEXT: Fetch clause starting at 8:1174; CM-NEXT: VTX_READ_8 T1.X, T1.X, 0, #11175; CM-NEXT: Fetch clause starting at 10:1176; CM-NEXT: VTX_READ_8 T0.X, T0.X, 0, #11177; CM-NEXT: VTX_READ_8 T2.X, T2.X, 0, #11178; CM-NEXT: ALU clause starting at 14:1179; CM-NEXT: LSHR * T0.W, KC0[3].Y, literal.x,1180; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1181; CM-NEXT: MOVA_INT * AR.x (MASKED), PV.W,1182; CM-NEXT: MOV * T0.X, T(0 + AR.x).X+,1183; CM-NEXT: ADD_INT * T1.X, KC0[3].X, PV.X,1184; CM-NEXT: ALU clause starting at 19:1185; CM-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X,1186; CM-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,1187; CM-NEXT: ALU clause starting at 21:1188; CM-NEXT: BFE_INT T0.Y, T1.X, 0.0, literal.x,1189; CM-NEXT: BFE_INT T0.Z, T2.X, 0.0, literal.x, BS:VEC_120/SCL_2121190; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_2011191; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)1192; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z,1193; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z,1194; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z,1195; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z,1196; CM-NEXT: ADD_INT * T0.W, PV.X, T0.Y,1197; CM-NEXT: BFE_INT * T0.X, PV.W, 0.0, literal.x,1198; CM-NEXT: 16(2.242078e-44), 0(0.000000e+00)1199; CM-NEXT: LSHR T1.X, KC0[2].Y, literal.x,1200; CM-NEXT: ASHR * T0.Y, PV.X, literal.y,1201; CM-NEXT: 2(2.802597e-45), 31(4.344025e-44)1202;1203; GCN-LABEL: i8_mad_64:1204; GCN: ; %bb.0: ; %entry1205; GCN-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD01206; GCN-NEXT: s_mov_b32 s25, SCRATCH_RSRC_DWORD11207; GCN-NEXT: s_mov_b32 s26, -11208; GCN-NEXT: s_mov_b32 s27, 0xe8f0001209; GCN-NEXT: s_add_u32 s24, s24, s111210; GCN-NEXT: s_addc_u32 s25, s25, 01211; GCN-NEXT: s_load_dword s8, s[4:5], 0x111212; GCN-NEXT: s_waitcnt lgkmcnt(0)1213; GCN-NEXT: s_add_i32 s9, s8, 41214; GCN-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x91215; GCN-NEXT: v_mov_b32_e32 v0, s81216; GCN-NEXT: v_mov_b32_e32 v1, s91217; GCN-NEXT: buffer_load_dword v1, v1, s[24:27], 0 offen1218; GCN-NEXT: buffer_load_dword v0, v0, s[24:27], 0 offen1219; GCN-NEXT: s_mov_b32 s11, 0xf0001220; GCN-NEXT: s_mov_b32 s14, 01221; GCN-NEXT: s_mov_b32 s15, s111222; GCN-NEXT: s_mov_b64 s[18:19], s[14:15]1223; GCN-NEXT: s_mov_b64 s[22:23], s[14:15]1224; GCN-NEXT: s_waitcnt lgkmcnt(0)1225; GCN-NEXT: s_mov_b64 s[12:13], s[2:3]1226; GCN-NEXT: s_mov_b64 s[16:17], s[4:5]1227; GCN-NEXT: s_mov_b64 s[20:21], s[6:7]1228; GCN-NEXT: s_waitcnt vmcnt(0)1229; GCN-NEXT: buffer_load_sbyte v2, v[0:1], s[12:15], 0 addr641230; GCN-NEXT: buffer_load_sbyte v3, v[0:1], s[16:19], 0 addr641231; GCN-NEXT: buffer_load_sbyte v0, v[0:1], s[20:23], 0 addr641232; GCN-NEXT: s_mov_b32 s10, -11233; GCN-NEXT: s_mov_b32 s8, s01234; GCN-NEXT: s_mov_b32 s9, s11235; GCN-NEXT: s_waitcnt vmcnt(2)1236; GCN-NEXT: v_and_b32_e32 v1, 0xffff, v21237; GCN-NEXT: s_waitcnt vmcnt(1)1238; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v31239; GCN-NEXT: s_waitcnt vmcnt(0)1240; GCN-NEXT: v_mad_u32_u24 v0, v1, v2, v01241; GCN-NEXT: v_bfe_i32 v0, v0, 0, 161242; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v01243; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 01244; GCN-NEXT: s_endpgm1245;1246; SI-LABEL: i8_mad_64:1247; SI: ; %bb.0: ; %entry1248; SI-NEXT: s_mov_b32 s88, SCRATCH_RSRC_DWORD01249; SI-NEXT: s_load_dword s0, s[4:5], 0x441250; SI-NEXT: s_mov_b32 s89, SCRATCH_RSRC_DWORD11251; SI-NEXT: s_mov_b32 s90, -11252; SI-NEXT: s_mov_b32 s91, 0xe800001253; SI-NEXT: s_add_u32 s88, s88, s111254; SI-NEXT: s_addc_u32 s89, s89, 01255; SI-NEXT: s_waitcnt lgkmcnt(0)1256; SI-NEXT: s_add_i32 s1, s0, 41257; SI-NEXT: v_mov_b32_e32 v0, s01258; SI-NEXT: buffer_load_dword v4, v0, s[88:91], 0 offen1259; SI-NEXT: v_mov_b32_e32 v0, s11260; SI-NEXT: buffer_load_dword v5, v0, s[88:91], 0 offen1261; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x241262; SI-NEXT: s_waitcnt lgkmcnt(0)1263; SI-NEXT: v_mov_b32_e32 v1, s31264; SI-NEXT: v_mov_b32_e32 v3, s51265; SI-NEXT: v_mov_b32_e32 v6, s71266; SI-NEXT: s_mov_b32 s3, 0xf0001267; SI-NEXT: s_waitcnt vmcnt(1)1268; SI-NEXT: v_add_u32_e32 v0, vcc, s2, v41269; SI-NEXT: s_waitcnt vmcnt(0)1270; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc1271; SI-NEXT: v_add_u32_e32 v2, vcc, s4, v41272; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc1273; SI-NEXT: v_add_u32_e32 v4, vcc, s6, v41274; SI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc1275; SI-NEXT: flat_load_sbyte v0, v[0:1]1276; SI-NEXT: flat_load_sbyte v1, v[2:3]1277; SI-NEXT: flat_load_sbyte v2, v[4:5]1278; SI-NEXT: s_mov_b32 s2, -11279; SI-NEXT: s_waitcnt vmcnt(0)1280; SI-NEXT: v_mad_u16 v0, v0, v1, v21281; SI-NEXT: v_bfe_i32 v0, v0, 0, 161282; SI-NEXT: v_ashrrev_i32_e32 v1, 31, v01283; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01284; SI-NEXT: s_endpgm1285;1286; VI-LABEL: i8_mad_64:1287; VI: ; %bb.0: ; %entry1288; VI-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD01289; VI-NEXT: s_load_dword s0, s[4:5], 0x441290; VI-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD11291; VI-NEXT: s_mov_b32 s14, -11292; VI-NEXT: s_mov_b32 s15, 0xe800001293; VI-NEXT: s_add_u32 s12, s12, s111294; VI-NEXT: s_addc_u32 s13, s13, 01295; VI-NEXT: s_waitcnt lgkmcnt(0)1296; VI-NEXT: s_add_i32 s1, s0, 41297; VI-NEXT: v_mov_b32_e32 v0, s01298; VI-NEXT: buffer_load_dword v4, v0, s[12:15], 0 offen1299; VI-NEXT: v_mov_b32_e32 v0, s11300; VI-NEXT: buffer_load_dword v5, v0, s[12:15], 0 offen1301; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x241302; VI-NEXT: s_waitcnt lgkmcnt(0)1303; VI-NEXT: v_mov_b32_e32 v1, s31304; VI-NEXT: v_mov_b32_e32 v3, s51305; VI-NEXT: v_mov_b32_e32 v6, s71306; VI-NEXT: s_mov_b32 s3, 0xf0001307; VI-NEXT: s_waitcnt vmcnt(1)1308; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41309; VI-NEXT: s_waitcnt vmcnt(0)1310; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc1311; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41312; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc1313; VI-NEXT: v_add_u32_e32 v4, vcc, s6, v41314; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc1315; VI-NEXT: flat_load_sbyte v0, v[0:1]1316; VI-NEXT: flat_load_sbyte v1, v[2:3]1317; VI-NEXT: flat_load_sbyte v2, v[4:5]1318; VI-NEXT: s_mov_b32 s2, -11319; VI-NEXT: s_waitcnt vmcnt(0)1320; VI-NEXT: v_mad_u16 v0, v0, v1, v21321; VI-NEXT: v_bfe_i32 v0, v0, 0, 161322; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v01323; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01324; VI-NEXT: s_endpgm1325entry:1326 %retval.0.i = load i64, ptr addrspace(5) %idx1327 %arrayidx = getelementptr inbounds i8, ptr addrspace(1) %a, i64 %retval.0.i1328 %arrayidx2 = getelementptr inbounds i8, ptr addrspace(1) %b, i64 %retval.0.i1329 %arrayidx4 = getelementptr inbounds i8, ptr addrspace(1) %c, i64 %retval.0.i1330 %la = load i8, ptr addrspace(1) %arrayidx, align 11331 %lb = load i8, ptr addrspace(1) %arrayidx2, align 11332 %lc = load i8, ptr addrspace(1) %arrayidx4, align 11333 %exta = sext i8 %la to i161334 %extb = sext i8 %lb to i161335 %extc = sext i8 %lc to i161336 %mul = mul i16 %exta, %extb1337 %mad = add i16 %mul, %extc1338 %mad_ext = sext i16 %mad to i641339 store i64 %mad_ext, ptr addrspace(1) %out1340 ret void1341}1342 1343; The ands are asserting the high bits are 0. SimplifyDemandedBits on1344; the adds would remove the ands before the target combine on the mul1345; had a chance to form mul24. The mul combine would then see1346; extractelement with no known bits and fail. All of the mul/add1347; combos in this loop should form v_mad_u32_u24.1348define void @mad24_known_bits_destroyed(i32 %arg, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, i32 %arg4, i32 %arg5, i32 %arg6, ptr addrspace(1) %arg7, ptr addrspace(1) %arg8) #0 {1349; EG-LABEL: mad24_known_bits_destroyed:1350; EG: ; %bb.0: ; %bb1351; EG-NEXT: ALU 21, @12, KC0[CB0:0-32], KC1[]1352; EG-NEXT: LOOP_START_DX10 @111353; EG-NEXT: ALU 8, @34, KC0[], KC1[]1354; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 01355; EG-NEXT: ALU 14, @43, KC0[], KC1[]1356; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 01357; EG-NEXT: ALU_PUSH_BEFORE 3, @58, KC0[], KC1[]1358; EG-NEXT: JUMP @10 POP:11359; EG-NEXT: LOOP_BREAK @101360; EG-NEXT: POP @10 POP:11361; EG-NEXT: END_LOOP @21362; EG-NEXT: CF_END1363; EG-NEXT: ALU clause starting at 12:1364; EG-NEXT: MOV * T0.W, KC0[5].X,1365; EG-NEXT: MOV * T0.Z, KC0[4].W,1366; EG-NEXT: MOV * T0.Y, KC0[4].Z,1367; EG-NEXT: MOV T0.X, KC0[2].Y,1368; EG-NEXT: AND_INT * T1.Y, KC0[4].X, literal.x,1369; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1370; EG-NEXT: AND_INT T1.Z, KC0[3].W, literal.x,1371; EG-NEXT: AND_INT T1.W, KC0[3].Z, literal.x,1372; EG-NEXT: MOV * T2.W, KC0[7].Y,1373; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1374; EG-NEXT: LSHR T1.X, PS, literal.x,1375; EG-NEXT: AND_INT T2.Y, KC0[6].Y, literal.y,1376; EG-NEXT: MOV T2.Z, KC0[6].X,1377; EG-NEXT: MOV * T2.W, KC0[5].W,1378; EG-NEXT: 2(2.802597e-45), 16777215(2.350989e-38)1379; EG-NEXT: MOV * T3.W, KC0[7].X,1380; EG-NEXT: LSHR T2.X, PV.W, literal.x,1381; EG-NEXT: MOV T3.Y, KC0[5].Z,1382; EG-NEXT: MOV T3.Z, KC0[6].Z,1383; EG-NEXT: MOV * T3.W, KC0[6].W,1384; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1385; EG-NEXT: MOV * T4.W, KC0[4].Y,1386; EG-NEXT: ALU clause starting at 34:1387; EG-NEXT: MULLO_INT * T0.X, T0.X, T2.Y,1388; EG-NEXT: ADD_INT * T4.W, PS, T3.Z,1389; EG-NEXT: AND_INT * T4.W, PV.W, literal.x,1390; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1391; EG-NEXT: MULLO_INT * T0.X, PV.W, T2.Y,1392; EG-NEXT: MULLO_INT * T0.W, T0.W, T1.Y,1393; EG-NEXT: MULLO_INT * T0.Z, T0.Z, T1.Z,1394; EG-NEXT: MULLO_INT * T0.Y, T0.Y, T1.W,1395; EG-NEXT: ADD_INT * T0.X, T0.X, T3.Z,1396; EG-NEXT: ALU clause starting at 43:1397; EG-NEXT: ADD_INT * T4.W, T0.Y, T3.Y,1398; EG-NEXT: AND_INT T4.W, PV.W, literal.x,1399; EG-NEXT: ADD_INT * T5.W, T0.Z, T2.W,1400; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1401; EG-NEXT: AND_INT T0.Z, PS, literal.x,1402; EG-NEXT: ADD_INT T0.W, T0.W, T2.Z,1403; EG-NEXT: MULLO_INT * T0.Y, PV.W, T1.W,1404; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1405; EG-NEXT: ADD_INT T0.Y, PS, T3.Y,1406; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1407; EG-NEXT: MULLO_INT * T0.Z, PV.Z, T1.Z,1408; EG-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1409; EG-NEXT: ADD_INT T0.Z, PS, T2.W,1410; EG-NEXT: MULLO_INT * T0.W, PV.W, T1.Y,1411; EG-NEXT: ADD_INT * T0.W, PS, T2.Z,1412; EG-NEXT: ALU clause starting at 58:1413; EG-NEXT: ADD_INT * T3.W, T3.W, literal.x,1414; EG-NEXT: -1(nan), 0(0.000000e+00)1415; EG-NEXT: SETE_INT * T4.W, PV.W, 0.0,1416; EG-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,1417;1418; CM-LABEL: mad24_known_bits_destroyed:1419; CM: ; %bb.0: ; %bb1420; CM-NEXT: ALU 22, @12, KC0[CB0:0-32], KC1[]1421; CM-NEXT: LOOP_START_DX10 @111422; CM-NEXT: ALU 23, @35, KC0[], KC1[]1423; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T2.X1424; CM-NEXT: ALU 23, @59, KC0[], KC1[]1425; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X1426; CM-NEXT: ALU_PUSH_BEFORE 3, @83, KC0[], KC1[]1427; CM-NEXT: JUMP @10 POP:11428; CM-NEXT: LOOP_BREAK @101429; CM-NEXT: POP @10 POP:11430; CM-NEXT: END_LOOP @21431; CM-NEXT: CF_END1432; CM-NEXT: ALU clause starting at 12:1433; CM-NEXT: MOV * T0.W, KC0[5].X,1434; CM-NEXT: MOV * T0.Z, KC0[4].W,1435; CM-NEXT: MOV * T0.Y, KC0[4].Z,1436; CM-NEXT: MOV T0.X, KC0[2].Y,1437; CM-NEXT: AND_INT * T1.Y, KC0[4].X, literal.x,1438; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1439; CM-NEXT: AND_INT T1.Z, KC0[3].W, literal.x,1440; CM-NEXT: AND_INT * T1.W, KC0[3].Z, literal.x,1441; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1442; CM-NEXT: AND_INT T2.Y, KC0[6].Y, literal.x,1443; CM-NEXT: MOV T2.Z, KC0[6].X,1444; CM-NEXT: MOV * T2.W, KC0[7].Y,1445; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1446; CM-NEXT: LSHR T1.X, PV.W, literal.x,1447; CM-NEXT: MOV T3.Y, KC0[5].W,1448; CM-NEXT: MOV T3.Z, KC0[5].Z,1449; CM-NEXT: MOV * T2.W, KC0[7].X,1450; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1451; CM-NEXT: LSHR T2.X, PV.W, literal.x,1452; CM-NEXT: MOV T4.Y, KC0[6].Z,1453; CM-NEXT: MOV T4.Z, KC0[6].W,1454; CM-NEXT: MOV * T2.W, KC0[4].Y,1455; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1456; CM-NEXT: ALU clause starting at 35:1457; CM-NEXT: MULLO_INT T0.X, T0.X, T2.Y,1458; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.X, T2.Y,1459; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.X, T2.Y,1460; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.X, T2.Y,1461; CM-NEXT: ADD_INT * T2.W, PV.X, T4.Y,1462; CM-NEXT: AND_INT * T2.W, PV.W, literal.x,1463; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1464; CM-NEXT: MULLO_INT T0.X, T2.W, T2.Y,1465; CM-NEXT: MULLO_INT T0.Y (MASKED), T2.W, T2.Y,1466; CM-NEXT: MULLO_INT T0.Z (MASKED), T2.W, T2.Y,1467; CM-NEXT: MULLO_INT * T0.W (MASKED), T2.W, T2.Y,1468; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Y,1469; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Y,1470; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Y,1471; CM-NEXT: MULLO_INT * T0.W, T0.W, T1.Y,1472; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Z, T1.Z,1473; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.Z, T1.Z,1474; CM-NEXT: MULLO_INT T0.Z, T0.Z, T1.Z,1475; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Z, T1.Z,1476; CM-NEXT: MULLO_INT T0.X (MASKED), T0.Y, T1.W,1477; CM-NEXT: MULLO_INT T0.Y, T0.Y, T1.W,1478; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.Y, T1.W,1479; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.Y, T1.W,1480; CM-NEXT: ADD_INT * T0.X, T0.X, T4.Y,1481; CM-NEXT: ALU clause starting at 59:1482; CM-NEXT: ADD_INT * T2.W, T0.Y, T3.Z,1483; CM-NEXT: ADD_INT T0.Z, T0.Z, T3.Y,1484; CM-NEXT: AND_INT * T2.W, PV.W, literal.x,1485; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1486; CM-NEXT: MULLO_INT T0.X (MASKED), T2.W, T1.W,1487; CM-NEXT: MULLO_INT T0.Y, T2.W, T1.W,1488; CM-NEXT: MULLO_INT T0.Z (MASKED), T2.W, T1.W,1489; CM-NEXT: MULLO_INT * T0.W (MASKED), T2.W, T1.W,1490; CM-NEXT: ADD_INT T0.Y, PV.Y, T3.Z,1491; CM-NEXT: ADD_INT T5.Z, T0.W, T2.Z, BS:VEC_021/SCL_1221492; CM-NEXT: AND_INT * T0.W, T0.Z, literal.x,1493; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1494; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Z,1495; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Z,1496; CM-NEXT: MULLO_INT T0.Z, T0.W, T1.Z,1497; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T1.Z,1498; CM-NEXT: ADD_INT T0.Z, PV.Z, T3.Y,1499; CM-NEXT: AND_INT * T0.W, T5.Z, literal.x,1500; CM-NEXT: 16777215(2.350989e-38), 0(0.000000e+00)1501; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, T1.Y,1502; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T1.Y,1503; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T1.Y,1504; CM-NEXT: MULLO_INT * T0.W, T0.W, T1.Y,1505; CM-NEXT: ADD_INT * T0.W, PV.W, T2.Z,1506; CM-NEXT: ALU clause starting at 83:1507; CM-NEXT: ADD_INT * T4.Z, T4.Z, literal.x,1508; CM-NEXT: -1(nan), 0(0.000000e+00)1509; CM-NEXT: SETE_INT * T2.W, PV.Z, 0.0,1510; CM-NEXT: PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,1511;1512; GCN-LABEL: mad24_known_bits_destroyed:1513; GCN: ; %bb.0: ; %bb1514; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1515; GCN-NEXT: v_mov_b32_e32 v5, v01516; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v131517; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v21518; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v31519; GCN-NEXT: v_and_b32_e32 v3, 0xffffff, v41520; GCN-NEXT: s_mov_b64 s[8:9], 01521; GCN-NEXT: s_mov_b32 s6, 01522; GCN-NEXT: s_mov_b32 s7, 0xf0001523; GCN-NEXT: s_mov_b32 s4, s61524; GCN-NEXT: s_mov_b32 s5, s61525; GCN-NEXT: .LBB9_1: ; %bb191526; GCN-NEXT: ; =>This Inner Loop Header: Depth=11527; GCN-NEXT: v_mad_u32_u24 v4, v5, v0, v141528; GCN-NEXT: s_waitcnt expcnt(0)1529; GCN-NEXT: v_mad_u32_u24 v6, v6, v1, v101530; GCN-NEXT: v_mad_u32_u24 v7, v7, v2, v111531; GCN-NEXT: v_mad_u32_u24 v8, v8, v3, v121532; GCN-NEXT: v_add_i32_e32 v15, vcc, -1, v151533; GCN-NEXT: v_mad_u32_u24 v5, v4, v0, v141534; GCN-NEXT: v_mad_u32_u24 v6, v6, v1, v101535; GCN-NEXT: v_mad_u32_u24 v7, v7, v2, v111536; GCN-NEXT: v_mad_u32_u24 v8, v8, v3, v121537; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v151538; GCN-NEXT: buffer_store_dword v5, v[16:17], s[4:7], 0 addr641539; GCN-NEXT: s_or_b64 s[8:9], vcc, s[8:9]1540; GCN-NEXT: buffer_store_dwordx4 v[5:8], v[18:19], s[4:7], 0 addr641541; GCN-NEXT: s_andn2_b64 exec, exec, s[8:9]1542; GCN-NEXT: s_cbranch_execnz .LBB9_11543; GCN-NEXT: ; %bb.2: ; %bb181544; GCN-NEXT: s_or_b64 exec, exec, s[8:9]1545; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)1546; GCN-NEXT: s_setpc_b64 s[30:31]1547;1548; GFX8-LABEL: mad24_known_bits_destroyed:1549; GFX8: ; %bb.0: ; %bb1550; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1551; GFX8-NEXT: v_mov_b32_e32 v5, v01552; GFX8-NEXT: v_and_b32_e32 v0, 0xffffff, v131553; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v21554; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v31555; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v41556; GFX8-NEXT: s_mov_b64 s[4:5], 01557; GFX8-NEXT: .LBB9_1: ; %bb191558; GFX8-NEXT: ; =>This Inner Loop Header: Depth=11559; GFX8-NEXT: v_add_u32_e32 v15, vcc, -1, v151560; GFX8-NEXT: v_mad_u32_u24 v4, v5, v0, v141561; GFX8-NEXT: v_mad_u32_u24 v6, v6, v1, v101562; GFX8-NEXT: v_mad_u32_u24 v7, v7, v2, v111563; GFX8-NEXT: v_mad_u32_u24 v8, v8, v3, v121564; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v151565; GFX8-NEXT: v_mad_u32_u24 v5, v4, v0, v141566; GFX8-NEXT: v_mad_u32_u24 v6, v6, v1, v101567; GFX8-NEXT: v_mad_u32_u24 v7, v7, v2, v111568; GFX8-NEXT: v_mad_u32_u24 v8, v8, v3, v121569; GFX8-NEXT: s_or_b64 s[4:5], vcc, s[4:5]1570; GFX8-NEXT: flat_store_dword v[16:17], v51571; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[5:8]1572; GFX8-NEXT: s_andn2_b64 exec, exec, s[4:5]1573; GFX8-NEXT: s_cbranch_execnz .LBB9_11574; GFX8-NEXT: ; %bb.2: ; %bb181575; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]1576; GFX8-NEXT: s_waitcnt vmcnt(0)1577; GFX8-NEXT: s_setpc_b64 s[30:31]1578bb:1579 %tmp = and i32 %arg4, 167772151580 %tmp9 = extractelement <4 x i32> %arg1, i64 11581 %tmp10 = extractelement <4 x i32> %arg3, i64 11582 %tmp11 = and i32 %tmp9, 167772151583 %tmp12 = extractelement <4 x i32> %arg1, i64 21584 %tmp13 = extractelement <4 x i32> %arg3, i64 21585 %tmp14 = and i32 %tmp12, 167772151586 %tmp15 = extractelement <4 x i32> %arg1, i64 31587 %tmp16 = extractelement <4 x i32> %arg3, i64 31588 %tmp17 = and i32 %tmp15, 167772151589 br label %bb191590 1591bb18: ; preds = %bb191592 ret void1593 1594bb19: ; preds = %bb19, %bb1595 %tmp20 = phi i32 [ %arg, %bb ], [ %tmp40, %bb19 ]1596 %tmp21 = phi i32 [ 0, %bb ], [ %tmp54, %bb19 ]1597 %tmp22 = phi <4 x i32> [ %arg2, %bb ], [ %tmp53, %bb19 ]1598 %tmp23 = and i32 %tmp20, 167772151599 %tmp24 = mul i32 %tmp23, %tmp1600 %tmp25 = add i32 %tmp24, %arg51601 %tmp26 = extractelement <4 x i32> %tmp22, i64 11602 %tmp27 = and i32 %tmp26, 167772151603 %tmp28 = mul i32 %tmp27, %tmp111604 %tmp29 = add i32 %tmp28, %tmp101605 %tmp30 = extractelement <4 x i32> %tmp22, i64 21606 %tmp31 = and i32 %tmp30, 167772151607 %tmp32 = mul i32 %tmp31, %tmp141608 %tmp33 = add i32 %tmp32, %tmp131609 %tmp34 = extractelement <4 x i32> %tmp22, i64 31610 %tmp35 = and i32 %tmp34, 167772151611 %tmp36 = mul i32 %tmp35, %tmp171612 %tmp37 = add i32 %tmp36, %tmp161613 %tmp38 = and i32 %tmp25, 167772151614 %tmp39 = mul i32 %tmp38, %tmp1615 %tmp40 = add i32 %tmp39, %arg51616 store i32 %tmp40, ptr addrspace(1) %arg71617 %tmp41 = insertelement <4 x i32> poison, i32 %tmp40, i32 01618 %tmp42 = and i32 %tmp29, 167772151619 %tmp43 = mul i32 %tmp42, %tmp111620 %tmp44 = add i32 %tmp43, %tmp101621 %tmp45 = insertelement <4 x i32> %tmp41, i32 %tmp44, i32 11622 %tmp46 = and i32 %tmp33, 167772151623 %tmp47 = mul i32 %tmp46, %tmp141624 %tmp48 = add i32 %tmp47, %tmp131625 %tmp49 = insertelement <4 x i32> %tmp45, i32 %tmp48, i32 21626 %tmp50 = and i32 %tmp37, 167772151627 %tmp51 = mul i32 %tmp50, %tmp171628 %tmp52 = add i32 %tmp51, %tmp161629 %tmp53 = insertelement <4 x i32> %tmp49, i32 %tmp52, i32 31630 store <4 x i32> %tmp53, ptr addrspace(1) %arg81631 %tmp54 = add nuw nsw i32 %tmp21, 11632 %tmp55 = icmp eq i32 %tmp54, %arg61633 br i1 %tmp55, label %bb18, label %bb191634}1635 1636attributes #0 = { norecurse nounwind }1637