219 lines · plain
1; RUN: llc -mtriple=amdgcn -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s2; XUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s3 4 ; FIXME: None of these trigger madmk emission anymore. It is still5 ; possible, but requires the correct registers to be used which is6 ; hard to trigger.7 8declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone9declare float @llvm.fabs.f32(float) nounwind readnone10 11; GCN-LABEL: {{^}}madmk_f32:12; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}13; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:414; GCN: v_madmk_f32 {{v[0-9]+}}, [[VA]], 0x41200000, [[VB]]15define amdgpu_kernel void @madmk_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {16 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone17 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid18 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 119 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid20 21 %a = load volatile float, ptr addrspace(1) %gep.0, align 422 %b = load volatile float, ptr addrspace(1) %gep.1, align 423 24 %mul = fmul float %a, 10.025 %madmk = fadd float %mul, %b26 store float %madmk, ptr addrspace(1) %out.gep, align 427 ret void28}29 30; GCN-LABEL: {{^}}madmk_2_use_f32:31; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}32; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:433; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:834; GCN-DAG: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]35; GCN-DAG: v_mac_f32_e32 [[VC]], 0x41200000, [[VA]]36; GCN: s_endpgm37define amdgpu_kernel void @madmk_2_use_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {38 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone39 40 %in.gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid41 %in.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 142 %in.gep.2 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 243 44 %out.gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid45 %out.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 146 47 %a = load volatile float, ptr addrspace(1) %in.gep.0, align 448 %b = load volatile float, ptr addrspace(1) %in.gep.1, align 449 %c = load volatile float, ptr addrspace(1) %in.gep.2, align 450 51 %mul0 = fmul float %a, 10.052 %mul1 = fmul float %a, 10.053 %madmk0 = fadd float %mul0, %b54 %madmk1 = fadd float %mul1, %c55 56 store float %madmk0, ptr addrspace(1) %out.gep.0, align 457 store float %madmk1, ptr addrspace(1) %out.gep.1, align 458 ret void59}60 61; We don't get any benefit if the constant is an inline immediate.62; GCN-LABEL: {{^}}madmk_inline_imm_f32:63; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}64; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:465; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]]66define amdgpu_kernel void @madmk_inline_imm_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {67 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone68 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid69 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 170 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid71 72 %a = load volatile float, ptr addrspace(1) %gep.0, align 473 %b = load volatile float, ptr addrspace(1) %gep.1, align 474 75 %mul = fmul float %a, 4.076 %madmk = fadd float %mul, %b77 store float %madmk, ptr addrspace(1) %out.gep, align 478 ret void79}80 81; GCN-LABEL: {{^}}s_s_madmk_f32:82; GCN-NOT: v_madmk_f3283; GCN: v_mac_f32_e3284; GCN: s_endpgm85define amdgpu_kernel void @s_s_madmk_f32(ptr addrspace(1) noalias %out, [8 x i32], float %a, [8 x i32], float %b) #0 {86 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone87 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid88 89 %mul = fmul float %a, 10.090 %madmk = fadd float %mul, %b91 store float %madmk, ptr addrspace(1) %out.gep, align 492 ret void93}94 95; GCN-LABEL: {{^}}v_s_madmk_f32:96; GCN-DAG: s_load_dword [[SREG:s[0-9]+]]97; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]]98; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]]99; GCN: v_madmk_f32 {{v[0-9]+}}, [[VREG1]], 0x41200000, [[VREG2]]100; GCN: s_endpgm101define amdgpu_kernel void @v_s_madmk_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, float %b) #0 {102 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone103 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid104 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid105 %a = load float, ptr addrspace(1) %gep.0, align 4106 107 %mul = fmul float %a, 10.0108 %madmk = fadd float %mul, %b109 store float %madmk, ptr addrspace(1) %out.gep, align 4110 ret void111}112 113; GCN-LABEL: {{^}}scalar_vector_madmk_f32:114; GCN-NOT: v_madmk_f32115; GCN: v_mac_f32_e32116; GCN: s_endpgm117define amdgpu_kernel void @scalar_vector_madmk_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, float %a) #0 {118 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone119 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid120 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid121 %b = load float, ptr addrspace(1) %gep.0, align 4122 123 %mul = fmul float %a, 10.0124 %madmk = fadd float %mul, %b125 store float %madmk, ptr addrspace(1) %out.gep, align 4126 ret void127}128 129; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32:130; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}131; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4132; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000133; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]]134define amdgpu_kernel void @no_madmk_src0_modifier_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {135 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone136 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid137 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1138 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid139 140 %a = load volatile float, ptr addrspace(1) %gep.0, align 4141 %b = load volatile float, ptr addrspace(1) %gep.1, align 4142 143 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone144 145 %mul = fmul float %a.fabs, 10.0146 %madmk = fadd float %mul, %b147 store float %madmk, ptr addrspace(1) %out.gep, align 4148 ret void149}150 151; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32:152; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}153; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4154; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}|155define amdgpu_kernel void @no_madmk_src2_modifier_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {156 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone157 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid158 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1159 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid160 161 %a = load volatile float, ptr addrspace(1) %gep.0, align 4162 %b = load volatile float, ptr addrspace(1) %gep.1, align 4163 164 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone165 166 %mul = fmul float %a, 10.0167 %madmk = fadd float %mul, %b.fabs168 store float %madmk, ptr addrspace(1) %out.gep, align 4169 ret void170}171 172; GCN-LABEL: {{^}}madmk_add_inline_imm_f32:173; GCN: buffer_load_dword [[A:v[0-9]+]]174; GCN: v_mov_b32_e32 [[B:v[0-9]+]], 2.0175; GCN: v_madmk_f32 {{v[0-9]+}}, [[A]], 0x41200000, [[B]]176 177define amdgpu_kernel void @madmk_add_inline_imm_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {178 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone179 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid180 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid181 182 %a = load float, ptr addrspace(1) %gep.0, align 4183 184 %mul = fmul float %a, 10.0185 %madmk = fadd float %mul, 2.0186 store float %madmk, ptr addrspace(1) %out.gep, align 4187 ret void188}189 190; SI-LABEL: {{^}}kill_madmk_verifier_error:191; SI: s_or_b64192; SI: s_xor_b64193; SI: v_mac_f32_e32 {{v[0-9]+}}, 0x472aee8c, {{v[0-9]+}}194define amdgpu_kernel void @kill_madmk_verifier_error() #0 {195bb:196 br label %bb2197 198bb1: ; preds = %bb2199 ret void200 201bb2: ; preds = %bb6, %bb202 %tmp = phi float [ poison, %bb ], [ %tmp8, %bb6 ]203 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1204 %f_tid = bitcast i32 %tid to float205 %tmp3 = fsub float %f_tid, %tmp206 %tmp5 = fcmp oeq float %tmp3, 1.000000e+04207 br i1 %tmp5, label %bb1, label %bb6208 209bb6: ; preds = %bb2210 %tmp7 = fmul float %tmp, 0x40E55DD180000000211 %tmp8 = fadd float %tmp7, %tmp212 br label %bb2213}214 215declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1216 217attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }218attributes #1 = { nounwind readnone }219