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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 %s -o - | FileCheck -check-prefix=GFX9 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 %s -o - | FileCheck -check-prefix=GFX10 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 %s -o - | FileCheck -check-prefix=GFX11 %s5 6define amdgpu_kernel void @test(ptr addrspace(1) %src, ptr addrspace(1) %dst) {7; GFX9-LABEL: test:8; GFX9: ; %bb.0: ; %entry9; GFX9-NEXT: s_load_dword s4, s[8:9], 0x1c10; GFX9-NEXT: s_load_dword s5, s[8:9], 0x3811; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x012; GFX9-NEXT: s_waitcnt lgkmcnt(0)13; GFX9-NEXT: s_and_b32 s4, s4, 0xffff14; GFX9-NEXT: s_mul_i32 s14, s14, s415; GFX9-NEXT: s_add_i32 s5, s5, s1416; GFX9-NEXT: v_add_u32_e32 v1, s5, v017; GFX9-NEXT: v_mov_b32_e32 v0, 018; GFX9-NEXT: v_ashrrev_i64 v[4:5], 28, v[0:1]19; GFX9-NEXT: v_mov_b32_e32 v1, s120; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v421; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v5, vcc22; GFX9-NEXT: global_load_dwordx4 v[0:3], v[0:1], off23; GFX9-NEXT: v_mov_b32_e32 v6, s324; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, s2, v425; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v5, vcc26; GFX9-NEXT: s_waitcnt vmcnt(0)27; GFX9-NEXT: v_not_b32_e32 v3, v328; GFX9-NEXT: v_not_b32_e32 v2, v229; GFX9-NEXT: v_not_b32_e32 v1, v130; GFX9-NEXT: v_not_b32_e32 v0, v031; GFX9-NEXT: global_store_dwordx4 v[4:5], v[0:3], off32; GFX9-NEXT: s_endpgm33;34; GFX10-LABEL: test:35; GFX10: ; %bb.0: ; %entry36; GFX10-NEXT: s_clause 0x237; GFX10-NEXT: s_load_dword s4, s[8:9], 0x1c38; GFX10-NEXT: s_load_dword s5, s[8:9], 0x3839; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x040; GFX10-NEXT: v_mov_b32_e32 v1, 041; GFX10-NEXT: s_waitcnt lgkmcnt(0)42; GFX10-NEXT: s_and_b32 s4, s4, 0xffff43; GFX10-NEXT: s_mul_i32 s14, s14, s444; GFX10-NEXT: v_add3_u32 v2, s5, s14, v045; GFX10-NEXT: v_ashrrev_i64 v[4:5], 28, v[1:2]46; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, s0, v447; GFX10-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v5, vcc_lo48; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, s2, v449; GFX10-NEXT: v_add_co_ci_u32_e64 v5, null, s3, v5, vcc_lo50; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off51; GFX10-NEXT: s_waitcnt vmcnt(0)52; GFX10-NEXT: v_not_b32_e32 v3, v353; GFX10-NEXT: v_not_b32_e32 v2, v254; GFX10-NEXT: v_not_b32_e32 v1, v155; GFX10-NEXT: v_not_b32_e32 v0, v056; GFX10-NEXT: global_store_dwordx4 v[4:5], v[0:3], off57; GFX10-NEXT: s_endpgm58;59; GFX11-LABEL: test:60; GFX11: ; %bb.0: ; %entry61; GFX11-NEXT: s_clause 0x262; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x1c63; GFX11-NEXT: s_load_b32 s7, s[4:5], 0x3864; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x065; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, 0x3ff, v066; GFX11-NEXT: s_waitcnt lgkmcnt(0)67; GFX11-NEXT: s_and_b32 s4, s6, 0xffff68; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)69; GFX11-NEXT: s_mul_i32 s13, s13, s470; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)71; GFX11-NEXT: v_add3_u32 v1, s7, s13, v172; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)73; GFX11-NEXT: v_ashrrev_i64 v[4:5], 28, v[0:1]74; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, s0, v475; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)76; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v5, vcc_lo77; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, s2, v478; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, s3, v5, vcc_lo79; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off80; GFX11-NEXT: s_waitcnt vmcnt(0)81; GFX11-NEXT: v_not_b32_e32 v3, v382; GFX11-NEXT: v_not_b32_e32 v2, v283; GFX11-NEXT: v_not_b32_e32 v1, v184; GFX11-NEXT: v_not_b32_e32 v0, v085; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off86; GFX11-NEXT: s_endpgm87entry:88 %implicitarg.ptr = tail call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()89 %arg.1.ptr = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 4090 %arg.1 = load i64, ptr addrspace(4) %arg.1.ptr, align 891 %workgroup.id.x = tail call i32 @llvm.amdgcn.workgroup.id.x()92 %arg.2.ptr = getelementptr inbounds i8, ptr addrspace(4) %implicitarg.ptr, i64 1293 %arg.2 = load i16, ptr addrspace(4) %arg.2.ptr, align 494 %arg.2.ext = zext i16 %arg.2 to i3295 %mul = mul i32 %workgroup.id.x, %arg.2.ext96 %workitem.id.x = tail call i32 @llvm.amdgcn.workitem.id.x()97 %add = add i32 %mul, %workitem.id.x98 %add.ext = zext i32 %add to i6499 %add.1 = add i64 %arg.1, %add.ext100 %sext = shl i64 %add.1, 32101 %idxprom = ashr exact i64 %sext, 32102 %arrayidx = getelementptr inbounds <16 x i8>, ptr addrspace(1) %src, i64 %idxprom103 %arrayval = load <16 x i8>, ptr addrspace(1) %arrayidx, align 16104 %not = xor <16 x i8> %arrayval, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>105 %arrayidx2 = getelementptr inbounds <16 x i8>, ptr addrspace(1) %dst, i64 %idxprom106 store <16 x i8> %not, ptr addrspace(1) %arrayidx2, align 16107 ret void108}109