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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=amdgcn -mcpu=pitcairn < %s | FileCheck -enable-var-scope -check-prefix=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 --amdgpu-enable-vopd=0 < %s | FileCheck -enable-var-scope -check-prefix=GFX1250 %s4; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s5 6define amdgpu_kernel void @v_test_imax_sge_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {7; SI-LABEL: v_test_imax_sge_i32:8; SI: ; %bb.0:9; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd10; SI-NEXT: s_mov_b32 s7, 0xf00011; SI-NEXT: s_mov_b32 s2, 012; SI-NEXT: s_mov_b32 s3, s713; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v014; SI-NEXT: v_mov_b32_e32 v1, 015; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr6417; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x918; SI-NEXT: s_mov_b32 s6, -119; SI-NEXT: s_waitcnt lgkmcnt(0)20; SI-NEXT: s_load_dword s2, s[2:3], 0x021; SI-NEXT: s_mov_b32 s4, s022; SI-NEXT: s_mov_b32 s5, s123; SI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)24; SI-NEXT: v_max_i32_e32 v0, s2, v025; SI-NEXT: buffer_store_dword v0, off, s[4:7], 026; SI-NEXT: s_endpgm27;28; GFX1250-LABEL: v_test_imax_sge_i32:29; GFX1250: ; %bb.0:30; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 131; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x3432; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v033; GFX1250-NEXT: v_mov_b32_e32 v1, 034; GFX1250-NEXT: s_wait_kmcnt 0x035; GFX1250-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset36; GFX1250-NEXT: s_wait_xcnt 0x037; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x2438; GFX1250-NEXT: s_wait_kmcnt 0x039; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x040; GFX1250-NEXT: s_wait_loadcnt 0x041; GFX1250-NEXT: s_wait_kmcnt 0x042; GFX1250-NEXT: v_max_i32_e32 v0, s2, v043; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]44; GFX1250-NEXT: s_endpgm45;46; EG-LABEL: v_test_imax_sge_i32:47; EG: ; %bb.0:48; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]49; EG-NEXT: TEX 1 @650; EG-NEXT: ALU 2, @14, KC0[CB0:0-32], KC1[]51; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 152; EG-NEXT: CF_END53; EG-NEXT: PAD54; EG-NEXT: Fetch clause starting at 6:55; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #156; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #157; EG-NEXT: ALU clause starting at 10:58; EG-NEXT: MOV T1.X, KC0[2].Z,59; EG-NEXT: LSHL * T0.W, T0.X, literal.x,60; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)61; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,62; EG-NEXT: ALU clause starting at 14:63; EG-NEXT: MAX_INT T0.X, T1.X, T0.X,64; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,65; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)66 %tid = call i32 @llvm.amdgcn.workitem.id.x()67 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid68 %a = load i32, ptr addrspace(1) %aptr, align 469 %b = load i32, ptr addrspace(1) %gep.in, align 470 %cmp = icmp sge i32 %a, %b71 %val = select i1 %cmp, i32 %a, i32 %b72 store i32 %val, ptr addrspace(1) %out, align 473 ret void74}75 76; These could be merged into one77define amdgpu_kernel void @v_test_imax_sge_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {78; SI-LABEL: v_test_imax_sge_v4i32:79; SI: ; %bb.0:80; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd81; SI-NEXT: s_mov_b32 s7, 0xf00082; SI-NEXT: s_mov_b32 s2, 083; SI-NEXT: s_mov_b32 s3, s784; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v085; SI-NEXT: v_mov_b32_e32 v1, 086; SI-NEXT: s_waitcnt lgkmcnt(0)87; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 addr6488; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x989; SI-NEXT: s_mov_b32 s6, -190; SI-NEXT: s_waitcnt lgkmcnt(0)91; SI-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x092; SI-NEXT: s_mov_b32 s4, s093; SI-NEXT: s_mov_b32 s5, s194; SI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)95; SI-NEXT: v_max_i32_e32 v3, s11, v396; SI-NEXT: v_max_i32_e32 v2, s10, v297; SI-NEXT: v_max_i32_e32 v1, s9, v198; SI-NEXT: v_max_i32_e32 v0, s8, v099; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0100; SI-NEXT: s_endpgm101;102; GFX1250-LABEL: v_test_imax_sge_v4i32:103; GFX1250: ; %bb.0:104; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1105; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34106; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0107; GFX1250-NEXT: v_mov_b32_e32 v4, 0108; GFX1250-NEXT: s_wait_kmcnt 0x0109; GFX1250-NEXT: global_load_b128 v[0:3], v0, s[0:1] scale_offset110; GFX1250-NEXT: s_wait_xcnt 0x0111; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24112; GFX1250-NEXT: s_wait_kmcnt 0x0113; GFX1250-NEXT: s_load_b128 s[4:7], s[2:3], 0x0114; GFX1250-NEXT: s_wait_loadcnt 0x0115; GFX1250-NEXT: s_wait_kmcnt 0x0116; GFX1250-NEXT: v_max_i32_e32 v3, s7, v3117; GFX1250-NEXT: v_max_i32_e32 v2, s6, v2118; GFX1250-NEXT: v_max_i32_e32 v1, s5, v1119; GFX1250-NEXT: v_max_i32_e32 v0, s4, v0120; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[0:1]121; GFX1250-NEXT: s_endpgm122;123; EG-LABEL: v_test_imax_sge_v4i32:124; EG: ; %bb.0:125; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]126; EG-NEXT: TEX 1 @6127; EG-NEXT: ALU 5, @14, KC0[CB0:0-32], KC1[]128; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1129; EG-NEXT: CF_END130; EG-NEXT: PAD131; EG-NEXT: Fetch clause starting at 6:132; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1133; EG-NEXT: VTX_READ_128 T1.XYZW, T1.X, 0, #1134; EG-NEXT: ALU clause starting at 10:135; EG-NEXT: MOV T1.X, KC0[2].Z,136; EG-NEXT: LSHL * T0.W, T0.X, literal.x,137; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)138; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,139; EG-NEXT: ALU clause starting at 14:140; EG-NEXT: MAX_INT * T0.W, T1.W, T0.W,141; EG-NEXT: MAX_INT * T0.Z, T1.Z, T0.Z,142; EG-NEXT: MAX_INT * T0.Y, T1.Y, T0.Y,143; EG-NEXT: MAX_INT T0.X, T1.X, T0.X,144; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,145; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)146 %tid = call i32 @llvm.amdgcn.workitem.id.x()147 %gep.in = getelementptr inbounds <4 x i32>, ptr addrspace(1) %bptr, i32 %tid148 %a = load <4 x i32>, ptr addrspace(1) %aptr, align 4149 %b = load <4 x i32>, ptr addrspace(1) %gep.in, align 4150 %cmp = icmp sge <4 x i32> %a, %b151 %val = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b152 store <4 x i32> %val, ptr addrspace(1) %out, align 4153 ret void154}155 156define amdgpu_kernel void @s_test_imax_sge_i32(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {157; SI-LABEL: s_test_imax_sge_i32:158; SI: ; %bb.0:159; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9160; SI-NEXT: s_waitcnt lgkmcnt(0)161; SI-NEXT: s_mov_b64 s[4:5], s[2:3]162; SI-NEXT: s_max_i32 s4, s4, s5163; SI-NEXT: s_mov_b32 s3, 0xf000164; SI-NEXT: s_mov_b32 s2, -1165; SI-NEXT: v_mov_b32_e32 v0, s4166; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0167; SI-NEXT: s_endpgm168;169; GFX1250-LABEL: s_test_imax_sge_i32:170; GFX1250: ; %bb.0:171; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1172; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24173; GFX1250-NEXT: v_mov_b32_e32 v0, 0174; GFX1250-NEXT: s_wait_kmcnt 0x0175; GFX1250-NEXT: s_max_i32 s2, s2, s3176; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)177; GFX1250-NEXT: v_mov_b32_e32 v1, s2178; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]179; GFX1250-NEXT: s_endpgm180;181; EG-LABEL: s_test_imax_sge_i32:182; EG: ; %bb.0:183; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]184; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1185; EG-NEXT: CF_END186; EG-NEXT: PAD187; EG-NEXT: ALU clause starting at 4:188; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,189; EG-NEXT: MAX_INT * T1.X, KC0[2].Z, KC0[2].W,190; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)191 %cmp = icmp sge i32 %a, %b192 %val = select i1 %cmp, i32 %a, i32 %b193 store i32 %val, ptr addrspace(1) %out, align 4194 ret void195}196 197define amdgpu_kernel void @s_test_imax_sge_imm_i32(ptr addrspace(1) %out, i32 %a) nounwind {198; SI-LABEL: s_test_imax_sge_imm_i32:199; SI: ; %bb.0:200; SI-NEXT: s_load_dword s6, s[4:5], 0xb201; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9202; SI-NEXT: s_mov_b32 s3, 0xf000203; SI-NEXT: s_mov_b32 s2, -1204; SI-NEXT: s_waitcnt lgkmcnt(0)205; SI-NEXT: s_max_i32 s4, s6, 9206; SI-NEXT: v_mov_b32_e32 v0, s4207; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0208; SI-NEXT: s_endpgm209;210; GFX1250-LABEL: s_test_imax_sge_imm_i32:211; GFX1250: ; %bb.0:212; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1213; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24214; GFX1250-NEXT: v_mov_b32_e32 v0, 0215; GFX1250-NEXT: s_wait_kmcnt 0x0216; GFX1250-NEXT: s_max_i32 s2, s2, 9217; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)218; GFX1250-NEXT: v_mov_b32_e32 v1, s2219; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]220; GFX1250-NEXT: s_endpgm221;222; EG-LABEL: s_test_imax_sge_imm_i32:223; EG: ; %bb.0:224; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]225; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1226; EG-NEXT: CF_END227; EG-NEXT: PAD228; EG-NEXT: ALU clause starting at 4:229; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,230; EG-NEXT: MAX_INT * T1.X, KC0[2].Z, literal.y,231; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)232 %cmp = icmp sge i32 %a, 9233 %val = select i1 %cmp, i32 %a, i32 9234 store i32 %val, ptr addrspace(1) %out, align 4235 ret void236}237 238define amdgpu_kernel void @v_test_imax_sge_i8(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {239; SI-LABEL: v_test_imax_sge_i8:240; SI: ; %bb.0:241; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9242; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd243; SI-NEXT: s_mov_b32 s7, 0xf000244; SI-NEXT: s_mov_b32 s6, -1245; SI-NEXT: s_mov_b32 s14, s6246; SI-NEXT: s_waitcnt lgkmcnt(0)247; SI-NEXT: s_mov_b32 s12, s2248; SI-NEXT: s_mov_b32 s13, s3249; SI-NEXT: s_mov_b32 s15, s7250; SI-NEXT: s_mov_b32 s10, s6251; SI-NEXT: s_mov_b32 s11, s7252; SI-NEXT: buffer_load_sbyte v0, off, s[12:15], 0253; SI-NEXT: buffer_load_sbyte v1, off, s[8:11], 0254; SI-NEXT: s_mov_b32 s4, s0255; SI-NEXT: s_mov_b32 s5, s1256; SI-NEXT: s_waitcnt vmcnt(0)257; SI-NEXT: v_max_i32_e32 v0, v0, v1258; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0259; SI-NEXT: s_endpgm260;261; GFX1250-LABEL: v_test_imax_sge_i8:262; GFX1250: ; %bb.0:263; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1264; GFX1250-NEXT: s_clause 0x1265; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24266; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34267; GFX1250-NEXT: v_mov_b32_e32 v0, 0268; GFX1250-NEXT: s_wait_kmcnt 0x0269; GFX1250-NEXT: s_load_i8 s4, s[2:3], 0x0270; GFX1250-NEXT: s_load_i8 s5, s[6:7], 0x0271; GFX1250-NEXT: s_wait_kmcnt 0x0272; GFX1250-NEXT: s_max_i32 s2, s4, s5273; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)274; GFX1250-NEXT: v_mov_b32_e32 v1, s2275; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]276; GFX1250-NEXT: s_endpgm277;278; EG-LABEL: v_test_imax_sge_i8:279; EG: ; %bb.0:280; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]281; EG-NEXT: TEX 0 @8282; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]283; EG-NEXT: TEX 0 @10284; EG-NEXT: ALU 14, @14, KC0[CB0:0-32], KC1[]285; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X286; EG-NEXT: CF_END287; EG-NEXT: PAD288; EG-NEXT: Fetch clause starting at 8:289; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1290; EG-NEXT: Fetch clause starting at 10:291; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1292; EG-NEXT: ALU clause starting at 12:293; EG-NEXT: MOV * T0.X, KC0[2].W,294; EG-NEXT: ALU clause starting at 13:295; EG-NEXT: MOV * T1.X, KC0[2].Z,296; EG-NEXT: ALU clause starting at 14:297; EG-NEXT: BFE_INT T0.Z, T0.X, 0.0, literal.x,298; EG-NEXT: BFE_INT T0.W, T1.X, 0.0, literal.x, BS:VEC_120/SCL_212299; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,300; EG-NEXT: 8(1.121039e-44), 3(4.203895e-45)301; EG-NEXT: MAX_INT * T0.W, PV.W, PV.Z,302; EG-NEXT: AND_INT T0.W, PV.W, literal.x,303; EG-NEXT: LSHL * T1.W, T1.W, literal.y,304; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)305; EG-NEXT: LSHL T0.X, PV.W, PS,306; EG-NEXT: LSHL * T0.W, literal.x, PS,307; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)308; EG-NEXT: MOV T0.Y, 0.0,309; EG-NEXT: MOV * T0.Z, 0.0,310; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,311; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)312 %a = load i8, ptr addrspace(1) %aptr, align 1313 %b = load i8, ptr addrspace(1) %bptr, align 1314 %cmp = icmp sge i8 %a, %b315 %val = select i1 %cmp, i8 %a, i8 %b316 store i8 %val, ptr addrspace(1) %out, align 1317 ret void318}319 320define amdgpu_kernel void @s_test_imax_sgt_imm_i32(ptr addrspace(1) %out, i32 %a) nounwind {321; SI-LABEL: s_test_imax_sgt_imm_i32:322; SI: ; %bb.0:323; SI-NEXT: s_load_dword s6, s[4:5], 0xb324; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9325; SI-NEXT: s_mov_b32 s3, 0xf000326; SI-NEXT: s_mov_b32 s2, -1327; SI-NEXT: s_waitcnt lgkmcnt(0)328; SI-NEXT: s_max_i32 s4, s6, 9329; SI-NEXT: v_mov_b32_e32 v0, s4330; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0331; SI-NEXT: s_endpgm332;333; GFX1250-LABEL: s_test_imax_sgt_imm_i32:334; GFX1250: ; %bb.0:335; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1336; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x24337; GFX1250-NEXT: v_mov_b32_e32 v0, 0338; GFX1250-NEXT: s_wait_kmcnt 0x0339; GFX1250-NEXT: s_max_i32 s2, s2, 9340; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)341; GFX1250-NEXT: v_mov_b32_e32 v1, s2342; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]343; GFX1250-NEXT: s_endpgm344;345; EG-LABEL: s_test_imax_sgt_imm_i32:346; EG: ; %bb.0:347; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]348; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1349; EG-NEXT: CF_END350; EG-NEXT: PAD351; EG-NEXT: ALU clause starting at 4:352; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,353; EG-NEXT: MAX_INT * T1.X, KC0[2].Z, literal.y,354; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)355 %cmp = icmp sgt i32 %a, 9356 %val = select i1 %cmp, i32 %a, i32 9357 store i32 %val, ptr addrspace(1) %out, align 4358 ret void359}360 361define amdgpu_kernel void @s_test_imax_sgt_imm_v2i32(ptr addrspace(1) %out, <2 x i32> %a) nounwind {362; SI-LABEL: s_test_imax_sgt_imm_v2i32:363; SI: ; %bb.0:364; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9365; SI-NEXT: s_waitcnt lgkmcnt(0)366; SI-NEXT: s_mov_b64 s[4:5], s[2:3]367; SI-NEXT: s_max_i32 s5, s5, 9368; SI-NEXT: s_max_i32 s4, s4, 9369; SI-NEXT: s_mov_b32 s3, 0xf000370; SI-NEXT: s_mov_b32 s2, -1371; SI-NEXT: v_mov_b32_e32 v0, s4372; SI-NEXT: v_mov_b32_e32 v1, s5373; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0374; SI-NEXT: s_endpgm375;376; GFX1250-LABEL: s_test_imax_sgt_imm_v2i32:377; GFX1250: ; %bb.0:378; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1379; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24380; GFX1250-NEXT: v_mov_b32_e32 v2, 0381; GFX1250-NEXT: s_wait_kmcnt 0x0382; GFX1250-NEXT: s_max_i32 s2, s2, 9383; GFX1250-NEXT: s_max_i32 s3, s3, 9384; GFX1250-NEXT: v_mov_b32_e32 v0, s2385; GFX1250-NEXT: v_mov_b32_e32 v1, s3386; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]387; GFX1250-NEXT: s_endpgm388;389; EG-LABEL: s_test_imax_sgt_imm_v2i32:390; EG: ; %bb.0:391; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]392; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1393; EG-NEXT: CF_END394; EG-NEXT: PAD395; EG-NEXT: ALU clause starting at 4:396; EG-NEXT: MAX_INT * T0.Y, KC0[3].X, literal.x,397; EG-NEXT: 9(1.261169e-44), 0(0.000000e+00)398; EG-NEXT: MAX_INT T0.X, KC0[2].W, literal.x,399; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,400; EG-NEXT: 9(1.261169e-44), 2(2.802597e-45)401 %cmp = icmp sgt <2 x i32> %a, <i32 9, i32 9>402 %val = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> <i32 9, i32 9>403 store <2 x i32> %val, ptr addrspace(1) %out, align 4404 ret void405}406 407define amdgpu_kernel void @v_test_imax_sgt_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {408; SI-LABEL: v_test_imax_sgt_i32:409; SI: ; %bb.0:410; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd411; SI-NEXT: s_mov_b32 s7, 0xf000412; SI-NEXT: s_mov_b32 s2, 0413; SI-NEXT: s_mov_b32 s3, s7414; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0415; SI-NEXT: v_mov_b32_e32 v1, 0416; SI-NEXT: s_waitcnt lgkmcnt(0)417; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64418; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9419; SI-NEXT: s_mov_b32 s6, -1420; SI-NEXT: s_waitcnt lgkmcnt(0)421; SI-NEXT: s_load_dword s2, s[2:3], 0x0422; SI-NEXT: s_mov_b32 s4, s0423; SI-NEXT: s_mov_b32 s5, s1424; SI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)425; SI-NEXT: v_max_i32_e32 v0, s2, v0426; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0427; SI-NEXT: s_endpgm428;429; GFX1250-LABEL: v_test_imax_sgt_i32:430; GFX1250: ; %bb.0:431; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1432; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34433; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0434; GFX1250-NEXT: v_mov_b32_e32 v1, 0435; GFX1250-NEXT: s_wait_kmcnt 0x0436; GFX1250-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset437; GFX1250-NEXT: s_wait_xcnt 0x0438; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24439; GFX1250-NEXT: s_wait_kmcnt 0x0440; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0441; GFX1250-NEXT: s_wait_loadcnt 0x0442; GFX1250-NEXT: s_wait_kmcnt 0x0443; GFX1250-NEXT: v_max_i32_e32 v0, s2, v0444; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]445; GFX1250-NEXT: s_endpgm446;447; EG-LABEL: v_test_imax_sgt_i32:448; EG: ; %bb.0:449; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]450; EG-NEXT: TEX 1 @6451; EG-NEXT: ALU 2, @14, KC0[CB0:0-32], KC1[]452; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1453; EG-NEXT: CF_END454; EG-NEXT: PAD455; EG-NEXT: Fetch clause starting at 6:456; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1457; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1458; EG-NEXT: ALU clause starting at 10:459; EG-NEXT: MOV T1.X, KC0[2].Z,460; EG-NEXT: LSHL * T0.W, T0.X, literal.x,461; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)462; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,463; EG-NEXT: ALU clause starting at 14:464; EG-NEXT: MAX_INT T0.X, T1.X, T0.X,465; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,466; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)467 %tid = call i32 @llvm.amdgcn.workitem.id.x()468 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid469 %a = load i32, ptr addrspace(1) %aptr, align 4470 %b = load i32, ptr addrspace(1) %gep.in, align 4471 %cmp = icmp sgt i32 %a, %b472 %val = select i1 %cmp, i32 %a, i32 %b473 store i32 %val, ptr addrspace(1) %out, align 4474 ret void475}476 477define amdgpu_kernel void @s_test_imax_sgt_i32(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {478; SI-LABEL: s_test_imax_sgt_i32:479; SI: ; %bb.0:480; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9481; SI-NEXT: s_waitcnt lgkmcnt(0)482; SI-NEXT: s_mov_b64 s[4:5], s[2:3]483; SI-NEXT: s_max_i32 s4, s4, s5484; SI-NEXT: s_mov_b32 s3, 0xf000485; SI-NEXT: s_mov_b32 s2, -1486; SI-NEXT: v_mov_b32_e32 v0, s4487; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0488; SI-NEXT: s_endpgm489;490; GFX1250-LABEL: s_test_imax_sgt_i32:491; GFX1250: ; %bb.0:492; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1493; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24494; GFX1250-NEXT: v_mov_b32_e32 v0, 0495; GFX1250-NEXT: s_wait_kmcnt 0x0496; GFX1250-NEXT: s_max_i32 s2, s2, s3497; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)498; GFX1250-NEXT: v_mov_b32_e32 v1, s2499; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]500; GFX1250-NEXT: s_endpgm501;502; EG-LABEL: s_test_imax_sgt_i32:503; EG: ; %bb.0:504; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]505; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1506; EG-NEXT: CF_END507; EG-NEXT: PAD508; EG-NEXT: ALU clause starting at 4:509; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,510; EG-NEXT: MAX_INT * T1.X, KC0[2].Z, KC0[2].W,511; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)512 %cmp = icmp sgt i32 %a, %b513 %val = select i1 %cmp, i32 %a, i32 %b514 store i32 %val, ptr addrspace(1) %out, align 4515 ret void516}517 518define amdgpu_kernel void @v_test_umax_uge_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {519; SI-LABEL: v_test_umax_uge_i32:520; SI: ; %bb.0:521; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd522; SI-NEXT: s_mov_b32 s7, 0xf000523; SI-NEXT: s_mov_b32 s2, 0524; SI-NEXT: s_mov_b32 s3, s7525; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0526; SI-NEXT: v_mov_b32_e32 v1, 0527; SI-NEXT: s_waitcnt lgkmcnt(0)528; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64529; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9530; SI-NEXT: s_mov_b32 s6, -1531; SI-NEXT: s_waitcnt lgkmcnt(0)532; SI-NEXT: s_load_dword s2, s[2:3], 0x0533; SI-NEXT: s_mov_b32 s4, s0534; SI-NEXT: s_mov_b32 s5, s1535; SI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)536; SI-NEXT: v_max_u32_e32 v0, s2, v0537; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0538; SI-NEXT: s_endpgm539;540; GFX1250-LABEL: v_test_umax_uge_i32:541; GFX1250: ; %bb.0:542; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1543; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34544; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0545; GFX1250-NEXT: v_mov_b32_e32 v1, 0546; GFX1250-NEXT: s_wait_kmcnt 0x0547; GFX1250-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset548; GFX1250-NEXT: s_wait_xcnt 0x0549; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24550; GFX1250-NEXT: s_wait_kmcnt 0x0551; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x0552; GFX1250-NEXT: s_wait_loadcnt 0x0553; GFX1250-NEXT: s_wait_kmcnt 0x0554; GFX1250-NEXT: v_max_u32_e32 v0, s2, v0555; GFX1250-NEXT: global_store_b32 v1, v0, s[0:1]556; GFX1250-NEXT: s_endpgm557;558; EG-LABEL: v_test_umax_uge_i32:559; EG: ; %bb.0:560; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]561; EG-NEXT: TEX 1 @6562; EG-NEXT: ALU 2, @14, KC0[CB0:0-32], KC1[]563; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1564; EG-NEXT: CF_END565; EG-NEXT: PAD566; EG-NEXT: Fetch clause starting at 6:567; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1568; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1569; EG-NEXT: ALU clause starting at 10:570; EG-NEXT: MOV T1.X, KC0[2].Z,571; EG-NEXT: LSHL * T0.W, T0.X, literal.x,572; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)573; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,574; EG-NEXT: ALU clause starting at 14:575; EG-NEXT: MAX_UINT T0.X, T1.X, T0.X,576; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,577; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)578 %tid = call i32 @llvm.amdgcn.workitem.id.x()579 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid580 %a = load i32, ptr addrspace(1) %aptr, align 4581 %b = load i32, ptr addrspace(1) %gep.in, align 4582 %cmp = icmp uge i32 %a, %b583 %val = select i1 %cmp, i32 %a, i32 %b584 store i32 %val, ptr addrspace(1) %out, align 4585 ret void586}587 588define amdgpu_kernel void @s_test_umax_uge_i32(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {589; SI-LABEL: s_test_umax_uge_i32:590; SI: ; %bb.0:591; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9592; SI-NEXT: s_waitcnt lgkmcnt(0)593; SI-NEXT: s_mov_b64 s[4:5], s[2:3]594; SI-NEXT: s_max_u32 s4, s4, s5595; SI-NEXT: s_mov_b32 s3, 0xf000596; SI-NEXT: s_mov_b32 s2, -1597; SI-NEXT: v_mov_b32_e32 v0, s4598; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0599; SI-NEXT: s_endpgm600;601; GFX1250-LABEL: s_test_umax_uge_i32:602; GFX1250: ; %bb.0:603; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1604; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24605; GFX1250-NEXT: v_mov_b32_e32 v0, 0606; GFX1250-NEXT: s_wait_kmcnt 0x0607; GFX1250-NEXT: s_max_u32 s2, s2, s3608; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)609; GFX1250-NEXT: v_mov_b32_e32 v1, s2610; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]611; GFX1250-NEXT: s_endpgm612;613; EG-LABEL: s_test_umax_uge_i32:614; EG: ; %bb.0:615; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]616; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1617; EG-NEXT: CF_END618; EG-NEXT: PAD619; EG-NEXT: ALU clause starting at 4:620; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,621; EG-NEXT: MAX_UINT * T1.X, KC0[2].Z, KC0[2].W,622; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)623 %cmp = icmp uge i32 %a, %b624 %val = select i1 %cmp, i32 %a, i32 %b625 store i32 %val, ptr addrspace(1) %out, align 4626 ret void627}628 629define amdgpu_kernel void @s_test_umax_uge_v3i32(ptr addrspace(1) %out, <3 x i32> %a, <3 x i32> %b) nounwind {630; SI-LABEL: s_test_umax_uge_v3i32:631; SI: ; %bb.0:632; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd633; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9634; SI-NEXT: s_mov_b32 s3, 0xf000635; SI-NEXT: s_mov_b32 s2, -1636; SI-NEXT: s_waitcnt lgkmcnt(0)637; SI-NEXT: s_max_u32 s6, s10, s14638; SI-NEXT: s_max_u32 s4, s9, s13639; SI-NEXT: s_max_u32 s5, s8, s12640; SI-NEXT: v_mov_b32_e32 v0, s6641; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8642; SI-NEXT: s_waitcnt expcnt(0)643; SI-NEXT: v_mov_b32_e32 v0, s5644; SI-NEXT: v_mov_b32_e32 v1, s4645; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0646; SI-NEXT: s_endpgm647;648; GFX1250-LABEL: s_test_umax_uge_v3i32:649; GFX1250: ; %bb.0:650; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1651; GFX1250-NEXT: s_clause 0x1652; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x34653; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24654; GFX1250-NEXT: v_mov_b32_e32 v3, 0655; GFX1250-NEXT: s_wait_kmcnt 0x0656; GFX1250-NEXT: s_max_u32 s2, s10, s14657; GFX1250-NEXT: s_max_u32 s3, s8, s12658; GFX1250-NEXT: s_max_u32 s4, s9, s13659; GFX1250-NEXT: v_mov_b32_e32 v0, s3660; GFX1250-NEXT: v_mov_b32_e32 v1, s4661; GFX1250-NEXT: v_mov_b32_e32 v2, s2662; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[0:1]663; GFX1250-NEXT: s_endpgm664;665; EG-LABEL: s_test_umax_uge_v3i32:666; EG: ; %bb.0:667; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]668; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0669; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1670; EG-NEXT: CF_END671; EG-NEXT: ALU clause starting at 4:672; EG-NEXT: MAX_UINT * T0.Y, KC0[3].Z, KC0[4].Z,673; EG-NEXT: MAX_UINT * T0.X, KC0[3].Y, KC0[4].Y,674; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,675; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,676; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)677; EG-NEXT: LSHR T2.X, PV.W, literal.x,678; EG-NEXT: MAX_UINT * T3.X, KC0[3].W, KC0[4].W,679; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)680 %cmp = icmp uge <3 x i32> %a, %b681 %val = select <3 x i1> %cmp, <3 x i32> %a, <3 x i32> %b682 store <3 x i32> %val, ptr addrspace(1) %out, align 4683 ret void684}685 686define amdgpu_kernel void @v_test_umax_uge_i8(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {687; SI-LABEL: v_test_umax_uge_i8:688; SI: ; %bb.0:689; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9690; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd691; SI-NEXT: s_mov_b32 s7, 0xf000692; SI-NEXT: s_mov_b32 s6, -1693; SI-NEXT: s_mov_b32 s14, s6694; SI-NEXT: s_waitcnt lgkmcnt(0)695; SI-NEXT: s_mov_b32 s12, s2696; SI-NEXT: s_mov_b32 s13, s3697; SI-NEXT: s_mov_b32 s15, s7698; SI-NEXT: s_mov_b32 s10, s6699; SI-NEXT: s_mov_b32 s11, s7700; SI-NEXT: buffer_load_ubyte v0, off, s[12:15], 0701; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0702; SI-NEXT: s_mov_b32 s4, s0703; SI-NEXT: s_mov_b32 s5, s1704; SI-NEXT: s_waitcnt vmcnt(0)705; SI-NEXT: v_max_u32_e32 v0, v0, v1706; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0707; SI-NEXT: s_endpgm708;709; GFX1250-LABEL: v_test_umax_uge_i8:710; GFX1250: ; %bb.0:711; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1712; GFX1250-NEXT: s_clause 0x1713; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24714; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x34715; GFX1250-NEXT: v_mov_b32_e32 v0, 0716; GFX1250-NEXT: s_wait_kmcnt 0x0717; GFX1250-NEXT: s_load_u8 s4, s[2:3], 0x0718; GFX1250-NEXT: s_load_u8 s5, s[6:7], 0x0719; GFX1250-NEXT: s_wait_kmcnt 0x0720; GFX1250-NEXT: s_max_u32 s2, s4, s5721; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)722; GFX1250-NEXT: v_mov_b32_e32 v1, s2723; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]724; GFX1250-NEXT: s_endpgm725;726; EG-LABEL: v_test_umax_uge_i8:727; EG: ; %bb.0:728; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]729; EG-NEXT: TEX 1 @6730; EG-NEXT: ALU 11, @12, KC0[CB0:0-32], KC1[]731; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X732; EG-NEXT: CF_END733; EG-NEXT: PAD734; EG-NEXT: Fetch clause starting at 6:735; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #1736; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1737; EG-NEXT: ALU clause starting at 10:738; EG-NEXT: MOV T0.X, KC0[2].Z,739; EG-NEXT: MOV * T1.X, KC0[2].W,740; EG-NEXT: ALU clause starting at 12:741; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,742; EG-NEXT: MAX_UINT * T1.W, T0.X, T1.X,743; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)744; EG-NEXT: LSHL * T0.W, PV.W, literal.x,745; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)746; EG-NEXT: LSHL T0.X, T1.W, PV.W,747; EG-NEXT: LSHL * T0.W, literal.x, PV.W,748; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)749; EG-NEXT: MOV T0.Y, 0.0,750; EG-NEXT: MOV * T0.Z, 0.0,751; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,752; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)753 %a = load i8, ptr addrspace(1) %aptr, align 1754 %b = load i8, ptr addrspace(1) %bptr, align 1755 %cmp = icmp uge i8 %a, %b756 %val = select i1 %cmp, i8 %a, i8 %b757 store i8 %val, ptr addrspace(1) %out, align 1758 ret void759}760 761define amdgpu_kernel void @v_test_umax_ugt_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) nounwind {762; SI-LABEL: v_test_umax_ugt_i32:763; SI: ; %bb.0:764; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd765; SI-NEXT: s_mov_b32 s7, 0xf000766; SI-NEXT: s_mov_b32 s2, 0767; SI-NEXT: s_mov_b32 s3, s7768; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0769; SI-NEXT: v_mov_b32_e32 v1, 0770; SI-NEXT: s_waitcnt lgkmcnt(0)771; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64772; SI-NEXT: s_load_dword s0, s[0:1], 0x0773; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9774; SI-NEXT: s_mov_b32 s6, -1775; SI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)776; SI-NEXT: v_max_u32_e32 v0, s0, v0777; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0778; SI-NEXT: s_endpgm779;780; GFX1250-LABEL: v_test_umax_ugt_i32:781; GFX1250: ; %bb.0:782; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1783; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x34784; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0785; GFX1250-NEXT: v_mov_b32_e32 v1, 0786; GFX1250-NEXT: s_wait_kmcnt 0x0787; GFX1250-NEXT: s_load_b32 s6, s[0:1], 0x0788; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x24789; GFX1250-NEXT: global_load_b32 v0, v0, s[0:1] scale_offset790; GFX1250-NEXT: s_wait_loadcnt 0x0791; GFX1250-NEXT: s_wait_kmcnt 0x0792; GFX1250-NEXT: v_max_u32_e32 v0, s6, v0793; GFX1250-NEXT: global_store_b32 v1, v0, s[2:3]794; GFX1250-NEXT: s_endpgm795;796; EG-LABEL: v_test_umax_ugt_i32:797; EG: ; %bb.0:798; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]799; EG-NEXT: TEX 1 @6800; EG-NEXT: ALU 2, @14, KC0[CB0:0-32], KC1[]801; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1802; EG-NEXT: CF_END803; EG-NEXT: PAD804; EG-NEXT: Fetch clause starting at 6:805; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1806; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1807; EG-NEXT: ALU clause starting at 10:808; EG-NEXT: MOV T1.X, KC0[2].W,809; EG-NEXT: LSHL * T0.W, T0.X, literal.x,810; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)811; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,812; EG-NEXT: ALU clause starting at 14:813; EG-NEXT: MAX_UINT T0.X, T0.X, T1.X,814; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,815; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)816 %tid = call i32 @llvm.amdgcn.workitem.id.x()817 %gep.in = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid818 %a = load i32, ptr addrspace(1) %gep.in, align 4819 %b = load i32, ptr addrspace(1) %bptr, align 4820 %cmp = icmp ugt i32 %a, %b821 %val = select i1 %cmp, i32 %a, i32 %b822 store i32 %val, ptr addrspace(1) %out, align 4823 ret void824}825 826define amdgpu_kernel void @s_test_umax_ugt_i32(ptr addrspace(1) %out, i32 %a, i32 %b) nounwind {827; SI-LABEL: s_test_umax_ugt_i32:828; SI: ; %bb.0:829; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9830; SI-NEXT: s_waitcnt lgkmcnt(0)831; SI-NEXT: s_mov_b64 s[4:5], s[2:3]832; SI-NEXT: s_max_u32 s4, s4, s5833; SI-NEXT: s_mov_b32 s3, 0xf000834; SI-NEXT: s_mov_b32 s2, -1835; SI-NEXT: v_mov_b32_e32 v0, s4836; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0837; SI-NEXT: s_endpgm838;839; GFX1250-LABEL: s_test_umax_ugt_i32:840; GFX1250: ; %bb.0:841; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1842; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24843; GFX1250-NEXT: v_mov_b32_e32 v0, 0844; GFX1250-NEXT: s_wait_kmcnt 0x0845; GFX1250-NEXT: s_max_u32 s2, s2, s3846; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)847; GFX1250-NEXT: v_mov_b32_e32 v1, s2848; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]849; GFX1250-NEXT: s_endpgm850;851; EG-LABEL: s_test_umax_ugt_i32:852; EG: ; %bb.0:853; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]854; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1855; EG-NEXT: CF_END856; EG-NEXT: PAD857; EG-NEXT: ALU clause starting at 4:858; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,859; EG-NEXT: MAX_UINT * T1.X, KC0[2].Z, KC0[2].W,860; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)861 %cmp = icmp ugt i32 %a, %b862 %val = select i1 %cmp, i32 %a, i32 %b863 store i32 %val, ptr addrspace(1) %out, align 4864 ret void865}866 867define amdgpu_kernel void @s_test_umax_ugt_imm_v2i32(ptr addrspace(1) %out, <2 x i32> %a) nounwind {868; SI-LABEL: s_test_umax_ugt_imm_v2i32:869; SI: ; %bb.0:870; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9871; SI-NEXT: s_waitcnt lgkmcnt(0)872; SI-NEXT: s_mov_b64 s[4:5], s[2:3]873; SI-NEXT: s_max_u32 s5, s5, 23874; SI-NEXT: s_max_u32 s4, s4, 15875; SI-NEXT: s_mov_b32 s3, 0xf000876; SI-NEXT: s_mov_b32 s2, -1877; SI-NEXT: v_mov_b32_e32 v0, s4878; SI-NEXT: v_mov_b32_e32 v1, s5879; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0880; SI-NEXT: s_endpgm881;882; GFX1250-LABEL: s_test_umax_ugt_imm_v2i32:883; GFX1250: ; %bb.0:884; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1885; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24886; GFX1250-NEXT: v_mov_b32_e32 v2, 0887; GFX1250-NEXT: s_wait_kmcnt 0x0888; GFX1250-NEXT: s_max_u32 s2, s2, 15889; GFX1250-NEXT: s_max_u32 s3, s3, 23890; GFX1250-NEXT: v_mov_b32_e32 v0, s2891; GFX1250-NEXT: v_mov_b32_e32 v1, s3892; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]893; GFX1250-NEXT: s_endpgm894;895; EG-LABEL: s_test_umax_ugt_imm_v2i32:896; EG: ; %bb.0:897; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]898; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1899; EG-NEXT: CF_END900; EG-NEXT: PAD901; EG-NEXT: ALU clause starting at 4:902; EG-NEXT: MAX_UINT * T0.Y, KC0[3].X, literal.x,903; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)904; EG-NEXT: MAX_UINT T0.X, KC0[2].W, literal.x,905; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,906; EG-NEXT: 15(2.101948e-44), 2(2.802597e-45)907 %cmp = icmp ugt <2 x i32> %a, <i32 15, i32 23>908 %val = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> <i32 15, i32 23>909 store <2 x i32> %val, ptr addrspace(1) %out, align 4910 ret void911}912 913; Make sure redundant and removed914 915define amdgpu_kernel void @simplify_demanded_bits_test_umax_ugt_i16(ptr addrspace(1) %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) nounwind {916; SI-LABEL: simplify_demanded_bits_test_umax_ugt_i16:917; SI: ; %bb.0:918; SI-NEXT: s_load_dword s6, s[4:5], 0x13919; SI-NEXT: s_load_dword s7, s[4:5], 0x1c920; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9921; SI-NEXT: s_mov_b32 s3, 0xf000922; SI-NEXT: s_mov_b32 s2, -1923; SI-NEXT: s_waitcnt lgkmcnt(0)924; SI-NEXT: s_and_b32 s4, s6, 0xffff925; SI-NEXT: s_and_b32 s5, s7, 0xffff926; SI-NEXT: s_max_u32 s4, s4, s5927; SI-NEXT: v_mov_b32_e32 v0, s4928; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0929; SI-NEXT: s_endpgm930;931; GFX1250-LABEL: simplify_demanded_bits_test_umax_ugt_i16:932; GFX1250: ; %bb.0:933; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1934; GFX1250-NEXT: s_clause 0x2935; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x4c936; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x70937; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24938; GFX1250-NEXT: v_mov_b32_e32 v0, 0939; GFX1250-NEXT: s_wait_kmcnt 0x0940; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff941; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff942; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)943; GFX1250-NEXT: s_max_u32 s2, s2, s3944; GFX1250-NEXT: v_mov_b32_e32 v1, s2945; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]946; GFX1250-NEXT: s_endpgm947;948; EG-LABEL: simplify_demanded_bits_test_umax_ugt_i16:949; EG: ; %bb.0:950; EG-NEXT: ALU 0, @10, KC0[], KC1[]951; EG-NEXT: TEX 1 @6952; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]953; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1954; EG-NEXT: CF_END955; EG-NEXT: PAD956; EG-NEXT: Fetch clause starting at 6:957; EG-NEXT: VTX_READ_16 T1.X, T0.X, 72, #3958; EG-NEXT: VTX_READ_16 T0.X, T0.X, 108, #3959; EG-NEXT: ALU clause starting at 10:960; EG-NEXT: MOV * T0.X, 0.0,961; EG-NEXT: ALU clause starting at 11:962; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,963; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_212964; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)965; EG-NEXT: MAX_UINT T0.X, PV.Z, PV.W,966; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,967; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)968 %a.ext = zext i16 %a to i32969 %b.ext = zext i16 %b to i32970 %cmp = icmp ugt i32 %a.ext, %b.ext971 %val = select i1 %cmp, i32 %a.ext, i32 %b.ext972 %mask = and i32 %val, 65535973 store i32 %mask, ptr addrspace(1) %out974 ret void975}976 977; Make sure redundant sign_extend_inreg removed.978 979define amdgpu_kernel void @simplify_demanded_bits_test_max_slt_i16(ptr addrspace(1) %out, [8 x i32], i16 signext %a, [8 x i32], i16 signext %b) nounwind {980; SI-LABEL: simplify_demanded_bits_test_max_slt_i16:981; SI: ; %bb.0:982; SI-NEXT: s_load_dword s6, s[4:5], 0x13983; SI-NEXT: s_load_dword s7, s[4:5], 0x1c984; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9985; SI-NEXT: s_mov_b32 s3, 0xf000986; SI-NEXT: s_mov_b32 s2, -1987; SI-NEXT: s_waitcnt lgkmcnt(0)988; SI-NEXT: s_sext_i32_i16 s4, s6989; SI-NEXT: s_sext_i32_i16 s5, s7990; SI-NEXT: s_max_i32 s4, s4, s5991; SI-NEXT: v_mov_b32_e32 v0, s4992; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0993; SI-NEXT: s_endpgm994;995; GFX1250-LABEL: simplify_demanded_bits_test_max_slt_i16:996; GFX1250: ; %bb.0:997; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1998; GFX1250-NEXT: s_clause 0x2999; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x4c1000; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x701001; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x241002; GFX1250-NEXT: v_mov_b32_e32 v0, 01003; GFX1250-NEXT: s_wait_kmcnt 0x01004; GFX1250-NEXT: s_sext_i32_i16 s2, s21005; GFX1250-NEXT: s_sext_i32_i16 s3, s31006; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1007; GFX1250-NEXT: s_max_i32 s2, s2, s31008; GFX1250-NEXT: v_mov_b32_e32 v1, s21009; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]1010; GFX1250-NEXT: s_endpgm1011;1012; EG-LABEL: simplify_demanded_bits_test_max_slt_i16:1013; EG: ; %bb.0:1014; EG-NEXT: ALU 0, @10, KC0[], KC1[]1015; EG-NEXT: TEX 1 @61016; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]1017; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11018; EG-NEXT: CF_END1019; EG-NEXT: PAD1020; EG-NEXT: Fetch clause starting at 6:1021; EG-NEXT: VTX_READ_16 T1.X, T0.X, 72, #31022; EG-NEXT: VTX_READ_16 T0.X, T0.X, 108, #31023; EG-NEXT: ALU clause starting at 10:1024; EG-NEXT: MOV * T0.X, 0.0,1025; EG-NEXT: ALU clause starting at 11:1026; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,1027; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_2121028; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1029; EG-NEXT: MAX_INT T0.X, PV.Z, PV.W,1030; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1031; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1032 %a.ext = sext i16 %a to i321033 %b.ext = sext i16 %b to i321034 %cmp = icmp sgt i32 %a.ext, %b.ext1035 %val = select i1 %cmp, i32 %a.ext, i32 %b.ext1036 %shl = shl i32 %val, 161037 %sextinreg = ashr i32 %shl, 161038 store i32 %sextinreg, ptr addrspace(1) %out1039 ret void1040}1041 1042define amdgpu_kernel void @s_test_imax_sge_i16(ptr addrspace(1) %out, [8 x i32], i16 %a, [8 x i32], i16 %b) nounwind {1043; SI-LABEL: s_test_imax_sge_i16:1044; SI: ; %bb.0:1045; SI-NEXT: s_load_dword s6, s[4:5], 0x131046; SI-NEXT: s_load_dword s7, s[4:5], 0x1c1047; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91048; SI-NEXT: s_mov_b32 s3, 0xf0001049; SI-NEXT: s_mov_b32 s2, -11050; SI-NEXT: s_waitcnt lgkmcnt(0)1051; SI-NEXT: s_sext_i32_i16 s4, s61052; SI-NEXT: s_sext_i32_i16 s5, s71053; SI-NEXT: s_max_i32 s4, s4, s51054; SI-NEXT: v_mov_b32_e32 v0, s41055; SI-NEXT: buffer_store_short v0, off, s[0:3], 01056; SI-NEXT: s_endpgm1057;1058; GFX1250-LABEL: s_test_imax_sge_i16:1059; GFX1250: ; %bb.0:1060; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11061; GFX1250-NEXT: s_clause 0x21062; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x701063; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x4c1064; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x241065; GFX1250-NEXT: v_mov_b32_e32 v0, 01066; GFX1250-NEXT: s_wait_kmcnt 0x01067; GFX1250-NEXT: s_sext_i32_i16 s2, s21068; GFX1250-NEXT: s_sext_i32_i16 s3, s31069; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)1070; GFX1250-NEXT: s_max_i32 s2, s3, s21071; GFX1250-NEXT: v_mov_b32_e32 v1, s21072; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]1073; GFX1250-NEXT: s_endpgm1074;1075; EG-LABEL: s_test_imax_sge_i16:1076; EG: ; %bb.0:1077; EG-NEXT: ALU 0, @10, KC0[], KC1[]1078; EG-NEXT: TEX 1 @61079; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]1080; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X1081; EG-NEXT: CF_END1082; EG-NEXT: PAD1083; EG-NEXT: Fetch clause starting at 6:1084; EG-NEXT: VTX_READ_16 T1.X, T0.X, 72, #31085; EG-NEXT: VTX_READ_16 T0.X, T0.X, 108, #31086; EG-NEXT: ALU clause starting at 10:1087; EG-NEXT: MOV * T0.X, 0.0,1088; EG-NEXT: ALU clause starting at 11:1089; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,1090; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_2121091; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,1092; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45)1093; EG-NEXT: MAX_INT * T0.W, PV.Z, PV.W,1094; EG-NEXT: AND_INT T0.W, PV.W, literal.x,1095; EG-NEXT: LSHL * T1.W, T1.W, literal.y,1096; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1097; EG-NEXT: LSHL T0.X, PV.W, PS,1098; EG-NEXT: LSHL * T0.W, literal.x, PS,1099; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1100; EG-NEXT: MOV T0.Y, 0.0,1101; EG-NEXT: MOV * T0.Z, 0.0,1102; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1103; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1104 %cmp = icmp sge i16 %a, %b1105 %val = select i1 %cmp, i16 %a, i16 %b1106 store i16 %val, ptr addrspace(1) %out1107 ret void1108}1109 1110; 64 bit1111 1112define amdgpu_kernel void @test_umax_ugt_i64(ptr addrspace(1) %out, i64 %a, i64 %b) nounwind {1113; SI-LABEL: test_umax_ugt_i64:1114; SI: ; %bb.0:1115; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91116; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1117; SI-NEXT: s_mov_b32 s7, 0xf0001118; SI-NEXT: s_mov_b32 s6, -11119; SI-NEXT: s_waitcnt lgkmcnt(0)1120; SI-NEXT: s_mov_b32 s4, s01121; SI-NEXT: v_mov_b32_e32 v0, s81122; SI-NEXT: v_mov_b32_e32 v1, s91123; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]1124; SI-NEXT: s_mov_b32 s5, s11125; SI-NEXT: s_and_b64 s[0:1], vcc, exec1126; SI-NEXT: s_cselect_b32 s0, s3, s91127; SI-NEXT: s_cselect_b32 s1, s2, s81128; SI-NEXT: v_mov_b32_e32 v0, s11129; SI-NEXT: v_mov_b32_e32 v1, s01130; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01131; SI-NEXT: s_endpgm1132;1133; GFX1250-LABEL: test_umax_ugt_i64:1134; GFX1250: ; %bb.0:1135; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11136; GFX1250-NEXT: s_clause 0x11137; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x241138; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x341139; GFX1250-NEXT: v_mov_b32_e32 v2, 01140; GFX1250-NEXT: s_wait_kmcnt 0x01141; GFX1250-NEXT: v_max_u64 v[0:1], s[2:3], s[6:7]1142; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]1143; GFX1250-NEXT: s_endpgm1144;1145; EG-LABEL: test_umax_ugt_i64:1146; EG: ; %bb.0:1147; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1148; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11149; EG-NEXT: CF_END1150; EG-NEXT: PAD1151; EG-NEXT: ALU clause starting at 4:1152; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,1153; EG-NEXT: SETGT_UINT * T0.W, KC0[3].X, KC0[3].Z,1154; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, KC0[3].Y,1155; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,1156; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,1157; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,1158; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1159; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1160 %tmp = icmp ugt i64 %a, %b1161 %val = select i1 %tmp, i64 %a, i64 %b1162 store i64 %val, ptr addrspace(1) %out, align 81163 ret void1164}1165 1166define amdgpu_kernel void @test_umax_uge_i64(ptr addrspace(1) %out, i64 %a, i64 %b) nounwind {1167; SI-LABEL: test_umax_uge_i64:1168; SI: ; %bb.0:1169; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91170; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1171; SI-NEXT: s_mov_b32 s7, 0xf0001172; SI-NEXT: s_mov_b32 s6, -11173; SI-NEXT: s_waitcnt lgkmcnt(0)1174; SI-NEXT: s_mov_b32 s4, s01175; SI-NEXT: v_mov_b32_e32 v0, s81176; SI-NEXT: v_mov_b32_e32 v1, s91177; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]1178; SI-NEXT: s_mov_b32 s5, s11179; SI-NEXT: s_and_b64 s[0:1], vcc, exec1180; SI-NEXT: s_cselect_b32 s0, s3, s91181; SI-NEXT: s_cselect_b32 s1, s2, s81182; SI-NEXT: v_mov_b32_e32 v0, s11183; SI-NEXT: v_mov_b32_e32 v1, s01184; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01185; SI-NEXT: s_endpgm1186;1187; GFX1250-LABEL: test_umax_uge_i64:1188; GFX1250: ; %bb.0:1189; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11190; GFX1250-NEXT: s_clause 0x11191; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x241192; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x341193; GFX1250-NEXT: v_mov_b32_e32 v2, 01194; GFX1250-NEXT: s_wait_kmcnt 0x01195; GFX1250-NEXT: v_max_u64 v[0:1], s[2:3], s[6:7]1196; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]1197; GFX1250-NEXT: s_endpgm1198;1199; EG-LABEL: test_umax_uge_i64:1200; EG: ; %bb.0:1201; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1202; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11203; EG-NEXT: CF_END1204; EG-NEXT: PAD1205; EG-NEXT: ALU clause starting at 4:1206; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,1207; EG-NEXT: SETGT_UINT * T0.W, KC0[3].X, KC0[3].Z,1208; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, KC0[3].Y,1209; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,1210; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,1211; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,1212; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1213; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1214 %tmp = icmp uge i64 %a, %b1215 %val = select i1 %tmp, i64 %a, i64 %b1216 store i64 %val, ptr addrspace(1) %out, align 81217 ret void1218}1219 1220define amdgpu_kernel void @test_imax_sgt_i64(ptr addrspace(1) %out, i64 %a, i64 %b) nounwind {1221; SI-LABEL: test_imax_sgt_i64:1222; SI: ; %bb.0:1223; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91224; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1225; SI-NEXT: s_mov_b32 s7, 0xf0001226; SI-NEXT: s_mov_b32 s6, -11227; SI-NEXT: s_waitcnt lgkmcnt(0)1228; SI-NEXT: s_mov_b32 s4, s01229; SI-NEXT: v_mov_b32_e32 v0, s81230; SI-NEXT: v_mov_b32_e32 v1, s91231; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]1232; SI-NEXT: s_mov_b32 s5, s11233; SI-NEXT: s_and_b64 s[0:1], vcc, exec1234; SI-NEXT: s_cselect_b32 s0, s3, s91235; SI-NEXT: s_cselect_b32 s1, s2, s81236; SI-NEXT: v_mov_b32_e32 v0, s11237; SI-NEXT: v_mov_b32_e32 v1, s01238; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01239; SI-NEXT: s_endpgm1240;1241; GFX1250-LABEL: test_imax_sgt_i64:1242; GFX1250: ; %bb.0:1243; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11244; GFX1250-NEXT: s_clause 0x11245; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x241246; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x341247; GFX1250-NEXT: v_mov_b32_e32 v2, 01248; GFX1250-NEXT: s_wait_kmcnt 0x01249; GFX1250-NEXT: v_max_i64 v[0:1], s[2:3], s[6:7]1250; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]1251; GFX1250-NEXT: s_endpgm1252;1253; EG-LABEL: test_imax_sgt_i64:1254; EG: ; %bb.0:1255; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1256; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11257; EG-NEXT: CF_END1258; EG-NEXT: PAD1259; EG-NEXT: ALU clause starting at 4:1260; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,1261; EG-NEXT: SETGT_INT * T0.W, KC0[3].X, KC0[3].Z,1262; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, KC0[3].Y,1263; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,1264; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,1265; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,1266; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1267; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1268 %tmp = icmp sgt i64 %a, %b1269 %val = select i1 %tmp, i64 %a, i64 %b1270 store i64 %val, ptr addrspace(1) %out, align 81271 ret void1272}1273 1274define amdgpu_kernel void @test_imax_sge_i64(ptr addrspace(1) %out, i64 %a, i64 %b) nounwind {1275; SI-LABEL: test_imax_sge_i64:1276; SI: ; %bb.0:1277; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x91278; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd1279; SI-NEXT: s_mov_b32 s7, 0xf0001280; SI-NEXT: s_mov_b32 s6, -11281; SI-NEXT: s_waitcnt lgkmcnt(0)1282; SI-NEXT: s_mov_b32 s4, s01283; SI-NEXT: v_mov_b32_e32 v0, s81284; SI-NEXT: v_mov_b32_e32 v1, s91285; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]1286; SI-NEXT: s_mov_b32 s5, s11287; SI-NEXT: s_and_b64 s[0:1], vcc, exec1288; SI-NEXT: s_cselect_b32 s0, s3, s91289; SI-NEXT: s_cselect_b32 s1, s2, s81290; SI-NEXT: v_mov_b32_e32 v0, s11291; SI-NEXT: v_mov_b32_e32 v1, s01292; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 01293; SI-NEXT: s_endpgm1294;1295; GFX1250-LABEL: test_imax_sge_i64:1296; GFX1250: ; %bb.0:1297; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11298; GFX1250-NEXT: s_clause 0x11299; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x241300; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x341301; GFX1250-NEXT: v_mov_b32_e32 v2, 01302; GFX1250-NEXT: s_wait_kmcnt 0x01303; GFX1250-NEXT: v_max_i64 v[0:1], s[2:3], s[6:7]1304; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]1305; GFX1250-NEXT: s_endpgm1306;1307; EG-LABEL: test_imax_sge_i64:1308; EG: ; %bb.0:1309; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1310; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11311; EG-NEXT: CF_END1312; EG-NEXT: PAD1313; EG-NEXT: ALU clause starting at 4:1314; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,1315; EG-NEXT: SETGT_INT * T0.W, KC0[3].X, KC0[3].Z,1316; EG-NEXT: SETGT_UINT * T1.W, KC0[2].W, KC0[3].Y,1317; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,1318; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,1319; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,1320; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1321; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1322 %tmp = icmp sge i64 %a, %b1323 %val = select i1 %tmp, i64 %a, i64 %b1324 store i64 %val, ptr addrspace(1) %out, align 81325 ret void1326}1327 1328declare i32 @llvm.amdgcn.workitem.id.x() #01329 1330attributes #0 = { nounwind readnone }1331attributes #1 = { nounwind }1332