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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s8; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s9; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s10; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s11 12define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) {13; GFX7-LABEL: v_maximumnum_bf16:14; GFX7: ; %bb.0:15; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v017; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v118; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v119; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v020; GFX7-NEXT: v_max_f32_e32 v0, v0, v121; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v022; GFX7-NEXT: s_setpc_b64 s[30:31]23;24; GFX8-LABEL: v_maximumnum_bf16:25; GFX8: ; %bb.0:26; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v028; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v229; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v130; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc31; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v232; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc33; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v134; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v035; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v236; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc37; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v038; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc39; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v140; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc41; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v242; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v143; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc44; GFX8-NEXT: s_setpc_b64 s[30:31]45;46; GFX900-LABEL: v_maximumnum_bf16:47; GFX900: ; %bb.0:48; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)49; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v050; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v251; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v152; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc53; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v354; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc55; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v056; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v157; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v2, v358; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc59; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v060; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc61; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v162; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc63; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v264; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v165; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc66; GFX900-NEXT: s_setpc_b64 s[30:31]67;68; GFX950-LABEL: v_maximumnum_bf16:69; GFX950: ; %bb.0:70; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)71; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v072; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v2, v273; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v174; GFX950-NEXT: s_nop 075; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc76; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v377; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v078; GFX950-NEXT: s_nop 079; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc80; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v181; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v2, v382; GFX950-NEXT: s_nop 183; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc84; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v085; GFX950-NEXT: s_nop 186; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc87; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v188; GFX950-NEXT: s_nop 189; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc90; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v291; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v192; GFX950-NEXT: s_nop 193; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc94; GFX950-NEXT: s_setpc_b64 s[30:31]95;96; GFX10-LABEL: v_maximumnum_bf16:97; GFX10: ; %bb.0:98; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)99; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v0100; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1101; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2102; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo103; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3104; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v0105; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo106; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1107; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3108; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo109; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0110; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2111; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo112; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1113; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo114; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3115; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo116; GFX10-NEXT: s_setpc_b64 s[30:31]117;118; GFX11-TRUE16-LABEL: v_maximumnum_bf16:119; GFX11-TRUE16: ; %bb.0:120; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)121; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0122; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l123; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l124; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)125; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2126; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l127; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l128; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo129; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)130; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2131; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h132; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo133; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)134; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2135; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo136; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h137; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0138; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)139; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo140; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l141; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2142; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)143; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo144; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]145;146; GFX11-FAKE16-LABEL: v_maximumnum_bf16:147; GFX11-FAKE16: ; %bb.0:148; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0150; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)151; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2152; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo153; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1154; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0155; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)156; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3157; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo158; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1159; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)160; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3161; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo162; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2163; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0164; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo165; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1166; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)167; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo168; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3169; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo170; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]171;172; GFX12-TRUE16-LABEL: v_maximumnum_bf16:173; GFX12-TRUE16: ; %bb.0:174; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0175; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0176; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0177; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0178; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0179; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0180; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l181; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l182; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)183; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2184; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l185; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l186; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)187; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo188; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2189; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)190; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h191; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)192; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo193; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2194; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)195; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo196; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h197; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)198; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)199; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s0200; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)201; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo202; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l203; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)204; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2205; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)206; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo207; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]208;209; GFX12-FAKE16-LABEL: v_maximumnum_bf16:210; GFX12-FAKE16: ; %bb.0:211; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0212; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0213; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0214; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0215; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0216; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0217; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)218; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2219; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)220; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo221; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1222; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0223; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)224; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3225; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)226; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo227; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1228; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)229; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3230; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)231; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo232; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2233; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0234; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)235; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo236; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1237; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)238; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)239; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo240; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3241; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)242; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo243; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]244 %result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)245 ret bfloat %result246}247 248define bfloat @v_maximumnum_bf16_nnan(bfloat %x, bfloat %y) {249; GFX7-LABEL: v_maximumnum_bf16_nnan:250; GFX7: ; %bb.0:251; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)252; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0253; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1254; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1255; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0256; GFX7-NEXT: v_max_f32_e32 v0, v0, v1257; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0258; GFX7-NEXT: s_setpc_b64 s[30:31]259;260; GFX8-LABEL: v_maximumnum_bf16_nnan:261; GFX8: ; %bb.0:262; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)263; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1264; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0265; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2266; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc267; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0268; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc269; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1270; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc271; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v2272; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1273; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc274; GFX8-NEXT: s_setpc_b64 s[30:31]275;276; GFX900-LABEL: v_maximumnum_bf16_nnan:277; GFX900: ; %bb.0:278; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)279; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v1280; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0281; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2282; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc283; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0284; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc285; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1286; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc287; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v2288; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1289; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc290; GFX900-NEXT: s_setpc_b64 s[30:31]291;292; GFX950-LABEL: v_maximumnum_bf16_nnan:293; GFX950: ; %bb.0:294; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v1296; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v0297; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2298; GFX950-NEXT: s_nop 1299; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc300; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0301; GFX950-NEXT: s_nop 1302; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc303; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1304; GFX950-NEXT: s_nop 1305; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc306; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v2307; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1308; GFX950-NEXT: s_nop 1309; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc310; GFX950-NEXT: s_setpc_b64 s[30:31]311;312; GFX10-LABEL: v_maximumnum_bf16_nnan:313; GFX10: ; %bb.0:314; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)315; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v1316; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v0317; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2318; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo319; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0320; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v2321; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo322; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1323; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo324; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3325; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo326; GFX10-NEXT: s_setpc_b64 s[30:31]327;328; GFX11-TRUE16-LABEL: v_maximumnum_bf16_nnan:329; GFX11-TRUE16: ; %bb.0:330; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)331; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0332; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l333; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l334; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l335; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)336; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l337; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2338; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo339; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l340; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)341; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, s0342; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo343; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2344; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)345; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo346; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]347;348; GFX11-FAKE16-LABEL: v_maximumnum_bf16_nnan:349; GFX11-FAKE16: ; %bb.0:350; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)351; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1352; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0353; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)354; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2355; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo356; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0357; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2358; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1359; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)360; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo361; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3362; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)363; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo364; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]365;366; GFX12-TRUE16-LABEL: v_maximumnum_bf16_nnan:367; GFX12-TRUE16: ; %bb.0:368; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0369; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0370; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0371; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0372; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0373; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0374; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l375; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l376; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l377; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)378; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l379; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2380; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)381; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo382; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l383; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)384; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)385; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, s0386; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)387; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo388; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2389; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)390; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)391; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo392; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]393;394; GFX12-FAKE16-LABEL: v_maximumnum_bf16_nnan:395; GFX12-FAKE16: ; %bb.0:396; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0397; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0398; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0399; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0400; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0401; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1402; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0403; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)404; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2405; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)406; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo407; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0408; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)409; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2410; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1411; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)412; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)413; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo414; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3415; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)416; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)417; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo418; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]419 %result = call nnan bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)420 ret bfloat %result421}422 423define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) {424; GFX7-LABEL: v_maximumnum_v2bf16:425; GFX7: ; %bb.0:426; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)427; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0428; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v2429; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1430; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v3431; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3432; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1433; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v2434; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0435; GFX7-NEXT: v_max_f32_e32 v1, v1, v3436; GFX7-NEXT: v_max_f32_e32 v0, v0, v2437; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0438; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1439; GFX7-NEXT: s_setpc_b64 s[30:31]440;441; GFX8-LABEL: v_maximumnum_v2bf16:442; GFX8: ; %bb.0:443; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)444; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v0445; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v2446; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1447; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v1448; GFX8-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD449; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v5450; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc451; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3452; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2453; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5454; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc455; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3456; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc457; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2458; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc459; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4460; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3461; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0462; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc463; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3464; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1465; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc466; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v3467; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc468; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v1469; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0470; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3471; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc472; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0473; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc474; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1475; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc476; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3477; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1478; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2479; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc480; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD481; GFX8-NEXT: s_setpc_b64 s[30:31]482;483; GFX900-LABEL: v_maximumnum_v2bf16:484; GFX900: ; %bb.0:485; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)486; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v0487; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v2488; GFX900-NEXT: v_lshrrev_b32_e32 v2, 16, v1489; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v1490; GFX900-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD491; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v5492; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc493; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v3494; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v2495; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5496; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc497; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3498; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc499; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2500; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc501; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v4502; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3503; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0504; GFX900-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc505; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3506; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1507; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc508; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v3509; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc510; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v1511; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v0512; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3513; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc514; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0515; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc516; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1517; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc518; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v3519; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1520; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc521; GFX900-NEXT: s_mov_b32 s4, 0x5040100522; GFX900-NEXT: v_perm_b32 v0, v2, v0, s4523; GFX900-NEXT: s_setpc_b64 s[30:31]524;525; GFX950-LABEL: v_maximumnum_v2bf16:526; GFX950: ; %bb.0:527; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX950-NEXT: v_and_b32_e32 v2, 0xffff0000, v0529; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v2, v2530; GFX950-NEXT: v_lshrrev_b32_e32 v2, 16, v1531; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v1532; GFX950-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD533; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v5534; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v3535; GFX950-NEXT: s_mov_b32 s0, 0x5040100536; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc537; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v2538; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v5539; GFX950-NEXT: s_nop 1540; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc541; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3542; GFX950-NEXT: s_nop 1543; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc544; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2545; GFX950-NEXT: s_nop 1546; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc547; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v4548; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3549; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v0550; GFX950-NEXT: s_nop 0551; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc552; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3553; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v1554; GFX950-NEXT: s_nop 0555; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc556; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v3557; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v0558; GFX950-NEXT: s_nop 0559; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc560; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v1561; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3562; GFX950-NEXT: s_nop 1563; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc564; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0565; GFX950-NEXT: s_nop 1566; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc567; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1568; GFX950-NEXT: s_nop 1569; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc570; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v3571; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1572; GFX950-NEXT: s_nop 1573; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc574; GFX950-NEXT: v_perm_b32 v0, v2, v0, s0575; GFX950-NEXT: s_setpc_b64 s[30:31]576;577; GFX10-LABEL: v_maximumnum_v2bf16:578; GFX10: ; %bb.0:579; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v0581; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v0582; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v1583; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1584; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2585; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v1586; GFX10-NEXT: v_cndmask_b32_sdwa v6, v0, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD587; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4588; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo589; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3590; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v6591; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo592; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5593; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0594; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2595; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo596; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4597; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1598; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo599; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7600; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3601; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo602; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6603; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo604; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0605; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4606; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo607; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2608; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo609; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1610; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo611; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7612; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo613; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6614; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo615; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100616; GFX10-NEXT: s_setpc_b64 s[30:31]617;618; GFX11-TRUE16-LABEL: v_maximumnum_v2bf16:619; GFX11-TRUE16: ; %bb.0:620; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)621; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0622; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1623; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0624; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1625; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)626; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2627; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3628; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)629; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l630; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0631; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5632; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo633; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s0634; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h635; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)636; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v2637; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo638; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3639; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l640; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s0641; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l642; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo643; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)644; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4645; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s1646; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.h647; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)648; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v3, v4649; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s0650; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h651; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)652; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s1653; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.h654; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s0655; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l656; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)657; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s1658; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4659; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)660; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo661; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0662; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]663;664; GFX11-FAKE16-LABEL: v_maximumnum_v2bf16:665; GFX11-FAKE16: ; %bb.0:666; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0668; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1669; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0670; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)671; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2672; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0673; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1674; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)675; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5676; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo677; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6678; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo679; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)680; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3681; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1682; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4683; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2684; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)685; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5686; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1687; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0688; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)689; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7690; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4691; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo692; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2693; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)694; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5695; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0696; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo697; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3698; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo699; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1700; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)701; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo702; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6703; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo704; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7705; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)706; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo707; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100708; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]709;710; GFX12-TRUE16-LABEL: v_maximumnum_v2bf16:711; GFX12-TRUE16: ; %bb.0:712; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0713; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0714; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0715; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0716; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0717; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0718; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1719; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0720; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1721; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)722; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2723; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v3724; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)725; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l726; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0727; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v5728; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)729; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo730; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)731; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)732; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s0733; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h734; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v2735; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)736; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo737; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3738; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l739; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)740; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)741; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s0742; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l743; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)744; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo745; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4746; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)747; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s1748; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.h749; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v3, v4750; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)751; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)752; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s0753; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h754; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s1755; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.h756; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)757; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)758; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s0759; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l760; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s1761; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)762; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v4763; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)764; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo765; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)766; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)767; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0768; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]769;770; GFX12-FAKE16-LABEL: v_maximumnum_v2bf16:771; GFX12-FAKE16: ; %bb.0:772; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0773; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0774; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0775; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0776; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0777; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0778; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1779; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0780; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)781; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2782; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)783; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0784; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1785; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)786; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5787; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)788; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo789; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6790; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)791; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo792; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)793; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3794; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1795; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4796; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)797; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2798; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)799; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v5800; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)801; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1802; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0803; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)804; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7805; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4806; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)807; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo808; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2809; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)810; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)811; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5812; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0813; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)814; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo815; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3816; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)817; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo818; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1819; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)820; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo821; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6822; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)823; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo824; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7825; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)826; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo827; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)828; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100829; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]830 %result = call <2 x bfloat> @llvm.maximumnum.v2bf16(<2 x bfloat> %x, <2 x bfloat> %y)831 ret <2 x bfloat> %result832}833 834define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y) {835; GFX7-LABEL: v_maximumnum_v2bf16_nnan:836; GFX7: ; %bb.0:837; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)838; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v0839; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v2840; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v1841; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v3842; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v3843; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1844; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v2845; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0846; GFX7-NEXT: v_max_f32_e32 v1, v1, v3847; GFX7-NEXT: v_max_f32_e32 v0, v0, v2848; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v0849; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1850; GFX7-NEXT: s_setpc_b64 s[30:31]851;852; GFX8-LABEL: v_maximumnum_v2bf16_nnan:853; GFX8: ; %bb.0:854; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)855; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1856; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0857; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2858; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc859; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0860; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc861; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1862; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2863; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc864; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4865; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc866; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v1867; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v0868; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0869; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1870; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3871; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc872; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0873; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc874; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1875; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc876; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3877; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1878; GFX8-NEXT: v_cndmask_b32_sdwa v0, v3, v0, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD879; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD880; GFX8-NEXT: s_setpc_b64 s[30:31]881;882; GFX900-LABEL: v_maximumnum_v2bf16_nnan:883; GFX900: ; %bb.0:884; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)885; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v1886; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v0887; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2888; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc889; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0890; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc891; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1892; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v2893; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc894; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4895; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc896; GFX900-NEXT: v_and_b32_e32 v3, 0xffff0000, v1897; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v0898; GFX900-NEXT: v_lshrrev_b32_e32 v0, 16, v0899; GFX900-NEXT: v_lshrrev_b32_e32 v1, 16, v1900; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3901; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc902; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0903; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc904; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1905; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc906; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v3907; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1908; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc909; GFX900-NEXT: s_mov_b32 s4, 0x5040100910; GFX900-NEXT: v_perm_b32 v0, v0, v2, s4911; GFX900-NEXT: s_setpc_b64 s[30:31]912;913; GFX950-LABEL: v_maximumnum_v2bf16_nnan:914; GFX950: ; %bb.0:915; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)916; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v1917; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v0918; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v3, v2919; GFX950-NEXT: s_mov_b32 s0, 0x5040100920; GFX950-NEXT: s_nop 0921; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc922; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0923; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v2924; GFX950-NEXT: s_nop 0925; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc926; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1927; GFX950-NEXT: s_nop 1928; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc929; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4930; GFX950-NEXT: v_and_b32_e32 v4, 0xffff0000, v0931; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v0932; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc933; GFX950-NEXT: v_and_b32_e32 v3, 0xffff0000, v1934; GFX950-NEXT: v_lshrrev_b32_e32 v1, 16, v1935; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v3936; GFX950-NEXT: s_nop 1937; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc938; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v0939; GFX950-NEXT: s_nop 1940; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc941; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1942; GFX950-NEXT: s_nop 1943; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc944; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v3945; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1946; GFX950-NEXT: s_nop 1947; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc948; GFX950-NEXT: v_perm_b32 v0, v0, v2, s0949; GFX950-NEXT: s_setpc_b64 s[30:31]950;951; GFX10-LABEL: v_maximumnum_v2bf16_nnan:952; GFX10: ; %bb.0:953; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)954; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v1955; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v0956; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v1957; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v0958; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v0959; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v1960; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2961; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo962; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4963; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2964; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo965; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0966; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo967; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6968; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo969; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1970; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3971; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo972; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7973; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo974; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4975; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo976; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6977; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo978; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100979; GFX10-NEXT: s_setpc_b64 s[30:31]980;981; GFX11-TRUE16-LABEL: v_maximumnum_v2bf16_nnan:982; GFX11-TRUE16: ; %bb.0:983; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)984; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1985; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0986; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l987; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v1988; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0989; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h990; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2991; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0992; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo993; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l994; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)995; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, v0.l, s0996; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3997; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)998; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo999; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41000; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, v0.l, s01001; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v0.h, vcc_lo1002; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.h1003; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1004; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, s11005; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo1006; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v31007; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1008; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo1009; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1010;1011; GFX11-FAKE16-LABEL: v_maximumnum_v2bf16_nnan:1012; GFX11-FAKE16: ; %bb.0:1013; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1014; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v01015; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v01016; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v11017; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v11018; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11019; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v01020; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)1021; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v21022; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo1023; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41024; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)1025; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v21026; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo1027; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01028; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo1029; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v61030; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo1031; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11032; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v31033; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1034; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71035; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo1036; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v41037; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)1038; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo1039; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v61040; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo1041; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1042; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401001043; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1044;1045; GFX12-TRUE16-LABEL: v_maximumnum_v2bf16_nnan:1046; GFX12-TRUE16: ; %bb.0:1047; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x01048; GFX12-TRUE16-NEXT: s_wait_expcnt 0x01049; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x01050; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x01051; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x01052; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v11053; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v01054; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l1055; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11056; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v01057; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h1058; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v21059; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, 01060; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1061; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo1062; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l1063; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1064; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)1065; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, v0.l, s01066; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v31067; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1068; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo1069; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41070; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1071; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)1072; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, v0.l, s01073; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1074; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v1.h, v0.h, vcc_lo1075; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.h1076; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, s11077; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1078; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)1079; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo1080; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v31081; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1082; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo1083; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]1084;1085; GFX12-FAKE16-LABEL: v_maximumnum_v2bf16_nnan:1086; GFX12-FAKE16: ; %bb.0:1087; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x01088; GFX12-FAKE16-NEXT: s_wait_expcnt 0x01089; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x01090; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x01091; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x01092; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v01093; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v01094; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v11095; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v11096; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v11097; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v01098; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1099; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v21100; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1101; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo1102; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41103; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1104; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v21105; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1106; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc_lo1107; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01108; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1109; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo1110; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v61111; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1112; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo1113; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11114; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v31115; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1116; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo1117; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v71118; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1119; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc_lo1120; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v41121; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1122; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo1123; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v61124; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1125; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo1126; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1127; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x50401001128; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]1129 %result = call nnan <2 x bfloat> @llvm.maximumnum.v2bf16(<2 x bfloat> %x, <2 x bfloat> %y)1130 ret <2 x bfloat> %result1131}1132 1133define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {1134; GFX7-LABEL: v_maximumnum_v3bf16:1135; GFX7: ; %bb.0:1136; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1137; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v01138; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v31139; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v11140; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v41141; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v21142; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v51143; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v51144; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v21145; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v41146; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v11147; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v31148; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v01149; GFX7-NEXT: v_max_f32_e32 v2, v2, v51150; GFX7-NEXT: v_max_f32_e32 v1, v1, v41151; GFX7-NEXT: v_max_f32_e32 v0, v0, v31152; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v21153; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v01154; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v11155; GFX7-NEXT: s_setpc_b64 s[30:31]1156;1157; GFX8-LABEL: v_maximumnum_v3bf16:1158; GFX8: ; %bb.0:1159; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1160; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v01161; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v41162; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v21163; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v21164; GFX8-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1165; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v71166; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1167; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v51168; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v41169; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v71170; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc1171; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51172; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc1173; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v41174; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc1175; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v61176; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51177; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v11178; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc1179; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v51180; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v31181; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1182; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v51183; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc1184; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v31185; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v11186; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v51187; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc1188; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11189; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc1190; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31191; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1192; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v51193; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31194; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v01195; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc1196; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v31197; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v21198; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1199; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v31200; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc1201; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v21202; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v01203; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v31204; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc1205; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01206; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1207; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21208; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1209; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v31210; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21211; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1212; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v41213; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1214; GFX8-NEXT: s_setpc_b64 s[30:31]1215;1216; GFX900-LABEL: v_maximumnum_v3bf16:1217; GFX900: ; %bb.0:1218; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1219; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v01220; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v41221; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v21222; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v21223; GFX900-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1224; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v71225; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1226; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v51227; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v41228; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v71229; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc1230; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51231; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc1232; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v41233; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc1234; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v61235; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51236; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v11237; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc1238; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v51239; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v31240; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1241; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v51242; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc1243; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v31244; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v11245; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v51246; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc1247; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11248; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc1249; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31250; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1251; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v51252; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31253; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v01254; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc1255; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v31256; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v21257; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1258; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v31259; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc1260; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v21261; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v01262; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v31263; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc1264; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01265; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1266; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21267; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1268; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v31269; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21270; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1271; GFX900-NEXT: s_mov_b32 s4, 0x50401001272; GFX900-NEXT: v_perm_b32 v0, v4, v0, s41273; GFX900-NEXT: s_setpc_b64 s[30:31]1274;1275; GFX950-LABEL: v_maximumnum_v3bf16:1276; GFX950: ; %bb.0:1277; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1278; GFX950-NEXT: v_and_b32_e32 v4, 0xffff0000, v01279; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v41280; GFX950-NEXT: v_lshrrev_b32_e32 v4, 16, v21281; GFX950-NEXT: v_and_b32_e32 v7, 0xffff0000, v21282; GFX950-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1283; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v71284; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v51285; GFX950-NEXT: s_mov_b32 s0, 0x50401001286; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc1287; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v41288; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v71289; GFX950-NEXT: s_nop 11290; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc1291; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51292; GFX950-NEXT: s_nop 11293; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc1294; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v41295; GFX950-NEXT: s_nop 11296; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc1297; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v61298; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51299; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v11300; GFX950-NEXT: s_nop 01301; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc1302; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v51303; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v31304; GFX950-NEXT: s_nop 01305; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1306; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v51307; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v11308; GFX950-NEXT: s_nop 01309; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc1310; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v31311; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v51312; GFX950-NEXT: s_nop 11313; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc1314; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11315; GFX950-NEXT: s_nop 11316; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc1317; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31318; GFX950-NEXT: s_nop 11319; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1320; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v51321; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31322; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v01323; GFX950-NEXT: s_nop 01324; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc1325; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v31326; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v21327; GFX950-NEXT: s_nop 01328; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1329; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v31330; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v01331; GFX950-NEXT: s_nop 01332; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc1333; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v21334; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v31335; GFX950-NEXT: s_nop 11336; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc1337; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01338; GFX950-NEXT: s_nop 11339; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1340; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21341; GFX950-NEXT: s_nop 11342; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1343; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v31344; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21345; GFX950-NEXT: s_nop 11346; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc1347; GFX950-NEXT: v_perm_b32 v0, v4, v0, s01348; GFX950-NEXT: s_setpc_b64 s[30:31]1349;1350; GFX10-LABEL: v_maximumnum_v3bf16:1351; GFX10: ; %bb.0:1352; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1353; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v01354; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v21355; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v01356; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v21357; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v21358; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v41359; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v11360; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v31361; GFX10-NEXT: v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1362; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v81363; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo1364; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v41365; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1366; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v61367; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc_lo1368; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v91369; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v101370; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v11371; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v41372; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo1373; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v71374; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v01375; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v21376; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo1377; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v61378; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v31379; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v10, vcc_lo1380; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v81381; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo1382; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v111383; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v51384; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc_lo1385; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v101386; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo1387; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01388; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo1389; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v41390; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo1391; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21392; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v61393; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo1394; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v91395; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo1396; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11397; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v71398; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo1399; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81400; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo1401; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31402; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x50401001403; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1404; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v41405; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo1406; GFX10-NEXT: s_setpc_b64 s[30:31]1407;1408; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16:1409; GFX11-TRUE16: ; %bb.0:1410; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1411; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v01412; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v21413; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, 01414; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v31415; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1416; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v41417; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v51418; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)1419; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l1420; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11421; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v71422; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo1423; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21424; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s01425; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h1426; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1427; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v71428; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v41429; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo1430; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v51431; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l1432; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)1433; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s01434; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l1435; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo1436; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v61437; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1438; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v5.h, s11439; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h1440; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v01441; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v61442; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1443; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s01444; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h1445; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s11446; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v31447; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1448; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s01449; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l1450; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s11451; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l1452; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1453; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v61454; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s21455; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.h1456; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1457; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s01458; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v0, v61459; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1460; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s11461; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.h1462; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s21463; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.h1464; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1465; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s11466; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l1467; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s21468; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1469; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v61470; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo1471; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1472; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s11473; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1474;1475; GFX11-FAKE16-LABEL: v_maximumnum_v3bf16:1476; GFX11-FAKE16: ; %bb.0:1477; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1478; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v01479; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v21480; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v01481; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v01482; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)1483; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v41484; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v21485; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1486; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v71487; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v11488; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v81489; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v31490; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21491; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)1492; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v61493; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1494; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v71495; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v41496; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo1497; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v51498; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)1499; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v101500; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo1501; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v91502; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v11503; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v61504; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v41505; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v21506; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo1507; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51508; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1509; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v01510; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v81511; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v31512; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo1513; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v101514; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo1515; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01516; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)1517; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo1518; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v71519; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v51520; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo1521; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21522; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo1523; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11524; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)1525; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v61526; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v71527; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo1528; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31529; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)1530; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x50401001531; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1532; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21533; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo1534; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1535;1536; GFX12-TRUE16-LABEL: v_maximumnum_v3bf16:1537; GFX12-TRUE16: ; %bb.0:1538; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x01539; GFX12-TRUE16-NEXT: s_wait_expcnt 0x01540; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x01541; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x01542; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x01543; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v01544; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v21545; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, 01546; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v31547; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1548; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v41549; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v51550; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)1551; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l1552; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11553; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v71554; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1555; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo1556; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21557; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1558; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1559; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s01560; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h1561; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v71562; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)1563; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v41564; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1565; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo1566; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v51567; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l1568; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1569; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)1570; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s01571; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l1572; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1573; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo1574; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v61575; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1576; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v5.h, s11577; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h1578; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v01579; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v61580; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1581; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1582; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s01583; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h1584; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s11585; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v31586; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1587; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1588; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s01589; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l1590; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s11591; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l1592; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1593; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v61594; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s21595; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.h1596; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1597; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1598; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s01599; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v0, v61600; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1601; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1602; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s11603; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.h1604; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s21605; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.h1606; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1607; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1608; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s11609; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l1610; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s21611; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)1612; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v61613; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)1614; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo1615; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)1616; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1617; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s11618; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]1619;1620; GFX12-FAKE16-LABEL: v_maximumnum_v3bf16:1621; GFX12-FAKE16: ; %bb.0:1622; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x01623; GFX12-FAKE16-NEXT: s_wait_expcnt 0x01624; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x01625; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x01626; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x01627; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v01628; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v21629; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v01630; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v01631; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)1632; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v41633; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1634; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v21635; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1636; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v71637; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1638; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v11639; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v81640; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1641; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v31642; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v21643; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v61644; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1645; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1646; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)1647; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v71648; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v41649; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1650; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo1651; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v51652; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v101653; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1654; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo1655; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v91656; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v11657; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1658; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)1659; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v61660; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v41661; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v21662; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1663; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo1664; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v51665; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1666; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1667; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v01668; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v81669; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v31670; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1671; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo1672; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v101673; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1674; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo1675; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01676; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1677; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo1678; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v71679; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v51680; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1681; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo1682; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21683; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1684; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo1685; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11686; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1687; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v61688; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v71689; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1690; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo1691; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31692; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)1693; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x50401001694; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1695; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1696; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21697; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)1698; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo1699; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]1700 %result = call <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)1701 ret <3 x bfloat> %result1702}1703 1704define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y) {1705; GFX7-LABEL: v_maximumnum_v3bf16_nnan:1706; GFX7: ; %bb.0:1707; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1708; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v01709; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v31710; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v11711; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v41712; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v21713; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v51714; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v51715; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v21716; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v41717; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v11718; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v31719; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v01720; GFX7-NEXT: v_max_f32_e32 v2, v2, v51721; GFX7-NEXT: v_max_f32_e32 v1, v1, v41722; GFX7-NEXT: v_max_f32_e32 v0, v0, v31723; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v21724; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v01725; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v11726; GFX7-NEXT: s_setpc_b64 s[30:31]1727;1728; GFX8-LABEL: v_maximumnum_v3bf16_nnan:1729; GFX8: ; %bb.0:1730; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1731; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v31732; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v11733; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v41734; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc1735; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11736; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc1737; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31738; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1739; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v41740; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31741; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc1742; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v21743; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v01744; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v01745; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v21746; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v31747; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc1748; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v51749; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v5, vcc1750; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v61751; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v31752; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc1753; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51754; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc1755; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v21756; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v01757; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v41758; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc1759; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01760; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1761; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21762; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1763; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v41764; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21765; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1766; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v31767; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1768; GFX8-NEXT: s_setpc_b64 s[30:31]1769;1770; GFX900-LABEL: v_maximumnum_v3bf16_nnan:1771; GFX900: ; %bb.0:1772; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1773; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v31774; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v11775; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v41776; GFX900-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc1777; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11778; GFX900-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc1779; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31780; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1781; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v41782; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31783; GFX900-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc1784; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v21785; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v01786; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v31787; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc1788; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01789; GFX900-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc1790; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21791; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v31792; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc1793; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51794; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc1795; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v21796; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v01797; GFX900-NEXT: v_lshrrev_b32_e32 v0, 16, v01798; GFX900-NEXT: v_lshrrev_b32_e32 v2, 16, v21799; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v41800; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc1801; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01802; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1803; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21804; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1805; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v41806; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21807; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1808; GFX900-NEXT: s_mov_b32 s4, 0x50401001809; GFX900-NEXT: v_perm_b32 v0, v0, v3, s41810; GFX900-NEXT: s_setpc_b64 s[30:31]1811;1812; GFX950-LABEL: v_maximumnum_v3bf16_nnan:1813; GFX950: ; %bb.0:1814; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1815; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v31816; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v11817; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v41818; GFX950-NEXT: s_mov_b32 s0, 0x50401001819; GFX950-NEXT: s_nop 01820; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc1821; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v11822; GFX950-NEXT: s_nop 11823; GFX950-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc1824; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v31825; GFX950-NEXT: s_nop 11826; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc1827; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v41828; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v31829; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v21830; GFX950-NEXT: s_nop 01831; GFX950-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc1832; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v01833; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v31834; GFX950-NEXT: s_nop 11835; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc1836; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01837; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v31838; GFX950-NEXT: s_nop 01839; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc1840; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21841; GFX950-NEXT: s_nop 11842; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc1843; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v51844; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v01845; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v01846; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc1847; GFX950-NEXT: v_and_b32_e32 v4, 0xffff0000, v21848; GFX950-NEXT: v_lshrrev_b32_e32 v2, 16, v21849; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v41850; GFX950-NEXT: s_nop 11851; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc1852; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v01853; GFX950-NEXT: s_nop 11854; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1855; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v21856; GFX950-NEXT: s_nop 11857; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc1858; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v41859; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v21860; GFX950-NEXT: s_nop 11861; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc1862; GFX950-NEXT: v_perm_b32 v0, v0, v3, s01863; GFX950-NEXT: s_setpc_b64 s[30:31]1864;1865; GFX10-LABEL: v_maximumnum_v3bf16_nnan:1866; GFX10: ; %bb.0:1867; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1868; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v21869; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v01870; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v31871; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v11872; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v21873; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v01874; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v61875; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v01876; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v21877; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo1878; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41879; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo1880; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v81881; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v41882; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc_lo1883; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01884; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v51885; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo1886; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11887; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo1888; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v101889; GFX10-NEXT: v_cndmask_b32_e32 v7, v5, v10, vcc_lo1890; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21891; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo1892; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v61893; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v111894; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo1895; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21896; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo1897; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81898; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v7, vcc_lo1899; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31900; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x50401001901; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1902; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v91903; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo1904; GFX10-NEXT: s_setpc_b64 s[30:31]1905;1906; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16_nnan:1907; GFX11-TRUE16: ; %bb.0:1908; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1909; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v31910; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11911; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l1912; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v01913; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l1914; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)1915; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41916; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, 01917; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v21918; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v3.l, v1.l, vcc_lo1919; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l1920; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s01921; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v41922; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)1923; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo1924; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v51925; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v21926; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v01927; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s01928; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.l, v0.l, vcc_lo1929; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l1930; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1931; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.h, v0.l, s11932; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v41933; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h1934; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v2.l, vcc_lo1935; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v31936; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)1937; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s01938; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v0.h, vcc_lo1939; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h1940; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s11941; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v41942; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1943; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo1944; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s01945; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1946;1947; GFX11-FAKE16-LABEL: v_maximumnum_v3bf16_nnan:1948; GFX11-FAKE16: ; %bb.0:1949; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1950; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v21951; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v01952; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v01953; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v21954; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v31955; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v21956; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v61957; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v11958; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v01959; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo1960; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)1961; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v41962; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo1963; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v81964; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc_lo1965; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v01966; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1967; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v51968; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo1969; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11970; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo1971; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v101972; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v10, vcc_lo1973; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v21974; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo1975; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v61976; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v111977; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo1978; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)1979; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21980; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo1981; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v81982; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v7 :: v_dual_lshlrev_b32 v9, 16, v41983; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v31984; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo1985; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)1986; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v91987; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo1988; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x50401001989; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1990;1991; GFX12-TRUE16-LABEL: v_maximumnum_v3bf16_nnan:1992; GFX12-TRUE16: ; %bb.0:1993; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x01994; GFX12-TRUE16-NEXT: s_wait_expcnt 0x01995; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x01996; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x01997; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x01998; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v31999; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12000; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l2001; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v02002; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l2003; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)2004; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v42005; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 02006; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v22007; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2008; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v3.l, v1.l, vcc_lo2009; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l2010; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2011; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)2012; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s02013; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v42014; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2015; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo2016; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v52017; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v22018; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v02019; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2020; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.h, v1.l, s02021; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2022; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.l, v0.l, vcc_lo2023; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l2024; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)2025; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.h, v0.l, s12026; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v42027; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h2028; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2029; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v2.l, vcc_lo2030; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v32031; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2032; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)2033; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v0.l, s02034; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2035; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v0.h, vcc_lo2036; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h2037; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s12038; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v42039; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2040; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)2041; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo2042; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2043; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v0.h, s02044; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]2045;2046; GFX12-FAKE16-LABEL: v_maximumnum_v3bf16_nnan:2047; GFX12-FAKE16: ; %bb.0:2048; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x02049; GFX12-FAKE16-NEXT: s_wait_expcnt 0x02050; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x02051; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x02052; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x02053; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v22054; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v02055; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v02056; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v22057; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v32058; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v22059; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v62060; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12061; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v02062; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2063; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo2064; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)2065; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v42066; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2067; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo2068; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v82069; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2070; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc_lo2071; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v02072; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)2073; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v52074; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2075; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo2076; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12077; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2078; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo2079; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v102080; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2081; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v5, v10, vcc_lo2082; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22083; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2084; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo2085; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v62086; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v112087; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2088; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo2089; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)2090; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22091; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2092; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo2093; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v82094; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2095; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v5, v7 :: v_dual_lshlrev_b32 v9, 16, v42096; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32097; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2098; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2099; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)2100; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v92101; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2102; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo2103; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x50401002104; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]2105 %result = call nnan <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)2106 ret <3 x bfloat> %result2107}2108 2109define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {2110; GFX7-LABEL: v_maximumnum_v4bf16:2111; GFX7: ; %bb.0:2112; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2113; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v02114; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v42115; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v12116; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v52117; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v22118; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v62119; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v32120; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v72121; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v72122; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v32123; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v62124; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v22125; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v52126; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v12127; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v42128; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v02129; GFX7-NEXT: v_max_f32_e32 v3, v3, v72130; GFX7-NEXT: v_max_f32_e32 v2, v2, v62131; GFX7-NEXT: v_max_f32_e32 v1, v1, v52132; GFX7-NEXT: v_max_f32_e32 v0, v0, v42133; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v02134; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v12135; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v22136; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v32137; GFX7-NEXT: s_setpc_b64 s[30:31]2138;2139; GFX8-LABEL: v_maximumnum_v4bf16:2140; GFX8: ; %bb.0:2141; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2142; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v12143; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v42144; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v32145; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v32146; GFX8-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2147; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v72148; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc2149; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v52150; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v42151; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v72152; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc2153; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52154; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc2155; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v42156; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc2157; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v62158; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52159; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v02160; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc2161; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v22162; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v02163; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v52164; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v22165; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc2166; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v82167; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc2168; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v52169; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v62170; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v82171; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc2172; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52173; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc2174; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v62175; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc2176; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v72177; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62178; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v12179; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc2180; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v62181; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v32182; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2183; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v62184; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc2185; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v32186; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v12187; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v62188; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc2189; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12190; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc2191; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32192; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2193; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v62194; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v32195; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v02196; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc2197; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v32198; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v22199; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2200; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v32201; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc2202; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v22203; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v02204; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v32205; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc2206; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v02207; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc2208; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22209; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2210; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v32211; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22212; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc2213; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v52214; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2215; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v42216; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2217; GFX8-NEXT: s_setpc_b64 s[30:31]2218;2219; GFX900-LABEL: v_maximumnum_v4bf16:2220; GFX900: ; %bb.0:2221; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2222; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v12223; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v42224; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v32225; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v32226; GFX900-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2227; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v72228; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc2229; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v52230; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v42231; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v72232; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc2233; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52234; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc2235; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v42236; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc2237; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v62238; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52239; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v02240; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc2241; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v22242; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v02243; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v52244; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v22245; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc2246; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v82247; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc2248; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v52249; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v62250; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v82251; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc2252; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52253; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc2254; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v62255; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc2256; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v72257; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62258; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v12259; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc2260; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v62261; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v32262; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2263; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v62264; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc2265; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v32266; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v12267; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v62268; GFX900-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc2269; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12270; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc2271; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32272; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2273; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v62274; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v32275; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v02276; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc2277; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v32278; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v22279; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2280; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v32281; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc2282; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v22283; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v02284; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v32285; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc2286; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v02287; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc2288; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22289; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2290; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v32291; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22292; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc2293; GFX900-NEXT: s_mov_b32 s4, 0x50401002294; GFX900-NEXT: v_perm_b32 v0, v5, v0, s42295; GFX900-NEXT: v_perm_b32 v1, v4, v1, s42296; GFX900-NEXT: s_setpc_b64 s[30:31]2297;2298; GFX950-LABEL: v_maximumnum_v4bf16:2299; GFX950: ; %bb.0:2300; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2301; GFX950-NEXT: v_and_b32_e32 v4, 0xffff0000, v12302; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v42303; GFX950-NEXT: v_lshrrev_b32_e32 v4, 16, v32304; GFX950-NEXT: v_and_b32_e32 v7, 0xffff0000, v32305; GFX950-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2306; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v72307; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v52308; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v22309; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc2310; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v42311; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v72312; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v02313; GFX950-NEXT: s_mov_b32 s0, 0x50401002314; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc2315; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52316; GFX950-NEXT: s_nop 12317; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc2318; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v42319; GFX950-NEXT: s_nop 12320; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc2321; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v62322; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v52323; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v02324; GFX950-NEXT: s_nop 02325; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc2326; GFX950-NEXT: v_lshrrev_b32_e32 v6, 16, v22327; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v52328; GFX950-NEXT: s_nop 12329; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc2330; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v8, v82331; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v52332; GFX950-NEXT: s_nop 02333; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc2334; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v62335; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v82336; GFX950-NEXT: s_nop 12337; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc2338; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v52339; GFX950-NEXT: s_nop 12340; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc2341; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v62342; GFX950-NEXT: s_nop 12343; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc2344; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v72345; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62346; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v12347; GFX950-NEXT: s_nop 02348; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc2349; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v62350; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v32351; GFX950-NEXT: s_nop 02352; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2353; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v62354; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v12355; GFX950-NEXT: s_nop 02356; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc2357; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v32358; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v62359; GFX950-NEXT: s_nop 12360; GFX950-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc2361; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12362; GFX950-NEXT: s_nop 12363; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc2364; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32365; GFX950-NEXT: s_nop 12366; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2367; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v62368; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v32369; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v02370; GFX950-NEXT: s_nop 02371; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc2372; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v32373; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v22374; GFX950-NEXT: v_perm_b32 v1, v4, v1, s02375; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2376; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v32377; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v02378; GFX950-NEXT: s_nop 02379; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc2380; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v22381; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v32382; GFX950-NEXT: s_nop 12383; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc2384; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v02385; GFX950-NEXT: s_nop 12386; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc2387; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22388; GFX950-NEXT: s_nop 12389; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2390; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v32391; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22392; GFX950-NEXT: s_nop 12393; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc2394; GFX950-NEXT: v_perm_b32 v0, v5, v0, s02395; GFX950-NEXT: s_setpc_b64 s[30:31]2396;2397; GFX10-LABEL: v_maximumnum_v4bf16:2398; GFX10: ; %bb.0:2399; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2400; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v12401; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v32402; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v32403; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v22404; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v02405; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v42406; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v02407; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v12408; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v02409; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v22410; GFX10-NEXT: v_cndmask_b32_sdwa v10, v1, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2411; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v62412; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v32413; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v22414; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc_lo2415; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v42416; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v52417; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc_lo2418; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v112419; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v102420; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v42421; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2422; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v132423; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo2424; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v142425; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo2426; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v92427; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v4, vcc_lo2428; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v122429; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo2430; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v102431; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v10, vcc_lo2432; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v62433; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v72434; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v82435; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo2436; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52437; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo2438; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v62439; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v32440; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v02441; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc_lo2442; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v102443; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v22444; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo2445; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v12446; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v42447; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo2448; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v92449; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v62450; GFX10-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo2451; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v72452; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo2453; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v102454; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo2455; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12456; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo2457; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v02458; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo2459; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32460; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2461; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22462; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v72463; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo2464; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v92465; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v82466; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo2467; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v32468; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo2469; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22470; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x50401002471; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo2472; GFX10-NEXT: v_perm_b32 v1, v5, v1, 0x50401002473; GFX10-NEXT: s_setpc_b64 s[30:31]2474;2475; GFX11-TRUE16-LABEL: v_maximumnum_v4bf16:2476; GFX11-TRUE16: ; %bb.0:2477; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2478; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12479; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v32480; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, 02481; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v02482; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v22483; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v42484; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v52485; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l2486; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v32487; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo2488; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)2489; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v92490; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22491; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s02492; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h2493; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2494; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v92495; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v52496; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo2497; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v72498; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l2499; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)2500; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s02501; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l2502; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v82503; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v12504; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v62505; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo2506; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2507; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s02508; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h2509; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v72510; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v7.h2511; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo2512; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v82513; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l2514; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)2515; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s02516; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l2517; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo2518; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v62519; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2520; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v8.h, s22521; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8.h2522; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v02523; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v62524; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2525; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s02526; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h2527; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s22528; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v32529; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s42530; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)2531; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s02532; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l2533; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s22534; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l2535; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2536; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v62537; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s32538; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.h2539; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2540; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s02541; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v0, v62542; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2543; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s22544; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.h2545; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s32546; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v5.h2547; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)2548; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s22549; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l2550; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v5.h, s32551; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2552; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v62553; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s12554; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo2555; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)2556; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s22557; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]2558;2559; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16:2560; GFX11-FAKE16: ; %bb.0:2561; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2562; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12563; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v32564; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12565; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v02566; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12567; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v42568; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)2569; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v32570; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v72571; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v22572; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v02573; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)2574; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v42575; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo2576; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v52577; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)2578; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v112579; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v22580; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v62581; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo2582; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v122583; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2584; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v42585; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v32586; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v92587; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v02588; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52589; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v22590; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2591; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v72592; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v142593; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo2594; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v102595; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2596; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v02597; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v82598; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v62599; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v132600; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo2601; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)2602; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v92603; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12604; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo2605; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v152606; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v32607; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo2608; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v62609; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo2610; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)2611; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v82612; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v52613; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo2614; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v22615; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v72616; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo2617; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)2618; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v102619; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo2620; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12621; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo2622; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v02623; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo2624; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32625; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)2626; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2627; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22628; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v72629; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v92630; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v82631; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2632; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v32633; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo2634; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2635; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22636; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x50401002637; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo2638; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)2639; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x50401002640; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]2641;2642; GFX12-TRUE16-LABEL: v_maximumnum_v4bf16:2643; GFX12-TRUE16: ; %bb.0:2644; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x02645; GFX12-TRUE16-NEXT: s_wait_expcnt 0x02646; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x02647; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x02648; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x02649; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12650; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v32651; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, 02652; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v02653; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v22654; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v42655; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v52656; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l2657; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v32658; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2659; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo2660; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2661; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v92662; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22663; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2664; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s02665; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h2666; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2667; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v92668; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v52669; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2670; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo2671; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v72672; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l2673; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2674; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)2675; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s02676; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l2677; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v82678; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v12679; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v62680; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2681; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo2682; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2683; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2684; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s02685; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h2686; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v72687; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v7.h2688; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2689; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo2690; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v82691; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l2692; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2693; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)2694; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s02695; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l2696; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2697; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo2698; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v62699; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2700; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v8.h, s22701; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8.h2702; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v02703; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v62704; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2705; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2706; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s02707; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h2708; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s22709; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v32710; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s42711; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2712; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)2713; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s02714; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l2715; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s22716; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l2717; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v62718; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)2719; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s32720; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.h2721; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2722; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s02723; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)2724; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v0, v62725; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2726; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s22727; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.h2728; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)2729; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s32730; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v5.h2731; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2732; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s22733; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l2734; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2735; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v5.h, s32736; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v62737; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)2738; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s12739; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)2740; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo2741; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)2742; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s22743; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]2744;2745; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16:2746; GFX12-FAKE16: ; %bb.0:2747; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x02748; GFX12-FAKE16-NEXT: s_wait_expcnt 0x02749; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x02750; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x02751; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x02752; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12753; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v32754; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v12755; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v02756; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12757; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v42758; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2759; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v32760; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)2761; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v72762; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v22763; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v02764; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v42765; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2766; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo2767; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2768; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v52769; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v112770; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2771; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v22772; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v62773; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2774; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo2775; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v122776; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2777; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2778; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v42779; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2780; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v32781; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v92782; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2783; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v02784; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v52785; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v22786; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2787; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)2788; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v72789; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v142790; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2791; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo2792; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v102793; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v02794; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)2795; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v82796; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2797; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v62798; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v132799; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2800; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo2801; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)2802; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v92803; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v12804; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2805; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo2806; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v152807; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v32808; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2809; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo2810; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v62811; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2812; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo2813; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v82814; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v52815; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2816; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo2817; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v22818; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v72819; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2820; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo2821; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)2822; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v102823; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2824; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo2825; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v12826; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2827; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo2828; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v02829; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2830; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo2831; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v32832; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2833; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo2834; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v22835; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2836; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v72837; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v92838; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2839; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v82840; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)2841; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v32842; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2843; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo2844; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22845; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)2846; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x50401002847; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)2848; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo2849; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x50401002850; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]2851 %result = call <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)2852 ret <4 x bfloat> %result2853}2854 2855define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y) {2856; GFX7-LABEL: v_maximumnum_v4bf16_nnan:2857; GFX7: ; %bb.0:2858; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2859; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v02860; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v42861; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v12862; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v52863; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v22864; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v62865; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v32866; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v72867; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v72868; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v32869; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v62870; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v22871; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v52872; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v12873; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v42874; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v02875; GFX7-NEXT: v_max_f32_e32 v3, v3, v72876; GFX7-NEXT: v_max_f32_e32 v2, v2, v62877; GFX7-NEXT: v_max_f32_e32 v1, v1, v52878; GFX7-NEXT: v_max_f32_e32 v0, v0, v42879; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v02880; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v12881; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v22882; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v32883; GFX7-NEXT: s_setpc_b64 s[30:31]2884;2885; GFX8-LABEL: v_maximumnum_v4bf16_nnan:2886; GFX8: ; %bb.0:2887; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2888; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v32889; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v12890; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v12891; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v32892; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v42893; GFX8-NEXT: v_cndmask_b32_e32 v4, v7, v6, vcc2894; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v62895; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v6, vcc2896; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v72897; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v42898; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc2899; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62900; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc2901; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v32902; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v12903; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v52904; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc2905; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12906; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc2907; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32908; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2909; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v52910; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v32911; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc2912; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v22913; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v02914; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v02915; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v22916; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v32917; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc2918; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v62919; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc2920; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v72921; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v32922; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc2923; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62924; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc2925; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v22926; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v02927; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v52928; GFX8-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc2929; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v02930; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc2931; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22932; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2933; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v52934; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22935; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc2936; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v32937; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2938; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v42939; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2940; GFX8-NEXT: s_setpc_b64 s[30:31]2941;2942; GFX900-LABEL: v_maximumnum_v4bf16_nnan:2943; GFX900: ; %bb.0:2944; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2945; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v32946; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v12947; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v42948; GFX900-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc2949; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12950; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc2951; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32952; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v42953; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc2954; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62955; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc2956; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v32957; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v12958; GFX900-NEXT: v_lshrrev_b32_e32 v1, 16, v12959; GFX900-NEXT: v_lshrrev_b32_e32 v3, 16, v32960; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v52961; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc2962; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v12963; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc2964; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v32965; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc2966; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v52967; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v32968; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc2969; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v22970; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v02971; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v32972; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc2973; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v02974; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v0, vcc2975; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22976; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v32977; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc2978; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v62979; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc2980; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v22981; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v02982; GFX900-NEXT: v_lshrrev_b32_e32 v0, 16, v02983; GFX900-NEXT: v_lshrrev_b32_e32 v2, 16, v22984; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v52985; GFX900-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc2986; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v02987; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc2988; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v22989; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc2990; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v52991; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v22992; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc2993; GFX900-NEXT: s_mov_b32 s4, 0x50401002994; GFX900-NEXT: v_perm_b32 v0, v0, v3, s42995; GFX900-NEXT: v_perm_b32 v1, v1, v4, s42996; GFX900-NEXT: s_setpc_b64 s[30:31]2997;2998; GFX950-LABEL: v_maximumnum_v4bf16_nnan:2999; GFX950: ; %bb.0:3000; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3001; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v33002; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v13003; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v43004; GFX950-NEXT: s_mov_b32 s0, 0x50401003005; GFX950-NEXT: s_nop 03006; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc3007; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13008; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v43009; GFX950-NEXT: s_nop 03010; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc3011; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33012; GFX950-NEXT: s_nop 13013; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v3, vcc3014; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v63015; GFX950-NEXT: v_and_b32_e32 v6, 0xffff0000, v13016; GFX950-NEXT: v_lshrrev_b32_e32 v1, 16, v13017; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc3018; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v33019; GFX950-NEXT: v_lshrrev_b32_e32 v3, 16, v33020; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v53021; GFX950-NEXT: s_nop 13022; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc3023; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13024; GFX950-NEXT: s_nop 13025; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3026; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33027; GFX950-NEXT: s_nop 13028; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc3029; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v53030; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33031; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v23032; GFX950-NEXT: s_nop 03033; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3034; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v03035; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v33036; GFX950-NEXT: v_perm_b32 v1, v1, v4, s03037; GFX950-NEXT: s_nop 03038; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc3039; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v03040; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v33041; GFX950-NEXT: s_nop 03042; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v0, vcc3043; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23044; GFX950-NEXT: s_nop 13045; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc3046; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v63047; GFX950-NEXT: v_and_b32_e32 v6, 0xffff0000, v03048; GFX950-NEXT: v_lshrrev_b32_e32 v0, 16, v03049; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc3050; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v23051; GFX950-NEXT: v_lshrrev_b32_e32 v2, 16, v23052; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v53053; GFX950-NEXT: s_nop 13054; GFX950-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc3055; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v03056; GFX950-NEXT: s_nop 13057; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc3058; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23059; GFX950-NEXT: s_nop 13060; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc3061; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v53062; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v23063; GFX950-NEXT: s_nop 13064; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc3065; GFX950-NEXT: v_perm_b32 v0, v0, v3, s03066; GFX950-NEXT: s_setpc_b64 s[30:31]3067;3068; GFX10-LABEL: v_maximumnum_v4bf16_nnan:3069; GFX10: ; %bb.0:3070; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3071; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v33072; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v13073; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v33074; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v13075; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v13076; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v23077; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v43078; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v33079; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v03080; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v23081; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v03082; GFX10-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo3083; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13084; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v43085; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo3086; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33087; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo3088; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v63089; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v03090; GFX10-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo3091; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133092; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo3093; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v93094; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v23095; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo3096; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83097; GFX10-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc_lo3098; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v113099; GFX10-NEXT: v_cndmask_b32_e32 v9, v4, v3, vcc_lo3100; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v03101; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo3102; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53103; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo3104; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33105; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v93106; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo3107; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23108; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo3109; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v73110; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v43111; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo3112; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23113; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v63114; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo3115; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v83116; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v3, vcc_lo3117; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v43118; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x50401003119; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo3120; GFX10-NEXT: v_perm_b32 v1, v3, v1, 0x50401003121; GFX10-NEXT: s_setpc_b64 s[30:31]3122;3123; GFX11-TRUE16-LABEL: v_maximumnum_v4bf16_nnan:3124; GFX11-TRUE16: ; %bb.0:3125; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3126; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v33127; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v13128; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l3129; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v33130; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v13131; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.h3132; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v43133; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, 03134; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.l, v1.l, vcc_lo3135; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l3136; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)3137; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v1.l, s03138; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53139; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)3140; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v3.l, vcc_lo3141; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v63142; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v23143; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v03144; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s03145; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v1.h, vcc_lo3146; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.h3147; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)3148; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s13149; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53150; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l3151; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v3.h, vcc_lo3152; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v43153; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v23154; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v03155; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)3156; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s03157; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.l, v0.l, vcc_lo3158; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l3159; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.h, v0.l, s13160; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53161; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h3162; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)3163; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo3164; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v43165; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s03166; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.h, v0.h, vcc_lo3167; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h3168; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)3169; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s13170; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53171; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo3172; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3173; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s03174; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]3175;3176; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_nnan:3177; GFX11-FAKE16: ; %bb.0:3178; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3179; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v33180; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v13181; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v13182; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v23183; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3184; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v43185; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v33186; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v13187; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo3188; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13189; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v33190; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)3191; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v43192; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo3193; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33194; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v03195; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v63196; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v03197; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo3198; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133199; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v12, 0xffff0000, v03200; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v93201; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v23202; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo3203; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v23204; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83205; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc_lo3206; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)3207; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v113208; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v4, v3, vcc_lo3209; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v03210; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo3211; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53212; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo3213; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33214; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo3215; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23216; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo3217; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v73218; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v43219; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v63220; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v93221; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)3222; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23223; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo3224; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v83225; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v3, vcc_lo3226; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v43227; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo3228; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3229; GFX11-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x50401003230; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x50401003231; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]3232;3233; GFX12-TRUE16-LABEL: v_maximumnum_v4bf16_nnan:3234; GFX12-TRUE16: ; %bb.0:3235; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x03236; GFX12-TRUE16-NEXT: s_wait_expcnt 0x03237; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x03238; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x03239; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x03240; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v33241; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v13242; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l3243; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v33244; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v13245; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v1.h3246; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v43247; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, 03248; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3249; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.l, v1.l, vcc_lo3250; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l3251; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)3252; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)3253; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v1.l, s03254; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53255; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3256; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v4.l, v3.l, vcc_lo3257; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v63258; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v23259; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v03260; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)3261; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v5.h, v1.l, s03262; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3263; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v1.h, vcc_lo3264; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.h3265; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3266; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s13267; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53268; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l3269; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3270; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.h, v3.h, vcc_lo3271; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v43272; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v23273; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v03274; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)3275; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s03276; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3277; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.l, v0.l, vcc_lo3278; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l3279; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3280; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.h, v0.l, s13281; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53282; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.h3283; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3284; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo3285; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v43286; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)3287; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)3288; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v5.h, v0.l, s03289; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3290; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v2.h, v0.h, vcc_lo3291; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h3292; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s13293; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v53294; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)3295; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)3296; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo3297; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)3298; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.h, v0.h, s03299; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]3300;3301; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16_nnan:3302; GFX12-FAKE16: ; %bb.0:3303; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x03304; GFX12-FAKE16-NEXT: s_wait_expcnt 0x03305; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x03306; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x03307; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x03308; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v33309; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v13310; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v13311; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v23312; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)3313; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v43314; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v33315; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v13316; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3317; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v3, v1, vcc_lo3318; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13319; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v33320; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)3321; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v43322; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3323; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc_lo3324; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33325; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3326; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v03327; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v63328; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v03329; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3330; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc_lo3331; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v133332; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3333; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v12, 0xffff0000, v03334; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v93335; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v23336; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3337; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo3338; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v23339; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83340; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3341; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v6, v8, vcc_lo3342; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)3343; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v113344; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3345; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v4, v3, vcc_lo3346; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v03347; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3348; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo3349; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53350; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3351; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo3352; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33353; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3354; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo3355; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23356; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3357; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo3358; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v73359; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v43360; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3361; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v63362; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v93363; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23364; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3365; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo3366; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)3367; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v83368; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3369; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v3, vcc_lo3370; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v43371; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)3372; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo3373; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3374; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x50401003375; GFX12-FAKE16-NEXT: v_perm_b32 v1, v3, v1, 0x50401003376; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]3377 %result = call nnan <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)3378 ret <4 x bfloat> %result3379}3380 3381define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {3382; GFX7-LABEL: v_maximumnum_v6bf16:3383; GFX7: ; %bb.0:3384; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3385; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v03386; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v63387; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v13388; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v73389; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v23390; GFX7-NEXT: v_mul_f32_e32 v8, 1.0, v83391; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v33392; GFX7-NEXT: v_mul_f32_e32 v9, 1.0, v93393; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v43394; GFX7-NEXT: v_mul_f32_e32 v10, 1.0, v103395; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v53396; GFX7-NEXT: v_mul_f32_e32 v11, 1.0, v113397; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v113398; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v53399; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v103400; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v43401; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v93402; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v33403; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v83404; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v23405; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v73406; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v13407; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v63408; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v03409; GFX7-NEXT: v_max_f32_e32 v5, v5, v113410; GFX7-NEXT: v_max_f32_e32 v4, v4, v103411; GFX7-NEXT: v_max_f32_e32 v3, v3, v93412; GFX7-NEXT: v_max_f32_e32 v2, v2, v83413; GFX7-NEXT: v_max_f32_e32 v1, v1, v73414; GFX7-NEXT: v_max_f32_e32 v0, v0, v63415; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v03416; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v13417; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v23418; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v33419; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v43420; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v53421; GFX7-NEXT: s_setpc_b64 s[30:31]3422;3423; GFX8-LABEL: v_maximumnum_v6bf16:3424; GFX8: ; %bb.0:3425; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3426; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v23427; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v53428; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v23429; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v63430; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v53431; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc3432; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v93433; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc3434; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v63435; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v73436; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v8, v93437; GFX8-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc3438; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v63439; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3440; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v73441; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc3442; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v83443; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v73444; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v13445; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3446; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v43447; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v13448; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v73449; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v43450; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc3451; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v103452; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc3453; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v73454; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v83455; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v9, v103456; GFX8-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc3457; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v73458; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc3459; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v83460; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc3461; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v93462; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v83463; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v03464; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc3465; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v33466; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v03467; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v83468; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v33469; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc3470; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v113471; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc3472; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v83473; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v93474; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v113475; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc3476; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v83477; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc3478; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v93479; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc3480; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v103481; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v93482; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v23483; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc3484; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v93485; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v53486; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc3487; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v93488; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc3489; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v53490; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v23491; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v93492; GFX8-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc3493; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23494; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc3495; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53496; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc3497; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v93498; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53499; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v13500; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc3501; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v53502; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v43503; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc3504; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v53505; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc3506; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v43507; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v13508; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v9, v53509; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc3510; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13511; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3512; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v43513; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc3514; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v53515; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v43516; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v03517; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3518; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v43519; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v33520; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc3521; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v43522; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc3523; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v33524; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v03525; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v43526; GFX8-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc3527; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v03528; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc3529; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33530; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc3531; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v43532; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33533; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc3534; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v83535; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3536; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v73537; GFX8-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3538; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v63539; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3540; GFX8-NEXT: s_setpc_b64 s[30:31]3541;3542; GFX900-LABEL: v_maximumnum_v6bf16:3543; GFX900: ; %bb.0:3544; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3545; GFX900-NEXT: v_and_b32_e32 v6, 0xffff0000, v23546; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v53547; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v23548; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v63549; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v53550; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc3551; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v93552; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc3553; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v63554; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v73555; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v8, v93556; GFX900-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc3557; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v63558; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3559; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v73560; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc3561; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v83562; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v73563; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v13564; GFX900-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3565; GFX900-NEXT: v_lshrrev_b32_e32 v8, 16, v43566; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v13567; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v73568; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v43569; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc3570; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v103571; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc3572; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v73573; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v83574; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v9, v103575; GFX900-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc3576; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v73577; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc3578; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v83579; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc3580; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v93581; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v83582; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v03583; GFX900-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc3584; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v33585; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v03586; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v83587; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v33588; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc3589; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v113590; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc3591; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v83592; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v93593; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v113594; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc3595; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v83596; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc3597; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v93598; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc3599; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v103600; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v93601; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v23602; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc3603; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v93604; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v53605; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc3606; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v93607; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc3608; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v53609; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v23610; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v93611; GFX900-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc3612; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23613; GFX900-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc3614; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53615; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc3616; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v93617; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53618; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v13619; GFX900-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc3620; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v53621; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v43622; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc3623; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v53624; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc3625; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v43626; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v13627; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v9, v53628; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc3629; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13630; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3631; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v43632; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc3633; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v53634; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v43635; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v03636; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3637; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v43638; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v33639; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc3640; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v43641; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc3642; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v33643; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v03644; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v43645; GFX900-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc3646; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v03647; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc3648; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33649; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc3650; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v43651; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33652; GFX900-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc3653; GFX900-NEXT: s_mov_b32 s4, 0x50401003654; GFX900-NEXT: v_perm_b32 v0, v8, v0, s43655; GFX900-NEXT: v_perm_b32 v1, v7, v1, s43656; GFX900-NEXT: v_perm_b32 v2, v6, v2, s43657; GFX900-NEXT: s_setpc_b64 s[30:31]3658;3659; GFX950-LABEL: v_maximumnum_v6bf16:3660; GFX950: ; %bb.0:3661; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3662; GFX950-NEXT: v_and_b32_e32 v6, 0xffff0000, v23663; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v53664; GFX950-NEXT: v_lshrrev_b32_e32 v8, 16, v23665; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v63666; GFX950-NEXT: v_and_b32_e32 v9, 0xffff0000, v53667; GFX950-NEXT: v_and_b32_e32 v10, 0xffff0000, v43668; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc3669; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v93670; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v63671; GFX950-NEXT: v_and_b32_e32 v11, 0xffff0000, v33672; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc3673; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v73674; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v8, v93675; GFX950-NEXT: v_lshrrev_b32_e32 v9, 16, v13676; GFX950-NEXT: s_mov_b32 s0, 0x50401003677; GFX950-NEXT: v_cndmask_b32_e32 v8, v7, v6, vcc3678; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v63679; GFX950-NEXT: s_nop 13680; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3681; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v73682; GFX950-NEXT: s_nop 13683; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc3684; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v83685; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v73686; GFX950-NEXT: v_and_b32_e32 v7, 0xffff0000, v13687; GFX950-NEXT: s_nop 03688; GFX950-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc3689; GFX950-NEXT: v_lshrrev_b32_e32 v8, 16, v43690; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v73691; GFX950-NEXT: s_nop 13692; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v8, vcc3693; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v10, v103694; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v73695; GFX950-NEXT: s_nop 03696; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc3697; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v83698; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v9, v103699; GFX950-NEXT: v_lshrrev_b32_e32 v10, 16, v03700; GFX950-NEXT: s_nop 03701; GFX950-NEXT: v_cndmask_b32_e32 v9, v8, v7, vcc3702; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v73703; GFX950-NEXT: s_nop 13704; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc3705; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v83706; GFX950-NEXT: s_nop 13707; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc3708; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v93709; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v83710; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v03711; GFX950-NEXT: s_nop 03712; GFX950-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc3713; GFX950-NEXT: v_lshrrev_b32_e32 v9, 16, v33714; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v8, v83715; GFX950-NEXT: s_nop 13716; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc3717; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v113718; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v83719; GFX950-NEXT: s_nop 03720; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc3721; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v93722; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v113723; GFX950-NEXT: s_nop 13724; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc3725; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v83726; GFX950-NEXT: s_nop 13727; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc3728; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v93729; GFX950-NEXT: s_nop 13730; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc3731; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v103732; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v93733; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v23734; GFX950-NEXT: s_nop 03735; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc3736; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v93737; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v53738; GFX950-NEXT: s_nop 03739; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc3740; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v93741; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v23742; GFX950-NEXT: s_nop 03743; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc3744; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v53745; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v93746; GFX950-NEXT: s_nop 13747; GFX950-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc3748; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v23749; GFX950-NEXT: s_nop 13750; GFX950-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc3751; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v53752; GFX950-NEXT: s_nop 13753; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc3754; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v93755; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v53756; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v13757; GFX950-NEXT: s_nop 03758; GFX950-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc3759; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v53760; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v43761; GFX950-NEXT: v_perm_b32 v2, v6, v2, s03762; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc3763; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v53764; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v13765; GFX950-NEXT: s_nop 03766; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc3767; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v43768; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v9, v53769; GFX950-NEXT: s_nop 13770; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v1, vcc3771; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v13772; GFX950-NEXT: s_nop 13773; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3774; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v43775; GFX950-NEXT: s_nop 13776; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc3777; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v53778; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v43779; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v03780; GFX950-NEXT: s_nop 03781; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc3782; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v43783; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v33784; GFX950-NEXT: v_perm_b32 v1, v7, v1, s03785; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc3786; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v43787; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v03788; GFX950-NEXT: s_nop 03789; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc3790; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v33791; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v43792; GFX950-NEXT: s_nop 13793; GFX950-NEXT: v_cndmask_b32_e32 v4, v3, v0, vcc3794; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v03795; GFX950-NEXT: s_nop 13796; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc3797; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v33798; GFX950-NEXT: s_nop 13799; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc3800; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v43801; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v33802; GFX950-NEXT: s_nop 13803; GFX950-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc3804; GFX950-NEXT: v_perm_b32 v0, v8, v0, s03805; GFX950-NEXT: s_setpc_b64 s[30:31]3806;3807; GFX10-LABEL: v_maximumnum_v6bf16:3808; GFX10: ; %bb.0:3809; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3810; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v23811; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v53812; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v53813; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v43814; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v13815; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v63816; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v13817; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v03818; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v43819; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v33820; GFX10-NEXT: v_cndmask_b32_sdwa v12, v2, v7, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3821; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v83822; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v03823; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v33824; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc_lo3825; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v63826; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v73827; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo3828; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v133829; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v123830; GFX10-NEXT: v_cndmask_b32_e32 v13, v15, v14, vcc_lo3831; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v113832; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v63833; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v133834; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v6, vcc_lo3835; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v163836; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v93837; GFX10-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo3838; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v123839; GFX10-NEXT: v_cndmask_b32_e32 v12, v10, v12, vcc_lo3840; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v83841; GFX10-NEXT: v_cndmask_b32_e32 v8, v14, v13, vcc_lo3842; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v73843; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v103844; GFX10-NEXT: v_cndmask_b32_e32 v7, v12, v7, vcc_lo3845; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v163846; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v83847; GFX10-NEXT: v_cndmask_b32_e32 v11, v9, v6, vcc_lo3848; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v143849; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo3850; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v63851; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo3852; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v123853; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v113854; GFX10-NEXT: v_cndmask_b32_e32 v10, v8, v13, vcc_lo3855; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v93856; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo3857; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v133858; GFX10-NEXT: v_cndmask_b32_e32 v9, v10, v13, vcc_lo3859; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v123860; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v23861; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo3862; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v83863; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v103864; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo3865; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v133866; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v53867; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo3868; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v113869; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v03870; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc_lo3871; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v13872; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v93873; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v43874; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v2, vcc_lo3875; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v103876; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v33877; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo3878; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v113879; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v23880; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v13881; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo3882; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v93883; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v53884; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v03885; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo3886; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v103887; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v43888; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo3889; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v93890; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v33891; GFX10-NEXT: v_cndmask_b32_e32 v9, v5, v2, vcc_lo3892; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v103893; GFX10-NEXT: v_cndmask_b32_e32 v10, v4, v1, vcc_lo3894; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23895; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo3896; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v113897; GFX10-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo3898; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v13899; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo3900; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v53901; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo3902; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v03903; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v113904; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo3905; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v43906; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo3907; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v103908; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v33909; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo3910; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v43911; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v93912; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo3913; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v53914; GFX10-NEXT: v_perm_b32 v1, v6, v1, 0x50401003915; GFX10-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo3916; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v33917; GFX10-NEXT: v_perm_b32 v0, v8, v0, 0x50401003918; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo3919; GFX10-NEXT: v_perm_b32 v2, v7, v2, 0x50401003920; GFX10-NEXT: s_setpc_b64 s[30:31]3921;3922; GFX11-TRUE16-LABEL: v_maximumnum_v6bf16:3923; GFX11-TRUE16: ; %bb.0:3924; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3925; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v23926; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v53927; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, 03928; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v43929; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v03930; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v63931; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v73932; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v9.l3933; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v13934; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v33935; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v2.h, v5.h, vcc_lo3936; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v53937; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)3938; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v5.h, v9.h, s03939; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h3940; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v13, v133941; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v43942; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)3943; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v83944; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v133945; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.h, v9.h, vcc_lo3946; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v73947; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3948; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v9.h, s03949; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v6.l3950; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v103951; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v9.l3952; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v93953; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v4.h, vcc_lo3954; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3955; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v4.h, v9.h, s03956; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h3957; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v103958; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v10.h3959; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v9.h, vcc_lo3960; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v113961; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l3962; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)3963; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v9.h, s03964; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v7.l3965; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v123966; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v23967; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v93968; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v0.h, v3.h, vcc_lo3969; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3970; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v9.h, s03971; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h3972; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v113973; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v11.h3974; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v9.h, vcc_lo3975; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v123976; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l3977; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)3978; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v8.l, v9.h, s03979; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v8.l3980; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.l, v5.l, vcc_lo3981; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v93982; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)3983; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v5.l, v12.h, s33984; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v12.h3985; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v13986; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v93987; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3988; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v12.h, s03989; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h3990; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v12.h, s33991; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v5, v53992; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v03993; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v33994; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)3995; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.h, v9.h, s03996; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l3997; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v4.l, s33998; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.l3999; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v12, v124000; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v94001; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)4002; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v4.l, v1.h, s44003; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.h4004; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v11.h, s74005; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, s04006; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)4007; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v1, v94008; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.h, v1.h, s34009; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v9.h4010; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)4011; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s44012; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v5, v54013; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v10.h, s64014; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.h, v9.h, s34015; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v1.l4016; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)4017; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v3.l, s44018; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.l4019; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v1.h, s24020; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v94021; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)4022; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v3.l, v0.h, s54023; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.h4024; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.h, s34025; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)4026; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v0, v94027; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v9.h, v0.h, s44028; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.h4029; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)4030; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s54031; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v8.h4032; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v9.h, s44033; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l4034; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4035; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v8.h, s54036; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v94037; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)4038; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.l, v0.h, s14039; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, vcc_lo4040; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s44041; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]4042;4043; GFX11-FAKE16-LABEL: v_maximumnum_v6bf16:4044; GFX11-FAKE16: ; %bb.0:4045; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4046; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v24047; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v54048; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v24049; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v14050; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v04051; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v64052; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v54053; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v34054; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo4055; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)4056; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v94057; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v14058; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v44059; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo4060; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)4061; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v84062; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v44063; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v74064; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v64065; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4066; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v134067; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v04068; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo4069; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v114070; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v84071; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo4072; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64073; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo4074; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v144075; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo4076; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v74077; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)4078; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo4079; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v34080; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v134081; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v104082; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v94083; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)4084; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v144085; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v124086; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo4087; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134088; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v114089; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84090; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v74091; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)4092; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v154093; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo4094; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v94095; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo4096; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v124097; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)4098; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo4099; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134100; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v24101; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo4102; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v74103; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v104104; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo4105; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v124106; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v54107; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo4108; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v114109; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v04110; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo4111; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v94112; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v14113; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4114; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v104115; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo4116; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v114117; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v44118; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v24119; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v34120; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)4121; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v94122; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v54123; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo4124; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v104125; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v14126; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)4127; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v94128; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v44129; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)4130; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v104131; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v34132; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24133; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)4134; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v04135; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v114136; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo4137; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14138; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo4139; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54140; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo4141; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v04142; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo4143; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v44144; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v104145; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34146; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)4147; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v94148; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v114149; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v44150; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo4151; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)4152; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54153; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo4154; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v34155; GFX11-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x50401004156; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo4157; GFX11-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x50401004158; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)4159; GFX11-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x50401004160; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]4161;4162; GFX12-TRUE16-LABEL: v_maximumnum_v6bf16:4163; GFX12-TRUE16: ; %bb.0:4164; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x04165; GFX12-TRUE16-NEXT: s_wait_expcnt 0x04166; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x04167; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x04168; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x04169; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v24170; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v54171; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, 04172; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v44173; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v04174; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v64175; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v74176; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v9.l4177; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v14178; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v34179; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4180; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v2.h, v5.h, vcc_lo4181; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v54182; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4183; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)4184; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v5.h, v9.h, s04185; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h4186; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v13, v134187; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v44188; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)4189; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v84190; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v134191; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4192; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.h, v9.h, vcc_lo4193; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v74194; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4195; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)4196; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v9.h, s04197; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v6.l4198; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v104199; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v9.l4200; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v94201; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4202; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v4.h, vcc_lo4203; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4204; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4205; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v4.h, v9.h, s04206; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h4207; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v104208; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v10.h4209; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4210; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v10.h, v9.h, vcc_lo4211; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v114212; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l4213; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4214; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)4215; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v9.h, s04216; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v7.l4217; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v124218; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v24219; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v94220; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4221; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v0.h, v3.h, vcc_lo4222; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4223; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4224; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v9.h, s04225; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h4226; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v114227; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v11.h4228; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4229; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v9.h, vcc_lo4230; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v124231; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l4232; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4233; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)4234; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v8.l, v9.h, s04235; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v8.l4236; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4237; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.l, v5.l, vcc_lo4238; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v94239; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)4240; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v5.l, v12.h, s34241; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v12.h4242; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14243; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v94244; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4245; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4246; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v9.h, v12.h, s04247; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v9.h4248; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v12.h, s34249; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v5, v54250; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v04251; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v34252; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4253; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.h, v9.h, s04254; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l4255; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v4.l, s34256; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.l4257; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v12, v124258; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)4259; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v94260; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v4.l, v1.h, s44261; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.h4262; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v2.h, v11.h, s74263; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4264; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v4.h, s04265; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v1, v94266; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4267; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4268; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v9.h, v1.h, s34269; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v9.h4270; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s44271; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v5, v54272; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v10.h, s64273; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4274; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)4275; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.h, v9.h, s34276; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v1.l4277; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v3.l, s44278; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.l4279; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v1.h, s24280; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v94281; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)4282; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v3.l, v0.h, s54283; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.h4284; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4285; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.h, s34286; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)4287; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v0, v94288; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4289; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v9.h, v0.h, s44290; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v9.h4291; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)4292; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s54293; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v8.h4294; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4295; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.h, v9.h, s44296; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l4297; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4298; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v8.h, s54299; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v94300; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)4301; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v6.l, v0.h, s14302; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)4303; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v4.l, vcc_lo4304; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)4305; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s44306; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]4307;4308; GFX12-FAKE16-LABEL: v_maximumnum_v6bf16:4309; GFX12-FAKE16: ; %bb.0:4310; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x04311; GFX12-FAKE16-NEXT: s_wait_expcnt 0x04312; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x04313; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x04314; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x04315; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v24316; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v54317; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v24318; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v14319; GFX12-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v04320; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v64321; GFX12-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v54322; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v34323; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4324; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo4325; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)4326; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v94327; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v14328; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v44329; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4330; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v6, vcc_lo4331; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v84332; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v44333; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4334; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)4335; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v74336; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v64337; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v134338; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v04339; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4340; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc_lo4341; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v114342; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v84343; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4344; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo4345; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v64346; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4347; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc_lo4348; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v144349; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4350; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v15, vcc_lo4351; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v74352; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4353; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo4354; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v34355; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)4356; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v134357; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v104358; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4359; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v94360; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v144361; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v124362; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4363; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v9, v8, vcc_lo4364; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134365; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4366; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)4367; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v114368; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v84369; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4370; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v74371; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v154372; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4373; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v7, v12, vcc_lo4374; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v94375; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4376; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo4377; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v124378; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4379; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v10, v12, vcc_lo4380; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v134381; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v24382; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4383; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc_lo4384; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v74385; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v104386; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4387; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo4388; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v124389; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v54390; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4391; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo4392; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v114393; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v04394; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4395; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc_lo4396; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v94397; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4398; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v14399; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4400; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v104401; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4402; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo4403; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v114404; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v44405; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4406; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v24407; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v34408; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)4409; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v94410; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v54411; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4412; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo4413; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v104414; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4415; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v14416; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v94417; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4418; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v44419; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4420; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v104421; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4422; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v34423; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v24424; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4425; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v04426; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)4427; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v114428; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4429; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v3, v0, vcc_lo4430; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14431; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4432; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo4433; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v54434; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4435; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo4436; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v04437; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4438; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo4439; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v44440; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4441; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v104442; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v34443; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4444; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v94445; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v114446; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v44447; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4448; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc_lo4449; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)4450; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v54451; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4452; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc_lo4453; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v34454; GFX12-FAKE16-NEXT: v_perm_b32 v0, v7, v0, 0x50401004455; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)4456; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc_lo4457; GFX12-FAKE16-NEXT: v_perm_b32 v1, v8, v1, 0x50401004458; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)4459; GFX12-FAKE16-NEXT: v_perm_b32 v2, v6, v2, 0x50401004460; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]4461 %result = call <6 x bfloat> @llvm.maximumnum.v6bf16(<6 x bfloat> %x, <6 x bfloat> %y)4462 ret <6 x bfloat> %result4463}4464 4465define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {4466; GFX7-LABEL: v_maximumnum_v8bf16:4467; GFX7: ; %bb.0:4468; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4469; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v04470; GFX7-NEXT: v_mul_f32_e32 v8, 1.0, v84471; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v14472; GFX7-NEXT: v_mul_f32_e32 v9, 1.0, v94473; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v24474; GFX7-NEXT: v_mul_f32_e32 v10, 1.0, v104475; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v34476; GFX7-NEXT: v_mul_f32_e32 v11, 1.0, v114477; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v44478; GFX7-NEXT: v_mul_f32_e32 v12, 1.0, v124479; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v54480; GFX7-NEXT: v_mul_f32_e32 v13, 1.0, v134481; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v64482; GFX7-NEXT: v_mul_f32_e32 v14, 1.0, v144483; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v74484; GFX7-NEXT: v_mul_f32_e32 v15, 1.0, v154485; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v154486; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v74487; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v144488; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v64489; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v134490; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v54491; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v124492; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v44493; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v114494; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v34495; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v104496; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v24497; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v94498; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v14499; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v84500; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v04501; GFX7-NEXT: v_max_f32_e32 v7, v7, v154502; GFX7-NEXT: v_max_f32_e32 v6, v6, v144503; GFX7-NEXT: v_max_f32_e32 v5, v5, v134504; GFX7-NEXT: v_max_f32_e32 v4, v4, v124505; GFX7-NEXT: v_max_f32_e32 v3, v3, v114506; GFX7-NEXT: v_max_f32_e32 v2, v2, v104507; GFX7-NEXT: v_max_f32_e32 v1, v1, v94508; GFX7-NEXT: v_max_f32_e32 v0, v0, v84509; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v04510; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v14511; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v24512; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v34513; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v44514; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v54515; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v64516; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v74517; GFX7-NEXT: s_setpc_b64 s[30:31]4518;4519; GFX8-LABEL: v_maximumnum_v8bf16:4520; GFX8: ; %bb.0:4521; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4522; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v34523; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v74524; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v34525; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v84526; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v74527; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc4528; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v114529; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc4530; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v84531; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v94532; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v114533; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc4534; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v84535; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc4536; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v94537; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc4538; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v104539; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v94540; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v24541; GFX8-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc4542; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v64543; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v24544; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v94545; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v64546; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v10, vcc4547; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v124548; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v9, vcc4549; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v94550; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v104551; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v11, v124552; GFX8-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc4553; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v94554; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4555; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v104556; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc4557; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v114558; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v104559; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v14560; GFX8-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4561; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v54562; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v14563; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v104564; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v54565; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc4566; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v134567; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc4568; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v104569; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v114570; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v12, v134571; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc4572; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v104573; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc4574; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114575; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc4576; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v124577; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114578; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v04579; GFX8-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc4580; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v44581; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v04582; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v114583; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v44584; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc4585; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v144586; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v11, vcc4587; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v114588; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v124589; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v13, v144590; GFX8-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc4591; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114592; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc4593; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v124594; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc4595; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v134596; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v124597; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v34598; GFX8-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc4599; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v124600; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v74601; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc4602; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v124603; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc4604; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v74605; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v34606; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v13, v124607; GFX8-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc4608; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34609; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc4610; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v74611; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc4612; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v124613; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v74614; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v24615; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc4616; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v74617; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v64618; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc4619; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v74620; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc4621; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v64622; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v24623; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v12, v74624; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc4625; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24626; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc4627; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v64628; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc4629; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v74630; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v64631; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v14632; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc4633; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v64634; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v54635; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc4636; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v64637; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc4638; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v54639; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v14640; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v64641; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc4642; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14643; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc4644; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54645; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc4646; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v64647; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54648; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v04649; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc4650; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v54651; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v44652; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc4653; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v54654; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc4655; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v44656; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v04657; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v54658; GFX8-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc4659; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v04660; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc4661; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v44662; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc4663; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v54664; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v44665; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc4666; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v114667; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4668; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v104669; GFX8-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4670; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v94671; GFX8-NEXT: v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4672; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v84673; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4674; GFX8-NEXT: s_setpc_b64 s[30:31]4675;4676; GFX900-LABEL: v_maximumnum_v8bf16:4677; GFX900: ; %bb.0:4678; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4679; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v34680; GFX900-NEXT: v_lshrrev_b32_e32 v9, 16, v74681; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v34682; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v84683; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v74684; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc4685; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v114686; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc4687; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v84688; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v94689; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v114690; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc4691; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v84692; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc4693; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v94694; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc4695; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v104696; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v94697; GFX900-NEXT: v_and_b32_e32 v9, 0xffff0000, v24698; GFX900-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc4699; GFX900-NEXT: v_lshrrev_b32_e32 v10, 16, v64700; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v24701; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v94702; GFX900-NEXT: v_and_b32_e32 v12, 0xffff0000, v64703; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v10, vcc4704; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v124705; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v9, vcc4706; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v94707; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v104708; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v11, v124709; GFX900-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc4710; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v94711; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4712; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v104713; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc4714; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v114715; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v104716; GFX900-NEXT: v_and_b32_e32 v10, 0xffff0000, v14717; GFX900-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4718; GFX900-NEXT: v_lshrrev_b32_e32 v11, 16, v54719; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v14720; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v104721; GFX900-NEXT: v_and_b32_e32 v13, 0xffff0000, v54722; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc4723; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v134724; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc4725; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v104726; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v114727; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v12, v134728; GFX900-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc4729; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v104730; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc4731; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114732; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc4733; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v124734; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114735; GFX900-NEXT: v_and_b32_e32 v11, 0xffff0000, v04736; GFX900-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc4737; GFX900-NEXT: v_lshrrev_b32_e32 v12, 16, v44738; GFX900-NEXT: v_lshrrev_b32_e32 v13, 16, v04739; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v114740; GFX900-NEXT: v_and_b32_e32 v14, 0xffff0000, v44741; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc4742; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v144743; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v11, vcc4744; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v114745; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v124746; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v13, v144747; GFX900-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc4748; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114749; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc4750; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v124751; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc4752; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v134753; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v124754; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v34755; GFX900-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc4756; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v124757; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v74758; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc4759; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v124760; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc4761; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v74762; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v34763; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v13, v124764; GFX900-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc4765; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34766; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc4767; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v74768; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc4769; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v124770; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v74771; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v24772; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc4773; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v74774; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v64775; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc4776; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v74777; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc4778; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v64779; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v24780; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v12, v74781; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc4782; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24783; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc4784; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v64785; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc4786; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v74787; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v64788; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v14789; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc4790; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v64791; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v54792; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc4793; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v64794; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc4795; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v54796; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v14797; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v64798; GFX900-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc4799; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14800; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc4801; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54802; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc4803; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v64804; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54805; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v04806; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc4807; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v54808; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v44809; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc4810; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v54811; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc4812; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v44813; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v04814; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v54815; GFX900-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc4816; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v04817; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc4818; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v44819; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc4820; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v54821; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v44822; GFX900-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc4823; GFX900-NEXT: s_mov_b32 s4, 0x50401004824; GFX900-NEXT: v_perm_b32 v0, v11, v0, s44825; GFX900-NEXT: v_perm_b32 v1, v10, v1, s44826; GFX900-NEXT: v_perm_b32 v2, v9, v2, s44827; GFX900-NEXT: v_perm_b32 v3, v8, v3, s44828; GFX900-NEXT: s_setpc_b64 s[30:31]4829;4830; GFX950-LABEL: v_maximumnum_v8bf16:4831; GFX950: ; %bb.0:4832; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4833; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v34834; GFX950-NEXT: v_lshrrev_b32_e32 v9, 16, v74835; GFX950-NEXT: v_lshrrev_b32_e32 v10, 16, v34836; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v8, v84837; GFX950-NEXT: v_and_b32_e32 v11, 0xffff0000, v74838; GFX950-NEXT: v_and_b32_e32 v12, 0xffff0000, v64839; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc4840; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v114841; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v84842; GFX950-NEXT: v_and_b32_e32 v13, 0xffff0000, v54843; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc4844; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v94845; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v114846; GFX950-NEXT: v_lshrrev_b32_e32 v11, 16, v24847; GFX950-NEXT: v_and_b32_e32 v14, 0xffff0000, v44848; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc4849; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v84850; GFX950-NEXT: s_mov_b32 s0, 0x50401004851; GFX950-NEXT: s_nop 04852; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc4853; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v94854; GFX950-NEXT: s_nop 14855; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc4856; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v104857; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v94858; GFX950-NEXT: v_and_b32_e32 v9, 0xffff0000, v24859; GFX950-NEXT: s_nop 04860; GFX950-NEXT: v_cndmask_b32_e32 v8, v10, v8, vcc4861; GFX950-NEXT: v_lshrrev_b32_e32 v10, 16, v64862; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v94863; GFX950-NEXT: s_nop 14864; GFX950-NEXT: v_cndmask_b32_e32 v9, v11, v10, vcc4865; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v124866; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v94867; GFX950-NEXT: s_nop 04868; GFX950-NEXT: v_cndmask_b32_e32 v10, v10, v9, vcc4869; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v104870; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v11, v124871; GFX950-NEXT: v_lshrrev_b32_e32 v12, 16, v14872; GFX950-NEXT: s_nop 04873; GFX950-NEXT: v_cndmask_b32_e32 v11, v10, v9, vcc4874; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v94875; GFX950-NEXT: s_nop 14876; GFX950-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4877; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v104878; GFX950-NEXT: s_nop 14879; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc4880; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v114881; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v104882; GFX950-NEXT: v_and_b32_e32 v10, 0xffff0000, v14883; GFX950-NEXT: s_nop 04884; GFX950-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc4885; GFX950-NEXT: v_lshrrev_b32_e32 v11, 16, v54886; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v10, v104887; GFX950-NEXT: s_nop 14888; GFX950-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc4889; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v13, v134890; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v104891; GFX950-NEXT: s_nop 04892; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc4893; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v114894; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v12, v134895; GFX950-NEXT: v_lshrrev_b32_e32 v13, 16, v04896; GFX950-NEXT: s_nop 04897; GFX950-NEXT: v_cndmask_b32_e32 v12, v11, v10, vcc4898; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v104899; GFX950-NEXT: s_nop 14900; GFX950-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc4901; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114902; GFX950-NEXT: s_nop 14903; GFX950-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc4904; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v124905; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114906; GFX950-NEXT: v_and_b32_e32 v11, 0xffff0000, v04907; GFX950-NEXT: s_nop 04908; GFX950-NEXT: v_cndmask_b32_e32 v10, v12, v10, vcc4909; GFX950-NEXT: v_lshrrev_b32_e32 v12, 16, v44910; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v114911; GFX950-NEXT: s_nop 14912; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc4913; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v14, v144914; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v114915; GFX950-NEXT: s_nop 04916; GFX950-NEXT: v_cndmask_b32_e32 v12, v12, v11, vcc4917; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v124918; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v13, v144919; GFX950-NEXT: s_nop 14920; GFX950-NEXT: v_cndmask_b32_e32 v13, v12, v11, vcc4921; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114922; GFX950-NEXT: s_nop 14923; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc4924; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v124925; GFX950-NEXT: s_nop 14926; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc4927; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v134928; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v124929; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v34930; GFX950-NEXT: s_nop 04931; GFX950-NEXT: v_cndmask_b32_e32 v11, v13, v11, vcc4932; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v124933; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v74934; GFX950-NEXT: s_nop 04935; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc4936; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v124937; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v34938; GFX950-NEXT: s_nop 04939; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc4940; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v74941; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v13, v124942; GFX950-NEXT: s_nop 14943; GFX950-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc4944; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v34945; GFX950-NEXT: s_nop 14946; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc4947; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v74948; GFX950-NEXT: s_nop 14949; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc4950; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v124951; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v74952; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v24953; GFX950-NEXT: s_nop 04954; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc4955; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v74956; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v64957; GFX950-NEXT: v_perm_b32 v3, v8, v3, s04958; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc4959; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v74960; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v24961; GFX950-NEXT: s_nop 04962; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc4963; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v64964; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v12, v74965; GFX950-NEXT: s_nop 14966; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc4967; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v24968; GFX950-NEXT: s_nop 14969; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc4970; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v64971; GFX950-NEXT: s_nop 14972; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc4973; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v74974; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v64975; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v14976; GFX950-NEXT: s_nop 04977; GFX950-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc4978; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v64979; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v54980; GFX950-NEXT: v_perm_b32 v2, v9, v2, s04981; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc4982; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v64983; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v14984; GFX950-NEXT: s_nop 04985; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc4986; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v54987; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v64988; GFX950-NEXT: s_nop 14989; GFX950-NEXT: v_cndmask_b32_e32 v6, v5, v1, vcc4990; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v14991; GFX950-NEXT: s_nop 14992; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc4993; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v54994; GFX950-NEXT: s_nop 14995; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc4996; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v64997; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v54998; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v04999; GFX950-NEXT: s_nop 05000; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc5001; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v55002; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v45003; GFX950-NEXT: v_perm_b32 v1, v10, v1, s05004; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc5005; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v55006; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v05007; GFX950-NEXT: s_nop 05008; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc5009; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v45010; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v55011; GFX950-NEXT: s_nop 15012; GFX950-NEXT: v_cndmask_b32_e32 v5, v4, v0, vcc5013; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v05014; GFX950-NEXT: s_nop 15015; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc5016; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v45017; GFX950-NEXT: s_nop 15018; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc5019; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v55020; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v45021; GFX950-NEXT: s_nop 15022; GFX950-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc5023; GFX950-NEXT: v_perm_b32 v0, v11, v0, s05024; GFX950-NEXT: s_setpc_b64 s[30:31]5025;5026; GFX10-LABEL: v_maximumnum_v8bf16:5027; GFX10: ; %bb.0:5028; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5029; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v35030; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v75031; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v35032; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v75033; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v25034; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v85035; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v65036; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v55037; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v05038; GFX10-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo5039; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v115040; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v25041; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v65042; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v85043; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc_lo5044; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v105045; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v95046; GFX10-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo5047; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v145048; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v105049; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v15050; GFX10-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo5051; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155052; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo5053; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v85054; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v115055; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo5056; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v95057; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo5058; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v155059; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v15060; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v55061; GFX10-NEXT: v_cndmask_b32_e32 v14, v11, v10, vcc_lo5062; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135063; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v125064; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v145065; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo5066; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v105067; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc_lo5068; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155069; GFX10-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo5070; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135071; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v05072; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v45073; GFX10-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo5074; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115075; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v155076; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc_lo5077; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v95078; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v125079; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v9, vcc_lo5080; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135081; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v45082; GFX10-NEXT: v_cndmask_b32_e32 v12, v17, v16, vcc_lo5083; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v185084; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v75085; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc_lo5086; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v95087; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v35088; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo5089; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135090; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo5091; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v155092; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v135093; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo5094; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v125095; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v145096; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v115097; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo5098; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v165099; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v25100; GFX10-NEXT: v_cndmask_b32_e32 v15, v13, v12, vcc_lo5101; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v175102; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v55103; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo5104; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145105; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v35106; GFX10-NEXT: v_cndmask_b32_e32 v9, v11, v9, vcc_lo5107; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v125108; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v12, vcc_lo5109; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v75110; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v135111; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo5112; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v125113; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v155114; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v65115; GFX10-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo5116; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v165117; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo5118; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35119; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v25120; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo5121; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135122; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v15123; GFX10-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo5124; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v145125; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v05126; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v2, vcc_lo5127; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v75128; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v65129; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo5130; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135131; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v45132; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v125133; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo5134; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155135; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v15136; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo5137; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v175138; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v05139; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo5140; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v145141; GFX10-NEXT: v_cndmask_b32_e32 v14, v6, v2, vcc_lo5142; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135143; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v55144; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc_lo5145; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25146; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v45147; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo5148; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v135149; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v145150; GFX10-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo5151; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65152; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo5153; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v165154; GFX10-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo5155; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15156; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo5157; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v05158; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo5159; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55160; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo5161; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v45162; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v65163; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo5164; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v155165; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v135166; GFX10-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo5167; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55168; GFX10-NEXT: v_perm_b32 v2, v10, v2, 0x50401005169; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo5170; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v45171; GFX10-NEXT: v_perm_b32 v0, v11, v0, 0x50401005172; GFX10-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo5173; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v75174; GFX10-NEXT: v_perm_b32 v1, v9, v1, 0x50401005175; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo5176; GFX10-NEXT: v_perm_b32 v3, v8, v3, 0x50401005177; GFX10-NEXT: s_setpc_b64 s[30:31]5178;5179; GFX11-TRUE16-LABEL: v_maximumnum_v8bf16:5180; GFX11-TRUE16: ; %bb.0:5181; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5182; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v35183; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v75184; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, 05185; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v65186; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v55187; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v85188; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v95189; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l5190; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v25191; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.l5192; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v3.h, v7.h, vcc_lo5193; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v05194; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v45195; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v75196; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)5197; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v7.h, v12.h, s05198; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5199; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v175200; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v65201; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)5202; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v115203; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v17, v175204; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v12.h, vcc_lo5205; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v95206; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)5207; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.l, v12.h, s05208; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l5209; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v105210; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v15211; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v125212; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.h, v6.h, vcc_lo5213; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5214; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v6.h, v12.h, s05215; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5216; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v135217; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v13.h5218; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v13.h, v12.h, vcc_lo5219; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v105220; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)5221; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v12.h, s05222; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v9.l5223; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v145224; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l5225; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v125226; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v1.h, v5.h, vcc_lo5227; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5228; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v5.h, v12.h, s05229; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5230; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v145231; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.h, v12.h, vcc_lo5232; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155233; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l5234; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)5235; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.l, v12.h, s05236; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l5237; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v165238; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v35239; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v125240; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v0.h, v4.h, vcc_lo5241; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5242; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v4.h, v12.h, s05243; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5244; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v155245; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v15.h, v12.h, vcc_lo5246; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v165247; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l5248; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)5249; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v12.h, s05250; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v11.l5251; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.l, v7.l, vcc_lo5252; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v125253; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)5254; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v7.l, v16.h, s45255; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v16.h5256; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v25257; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v125258; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5259; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v16.h, s05260; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5261; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v16.h, s45262; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v7, v75263; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v15264; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v55265; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)5266; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.h, v12.h, s05267; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v3.l5268; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v6.l, s45269; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v12.l5270; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v16, v165271; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v45272; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v125273; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v6.l, v2.h, s55274; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v2.h5275; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5276; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v165277; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v6.h, s05278; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)5279; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v2, v125280; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v12.h, v2.h, s45281; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v12.h5282; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)5283; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v2.h, s55284; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v75285; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v05286; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.h, v13.h, s85287; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.h, v12.h, s45288; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l5289; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v5.l, s55290; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v12.l5291; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.l, v2.h, s25292; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5293; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v125294; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v5.l, v1.h, s65295; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.h5296; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5297; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.h, s45298; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v1, v125299; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5300; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.h, s55301; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v12.h5302; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s65303; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v7, v75304; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5305; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v12.h, s55306; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v1.l5307; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v4.l, s65308; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v12.l5309; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5310; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v125311; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.l, v0.h, s75312; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.h5313; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5314; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s55315; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v0, v125316; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v12.h5317; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)5318; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v12.h, v0.h, s65319; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v11.h5320; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s75321; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)5322; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.h, v11.h, s65323; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v14.h5324; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v15.h5325; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v12.h, s95326; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l5327; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5328; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v14.h, s65329; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v15.h, s75330; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v1.h, s15331; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5332; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v125333; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v0.h, s35334; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)5335; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v5.l, vcc_lo5336; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s15337; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]5338;5339; GFX11-FAKE16-LABEL: v_maximumnum_v8bf16:5340; GFX11-FAKE16: ; %bb.0:5341; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5342; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v35343; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v75344; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v35345; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v25346; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v55347; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v85348; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v75349; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v05350; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo5351; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)5352; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v115353; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v65354; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v25355; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)5356; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v105357; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v85358; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v95359; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo5360; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5361; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v145362; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v65363; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v105364; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo5365; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)5366; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155367; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo5368; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v85369; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v15370; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v95371; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5372; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v115373; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v155374; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v15375; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v55376; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135377; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)5378; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo5379; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v105380; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v125381; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155382; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)5383; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo5384; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135385; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v05386; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v45387; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo5388; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115389; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v155390; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v95391; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)5392; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v125393; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v145394; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135395; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v75396; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v185397; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v45398; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v95399; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35400; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)5401; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135402; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo5403; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v155404; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v135405; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v145406; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo5407; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v125408; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)5409; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v165410; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v115411; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v25412; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v175413; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo5414; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145415; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35416; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v125417; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)5418; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v75419; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v135420; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo5421; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5422; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v125423; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v65424; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo5425; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v165426; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v155427; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35428; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)5429; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v25430; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135431; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15432; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo5433; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v145434; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v05435; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v75436; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v55437; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5438; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v65439; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135440; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo5441; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155442; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo5443; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v175444; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)5445; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v05446; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo5447; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v145448; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v125449; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v45450; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135451; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v55452; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25453; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)5454; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v45455; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v15456; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v135457; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v145458; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo5459; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65460; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo5461; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v165462; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo5463; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15464; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo5465; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v05466; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)5467; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo5468; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55469; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo5470; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v45471; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)5472; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v65473; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v155474; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo5475; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55476; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)5477; GFX11-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x50401005478; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo5479; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v135480; GFX11-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x50401005481; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)5482; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v45483; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo5484; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v75485; GFX11-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x50401005486; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo5487; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)5488; GFX11-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x50401005489; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]5490;5491; GFX12-TRUE16-LABEL: v_maximumnum_v8bf16:5492; GFX12-TRUE16: ; %bb.0:5493; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x05494; GFX12-TRUE16-NEXT: s_wait_expcnt 0x05495; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x05496; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x05497; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x05498; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v35499; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v75500; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, 05501; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v65502; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v55503; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v85504; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v95505; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l5506; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v25507; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v12.l5508; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5509; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v3.h, v7.h, vcc_lo5510; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v05511; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v45512; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v75513; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5514; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v7.h, v12.h, s05515; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5516; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)5517; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v175518; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v65519; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v115520; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)5521; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v17, v175522; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5523; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v11.h, v12.h, vcc_lo5524; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v95525; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5526; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.l, v12.h, s05527; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l5528; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v105529; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v15530; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)5531; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v125532; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5533; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v2.h, v6.h, vcc_lo5534; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5535; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v6.h, v12.h, s05536; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5537; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5538; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v135539; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v13.h5540; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5541; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v13.h, v12.h, vcc_lo5542; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v105543; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5544; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)5545; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v12.h, s05546; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v9.l5547; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v145548; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l5549; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v125550; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5551; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v1.h, v5.h, vcc_lo5552; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5553; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5554; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v5.h, v12.h, s05555; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5556; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v145557; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5558; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v14.h, v12.h, vcc_lo5559; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155560; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v12.l5561; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5562; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)5563; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.l, v12.h, s05564; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l5565; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v165566; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v35567; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v125568; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5569; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v0.h, v4.h, vcc_lo5570; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5571; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5572; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v4.h, v12.h, s05573; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5574; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v12, v155575; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5576; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v15.h, v12.h, vcc_lo5577; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v165578; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v12.l5579; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5580; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)5581; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v12.h, s05582; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v11.l5583; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5584; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.l, v7.l, vcc_lo5585; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v125586; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)5587; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v7.l, v16.h, s45588; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v16.h5589; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v25590; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v125591; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5592; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5593; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v12.h, v16.h, s05594; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v12.h5595; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v16.h, s45596; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v7, v75597; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v15598; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v55599; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5600; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.h, v12.h, s05601; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v3.l5602; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v6.l, s45603; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v12.l5604; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v16, v165605; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v45606; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v125607; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v6.l, v2.h, s55608; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v2.h5609; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)5610; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v16, v165611; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5612; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v6.h, s05613; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v2, v125614; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5615; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v12.h, v2.h, s45616; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v12.h5617; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5618; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v2.h, s55619; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v7, v75620; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v05621; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.h, v13.h, s85622; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5623; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.h, v12.h, s45624; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l5625; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v5.l, s55626; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v12.l5627; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v9.l, v2.h, s25628; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5629; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v125630; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v5.l, v1.h, s65631; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.h5632; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5633; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5634; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.h, s45635; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v1, v125636; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5637; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5638; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v12.h, v1.h, s55639; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v12.h5640; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v1.h, s65641; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v7, v75642; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5643; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5644; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v12.h, s55645; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v1.l5646; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v4.l, s65647; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v12.l5648; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5649; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v125650; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.l, v0.h, s75651; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.h5652; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5653; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5654; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s55655; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v0, v125656; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v12.h5657; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5658; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)5659; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v12.h, v0.h, s65660; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v11.h5661; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s75662; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5663; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5664; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v8.h, v11.h, s65665; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v14.h5666; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v15.h5667; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.h, v12.h, s95668; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l5669; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5670; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v10.h, v14.h, s65671; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.h, v15.h, s75672; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v8.l, v1.h, s15673; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v125674; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)5675; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v0.h, s35676; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)5677; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v11.l, v5.l, vcc_lo5678; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)5679; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s15680; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]5681;5682; GFX12-FAKE16-LABEL: v_maximumnum_v8bf16:5683; GFX12-FAKE16: ; %bb.0:5684; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x05685; GFX12-FAKE16-NEXT: s_wait_expcnt 0x05686; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x05687; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x05688; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x05689; GFX12-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v35690; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v75691; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v35692; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v25693; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v55694; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v85695; GFX12-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v75696; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v05697; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5698; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v9, vcc_lo5699; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)5700; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v115701; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v65702; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5703; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v25704; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)5705; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v105706; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v85707; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v95708; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5709; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v11, vcc_lo5710; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5711; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v145712; GFX12-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v65713; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v105714; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5715; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v8, vcc_lo5716; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5717; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155718; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5719; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v10, vcc_lo5720; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v85721; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5722; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v15723; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v95724; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5725; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5726; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v115727; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v155728; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v15729; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5730; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v55731; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135732; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5733; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo5734; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v105735; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5736; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v125737; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155738; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5739; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v16, v9, vcc_lo5740; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5741; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135742; GFX12-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v05743; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v45744; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5745; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo5746; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115747; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v155748; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5749; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v95750; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)5751; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v125752; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5753; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v145754; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135755; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5756; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v75757; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5758; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v185759; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5760; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v45761; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v95762; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5763; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35764; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)5765; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135766; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5767; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v16, v12, vcc_lo5768; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v155769; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5770; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v135771; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v145772; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5773; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo5774; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v125775; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)5776; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v165777; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v115778; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5779; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v25780; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v175781; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5782; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v3, vcc_lo5783; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v145784; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5785; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35786; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v125787; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5788; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v75789; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v135790; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5791; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)5792; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc_lo5793; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v125794; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v65795; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5796; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc_lo5797; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v165798; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5799; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v155800; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v35801; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5802; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)5803; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v25804; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v135805; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v15806; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5807; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v15, v11, vcc_lo5808; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v145809; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5810; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v05811; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v75812; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v55813; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5814; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)5815; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v65816; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135817; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5818; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo5819; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v155820; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5821; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo5822; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v175823; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)5824; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v05825; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5826; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc_lo5827; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v145828; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5829; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v125830; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v45831; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)5832; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v135833; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5834; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v55835; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v25836; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v45837; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5838; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v15839; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)5840; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v135841; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v145842; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5843; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v5, v1, vcc_lo5844; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v65845; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5846; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo5847; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v165848; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5849; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v0, vcc_lo5850; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15851; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5852; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo5853; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v05854; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5855; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo5856; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v55857; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5858; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo5859; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v45860; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5861; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v65862; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v155863; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5864; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v14, v2, vcc_lo5865; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)5866; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v55867; GFX12-FAKE16-NEXT: v_perm_b32 v2, v10, v2, 0x50401005868; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5869; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo5870; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v135871; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5872; GFX12-FAKE16-NEXT: v_perm_b32 v0, v11, v0, 0x50401005873; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v45874; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5875; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc_lo5876; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v75877; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)5878; GFX12-FAKE16-NEXT: v_perm_b32 v1, v9, v1, 0x50401005879; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)5880; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc_lo5881; GFX12-FAKE16-NEXT: v_perm_b32 v3, v8, v3, 0x50401005882; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]5883 %result = call <8 x bfloat> @llvm.maximumnum.v8bf16(<8 x bfloat> %x, <8 x bfloat> %y)5884 ret <8 x bfloat> %result5885}5886 5887define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {5888; GFX7-LABEL: v_maximumnum_v16bf16:5889; GFX7: ; %bb.0:5890; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5891; GFX7-NEXT: v_mul_f32_e32 v11, 1.0, v115892; GFX7-NEXT: v_mul_f32_e32 v27, 1.0, v275893; GFX7-NEXT: v_and_b32_e32 v27, 0xffff0000, v275894; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v115895; GFX7-NEXT: v_max_f32_e32 v11, v11, v275896; GFX7-NEXT: buffer_load_dword v27, off, s[0:3], s325897; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v65898; GFX7-NEXT: v_mul_f32_e32 v22, 1.0, v225899; GFX7-NEXT: v_and_b32_e32 v22, 0xffff0000, v225900; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v65901; GFX7-NEXT: v_mul_f32_e32 v14, 1.0, v145902; GFX7-NEXT: v_mul_f32_e32 v30, 1.0, v305903; GFX7-NEXT: v_mul_f32_e32 v13, 1.0, v135904; GFX7-NEXT: v_mul_f32_e32 v29, 1.0, v295905; GFX7-NEXT: v_mul_f32_e32 v12, 1.0, v125906; GFX7-NEXT: v_mul_f32_e32 v28, 1.0, v285907; GFX7-NEXT: v_mul_f32_e32 v10, 1.0, v105908; GFX7-NEXT: v_mul_f32_e32 v26, 1.0, v265909; GFX7-NEXT: v_mul_f32_e32 v9, 1.0, v95910; GFX7-NEXT: v_mul_f32_e32 v25, 1.0, v255911; GFX7-NEXT: v_mul_f32_e32 v8, 1.0, v85912; GFX7-NEXT: v_mul_f32_e32 v24, 1.0, v245913; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v75914; GFX7-NEXT: v_mul_f32_e32 v23, 1.0, v235915; GFX7-NEXT: v_mul_f32_e32 v15, 1.0, v155916; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v55917; GFX7-NEXT: v_max_f32_e32 v6, v6, v225918; GFX7-NEXT: v_mul_f32_e32 v21, 1.0, v215919; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v45920; GFX7-NEXT: v_mul_f32_e32 v20, 1.0, v205921; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v35922; GFX7-NEXT: v_mul_f32_e32 v19, 1.0, v195923; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v25924; GFX7-NEXT: v_mul_f32_e32 v18, 1.0, v185925; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v15926; GFX7-NEXT: v_mul_f32_e32 v17, 1.0, v175927; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v05928; GFX7-NEXT: v_mul_f32_e32 v16, 1.0, v165929; GFX7-NEXT: v_and_b32_e32 v30, 0xffff0000, v305930; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v145931; GFX7-NEXT: v_and_b32_e32 v29, 0xffff0000, v295932; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v135933; GFX7-NEXT: v_and_b32_e32 v28, 0xffff0000, v285934; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v125935; GFX7-NEXT: v_and_b32_e32 v26, 0xffff0000, v265936; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v105937; GFX7-NEXT: v_and_b32_e32 v25, 0xffff0000, v255938; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v95939; GFX7-NEXT: v_and_b32_e32 v24, 0xffff0000, v245940; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v85941; GFX7-NEXT: v_and_b32_e32 v23, 0xffff0000, v235942; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v75943; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v155944; GFX7-NEXT: v_and_b32_e32 v21, 0xffff0000, v215945; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v55946; GFX7-NEXT: v_and_b32_e32 v20, 0xffff0000, v205947; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v45948; GFX7-NEXT: v_and_b32_e32 v19, 0xffff0000, v195949; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v35950; GFX7-NEXT: v_and_b32_e32 v18, 0xffff0000, v185951; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v25952; GFX7-NEXT: v_and_b32_e32 v17, 0xffff0000, v175953; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v15954; GFX7-NEXT: v_and_b32_e32 v16, 0xffff0000, v165955; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v05956; GFX7-NEXT: v_max_f32_e32 v14, v14, v305957; GFX7-NEXT: v_max_f32_e32 v13, v13, v295958; GFX7-NEXT: v_max_f32_e32 v12, v12, v285959; GFX7-NEXT: v_max_f32_e32 v10, v10, v265960; GFX7-NEXT: v_max_f32_e32 v9, v9, v255961; GFX7-NEXT: v_max_f32_e32 v8, v8, v245962; GFX7-NEXT: v_max_f32_e32 v7, v7, v235963; GFX7-NEXT: v_max_f32_e32 v5, v5, v215964; GFX7-NEXT: v_max_f32_e32 v4, v4, v205965; GFX7-NEXT: v_max_f32_e32 v3, v3, v195966; GFX7-NEXT: v_max_f32_e32 v2, v2, v185967; GFX7-NEXT: v_max_f32_e32 v1, v1, v175968; GFX7-NEXT: v_max_f32_e32 v0, v0, v165969; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v05970; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v15971; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v25972; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v35973; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v45974; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v55975; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v65976; GFX7-NEXT: s_waitcnt vmcnt(0)5977; GFX7-NEXT: v_mul_f32_e32 v22, 1.0, v275978; GFX7-NEXT: v_and_b32_e32 v22, 0xffff0000, v225979; GFX7-NEXT: v_max_f32_e32 v15, v15, v225980; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v75981; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v85982; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v95983; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v105984; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v115985; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v125986; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v135987; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v145988; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v155989; GFX7-NEXT: s_setpc_b64 s[30:31]5990;5991; GFX8-LABEL: v_maximumnum_v16bf16:5992; GFX8: ; %bb.0:5993; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5994; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v75995; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v16, v165996; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v155997; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v75998; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v155999; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc6000; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v196001; GFX8-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc6002; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v176003; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v166004; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v18, v196005; GFX8-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc6006; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v176007; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc6008; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v166009; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc6010; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v186011; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v176012; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v66013; GFX8-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc6014; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v176015; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v146016; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v66017; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v146018; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v17, vcc6019; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v206020; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc6021; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v186022; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v176023; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v19, v206024; GFX8-NEXT: v_cndmask_b32_e32 v19, v17, v18, vcc6025; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v186026; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc6027; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v176028; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc6029; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v196030; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v186031; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v56032; GFX8-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc6033; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v186034; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v136035; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v56036; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v136037; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v18, vcc6038; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v216039; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc6040; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v196041; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v186042; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v20, v216043; GFX8-NEXT: v_cndmask_b32_e32 v20, v18, v19, vcc6044; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v196045; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc6046; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v186047; GFX8-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc6048; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v206049; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v196050; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v46051; GFX8-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc6052; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v196053; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v126054; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v46055; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v126056; GFX8-NEXT: v_cndmask_b32_e32 v20, v20, v19, vcc6057; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v226058; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc6059; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v206060; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v196061; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v21, v226062; GFX8-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc6063; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v206064; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc6065; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v196066; GFX8-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc6067; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v216068; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v206069; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v36070; GFX8-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc6071; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v206072; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v116073; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v36074; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v116075; GFX8-NEXT: v_cndmask_b32_e32 v21, v21, v20, vcc6076; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v236077; GFX8-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc6078; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v216079; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v206080; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v22, v236081; GFX8-NEXT: v_cndmask_b32_e32 v22, v20, v21, vcc6082; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v216083; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc6084; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v206085; GFX8-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc6086; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v226087; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v216088; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v26089; GFX8-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc6090; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v216091; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v106092; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v26093; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v106094; GFX8-NEXT: v_cndmask_b32_e32 v22, v22, v21, vcc6095; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v246096; GFX8-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc6097; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v226098; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v216099; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v23, v246100; GFX8-NEXT: v_cndmask_b32_e32 v23, v21, v22, vcc6101; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v226102; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc6103; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v216104; GFX8-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc6105; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v236106; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v226107; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v16108; GFX8-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc6109; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v226110; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v96111; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v16112; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v96113; GFX8-NEXT: v_cndmask_b32_e32 v23, v23, v22, vcc6114; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v256115; GFX8-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc6116; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v236117; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v226118; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v24, v256119; GFX8-NEXT: v_cndmask_b32_e32 v24, v22, v23, vcc6120; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v236121; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc6122; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v226123; GFX8-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc6124; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v246125; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v236126; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v06127; GFX8-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc6128; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v236129; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v86130; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v06131; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v86132; GFX8-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc6133; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v266134; GFX8-NEXT: v_cndmask_b32_e32 v23, v23, v24, vcc6135; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v246136; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v236137; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v25, v266138; GFX8-NEXT: v_cndmask_b32_e32 v25, v23, v24, vcc6139; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v246140; GFX8-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc6141; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v236142; GFX8-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc6143; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v256144; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v246145; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v76146; GFX8-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc6147; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v246148; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v156149; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc6150; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v246151; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc6152; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v156153; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v76154; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v25, v246155; GFX8-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc6156; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v76157; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc6158; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v156159; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc6160; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v246161; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v156162; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v66163; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc6164; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v15, v156165; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v146166; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc6167; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v15, v156168; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc6169; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v146170; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v66171; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v24, v156172; GFX8-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc6173; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v66174; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc6175; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v146176; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc6177; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v156178; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v146179; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v56180; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc6181; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v146182; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v136183; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc6184; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v14, v146185; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc6186; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v136187; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v56188; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v15, v146189; GFX8-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc6190; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v56191; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6192; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v136193; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc6194; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v146195; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v136196; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v46197; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6198; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v136199; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v126200; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc6201; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v13, v136202; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc6203; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v126204; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v46205; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v14, v136206; GFX8-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc6207; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v46208; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc6209; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v126210; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc6211; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v136212; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v126213; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v36214; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc6215; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v126216; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v116217; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc6218; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v12, v126219; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc6220; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v116221; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v36222; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v13, v126223; GFX8-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc6224; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36225; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc6226; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v116227; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc6228; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v126229; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v116230; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v26231; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc6232; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v116233; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v106234; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc6235; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v11, v116236; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc6237; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v106238; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v26239; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v12, v116240; GFX8-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc6241; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v26242; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6243; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v106244; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc6245; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v116246; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v106247; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v16248; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6249; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v106250; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v96251; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc6252; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v10, v106253; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc6254; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v96255; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v16256; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v11, v106257; GFX8-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc6258; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16259; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc6260; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v96261; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc6262; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v106263; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v96264; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v06265; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc6266; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v96267; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v86268; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc6269; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v9, v96270; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc6271; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v86272; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v06273; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v10, v96274; GFX8-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc6275; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v06276; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc6277; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v86278; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc6279; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v96280; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v86281; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc6282; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v236283; GFX8-NEXT: v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6284; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v226285; GFX8-NEXT: v_or_b32_sdwa v1, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6286; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v216287; GFX8-NEXT: v_or_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6288; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v206289; GFX8-NEXT: v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6290; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v196291; GFX8-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6292; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v186293; GFX8-NEXT: v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6294; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v176295; GFX8-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6296; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v166297; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6298; GFX8-NEXT: s_setpc_b64 s[30:31]6299;6300; GFX900-LABEL: v_maximumnum_v16bf16:6301; GFX900: ; %bb.0:6302; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6303; GFX900-NEXT: v_and_b32_e32 v16, 0xffff0000, v76304; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v16, v166305; GFX900-NEXT: v_lshrrev_b32_e32 v16, 16, v156306; GFX900-NEXT: v_lshrrev_b32_e32 v17, 16, v76307; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v156308; GFX900-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc6309; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v196310; GFX900-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc6311; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v176312; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v166313; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v18, v196314; GFX900-NEXT: v_cndmask_b32_e32 v18, v16, v17, vcc6315; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v176316; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc6317; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v166318; GFX900-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc6319; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v186320; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v176321; GFX900-NEXT: v_and_b32_e32 v17, 0xffff0000, v66322; GFX900-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc6323; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v176324; GFX900-NEXT: v_lshrrev_b32_e32 v17, 16, v146325; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v66326; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v146327; GFX900-NEXT: v_cndmask_b32_e32 v18, v18, v17, vcc6328; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v206329; GFX900-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc6330; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v186331; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v176332; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v19, v206333; GFX900-NEXT: v_cndmask_b32_e32 v19, v17, v18, vcc6334; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v186335; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc6336; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v176337; GFX900-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc6338; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v196339; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v186340; GFX900-NEXT: v_and_b32_e32 v18, 0xffff0000, v56341; GFX900-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc6342; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v186343; GFX900-NEXT: v_lshrrev_b32_e32 v18, 16, v136344; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v56345; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v136346; GFX900-NEXT: v_cndmask_b32_e32 v19, v19, v18, vcc6347; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v216348; GFX900-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc6349; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v196350; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v186351; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v20, v216352; GFX900-NEXT: v_cndmask_b32_e32 v20, v18, v19, vcc6353; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v196354; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc6355; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v186356; GFX900-NEXT: v_cndmask_b32_e32 v18, v19, v18, vcc6357; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v206358; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v196359; GFX900-NEXT: v_and_b32_e32 v19, 0xffff0000, v46360; GFX900-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc6361; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v196362; GFX900-NEXT: v_lshrrev_b32_e32 v19, 16, v126363; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v46364; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v126365; GFX900-NEXT: v_cndmask_b32_e32 v20, v20, v19, vcc6366; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v226367; GFX900-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc6368; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v206369; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v196370; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v21, v226371; GFX900-NEXT: v_cndmask_b32_e32 v21, v19, v20, vcc6372; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v206373; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc6374; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v196375; GFX900-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc6376; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v216377; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v206378; GFX900-NEXT: v_and_b32_e32 v20, 0xffff0000, v36379; GFX900-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc6380; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v206381; GFX900-NEXT: v_lshrrev_b32_e32 v20, 16, v116382; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v36383; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v116384; GFX900-NEXT: v_cndmask_b32_e32 v21, v21, v20, vcc6385; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v236386; GFX900-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc6387; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v216388; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v206389; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v22, v236390; GFX900-NEXT: v_cndmask_b32_e32 v22, v20, v21, vcc6391; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v216392; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc6393; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v206394; GFX900-NEXT: v_cndmask_b32_e32 v20, v21, v20, vcc6395; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v226396; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v216397; GFX900-NEXT: v_and_b32_e32 v21, 0xffff0000, v26398; GFX900-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc6399; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v216400; GFX900-NEXT: v_lshrrev_b32_e32 v21, 16, v106401; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v26402; GFX900-NEXT: v_and_b32_e32 v24, 0xffff0000, v106403; GFX900-NEXT: v_cndmask_b32_e32 v22, v22, v21, vcc6404; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v246405; GFX900-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc6406; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v226407; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v216408; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v23, v246409; GFX900-NEXT: v_cndmask_b32_e32 v23, v21, v22, vcc6410; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v226411; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc6412; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v216413; GFX900-NEXT: v_cndmask_b32_e32 v21, v22, v21, vcc6414; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v236415; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v226416; GFX900-NEXT: v_and_b32_e32 v22, 0xffff0000, v16417; GFX900-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc6418; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v226419; GFX900-NEXT: v_lshrrev_b32_e32 v22, 16, v96420; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v16421; GFX900-NEXT: v_and_b32_e32 v25, 0xffff0000, v96422; GFX900-NEXT: v_cndmask_b32_e32 v23, v23, v22, vcc6423; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v256424; GFX900-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc6425; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v236426; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v226427; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v24, v256428; GFX900-NEXT: v_cndmask_b32_e32 v24, v22, v23, vcc6429; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v236430; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc6431; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v226432; GFX900-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc6433; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v246434; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v236435; GFX900-NEXT: v_and_b32_e32 v23, 0xffff0000, v06436; GFX900-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc6437; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v236438; GFX900-NEXT: v_lshrrev_b32_e32 v23, 16, v86439; GFX900-NEXT: v_lshrrev_b32_e32 v24, 16, v06440; GFX900-NEXT: v_and_b32_e32 v26, 0xffff0000, v86441; GFX900-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc6442; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v266443; GFX900-NEXT: v_cndmask_b32_e32 v23, v23, v24, vcc6444; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v246445; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v236446; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v25, v266447; GFX900-NEXT: v_cndmask_b32_e32 v25, v23, v24, vcc6448; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v246449; GFX900-NEXT: v_cndmask_b32_e32 v24, v25, v24, vcc6450; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v236451; GFX900-NEXT: v_cndmask_b32_e32 v23, v24, v23, vcc6452; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v256453; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v246454; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v76455; GFX900-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc6456; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v246457; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v156458; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc6459; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v246460; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc6461; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v156462; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v76463; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v25, v246464; GFX900-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc6465; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v76466; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc6467; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v156468; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc6469; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v246470; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v156471; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v66472; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc6473; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v15, v156474; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v146475; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc6476; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v15, v156477; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc6478; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v146479; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v66480; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v24, v156481; GFX900-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc6482; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v66483; GFX900-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc6484; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v146485; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc6486; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v156487; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v146488; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v56489; GFX900-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc6490; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v146491; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v136492; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc6493; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v14, v146494; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc6495; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v136496; GFX900-NEXT: v_lshlrev_b32_e32 v15, 16, v56497; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v15, v146498; GFX900-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc6499; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v56500; GFX900-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6501; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v136502; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc6503; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v146504; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v136505; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v46506; GFX900-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6507; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v136508; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v126509; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc6510; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v13, v136511; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc6512; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v126513; GFX900-NEXT: v_lshlrev_b32_e32 v14, 16, v46514; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v14, v136515; GFX900-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc6516; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v46517; GFX900-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc6518; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v126519; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc6520; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v136521; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v126522; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v36523; GFX900-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc6524; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v126525; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v116526; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc6527; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v12, v126528; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc6529; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v116530; GFX900-NEXT: v_lshlrev_b32_e32 v13, 16, v36531; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v13, v126532; GFX900-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc6533; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36534; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc6535; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v116536; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc6537; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v126538; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v116539; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v26540; GFX900-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc6541; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v116542; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v106543; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc6544; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v11, v116545; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc6546; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v106547; GFX900-NEXT: v_lshlrev_b32_e32 v12, 16, v26548; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v12, v116549; GFX900-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc6550; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v26551; GFX900-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6552; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v106553; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc6554; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v116555; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v106556; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v16557; GFX900-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6558; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v106559; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v96560; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc6561; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v10, v106562; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc6563; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v96564; GFX900-NEXT: v_lshlrev_b32_e32 v11, 16, v16565; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v11, v106566; GFX900-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc6567; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16568; GFX900-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc6569; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v96570; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc6571; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v106572; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v96573; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v06574; GFX900-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc6575; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v96576; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v86577; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc6578; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v9, v96579; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc6580; GFX900-NEXT: v_lshlrev_b32_e32 v9, 16, v86581; GFX900-NEXT: v_lshlrev_b32_e32 v10, 16, v06582; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v10, v96583; GFX900-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc6584; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v06585; GFX900-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc6586; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v86587; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc6588; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v96589; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v86590; GFX900-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc6591; GFX900-NEXT: s_mov_b32 s4, 0x50401006592; GFX900-NEXT: v_perm_b32 v0, v23, v0, s46593; GFX900-NEXT: v_perm_b32 v1, v22, v1, s46594; GFX900-NEXT: v_perm_b32 v2, v21, v2, s46595; GFX900-NEXT: v_perm_b32 v3, v20, v3, s46596; GFX900-NEXT: v_perm_b32 v4, v19, v4, s46597; GFX900-NEXT: v_perm_b32 v5, v18, v5, s46598; GFX900-NEXT: v_perm_b32 v6, v17, v6, s46599; GFX900-NEXT: v_perm_b32 v7, v16, v7, s46600; GFX900-NEXT: s_setpc_b64 s[30:31]6601;6602; GFX950-LABEL: v_maximumnum_v16bf16:6603; GFX950: ; %bb.0:6604; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6605; GFX950-NEXT: v_and_b32_e32 v16, 0xffff0000, v76606; GFX950-NEXT: v_lshrrev_b32_e32 v17, 16, v156607; GFX950-NEXT: v_lshrrev_b32_e32 v18, 16, v76608; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v16, v166609; GFX950-NEXT: v_and_b32_e32 v19, 0xffff0000, v156610; GFX950-NEXT: v_and_b32_e32 v20, 0xffff0000, v146611; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc6612; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v196613; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v166614; GFX950-NEXT: v_and_b32_e32 v21, 0xffff0000, v136615; GFX950-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc6616; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v176617; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v18, v196618; GFX950-NEXT: v_lshrrev_b32_e32 v19, 16, v66619; GFX950-NEXT: v_and_b32_e32 v22, 0xffff0000, v126620; GFX950-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc6621; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v166622; GFX950-NEXT: v_and_b32_e32 v23, 0xffff0000, v116623; GFX950-NEXT: v_and_b32_e32 v24, 0xffff0000, v106624; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc6625; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v176626; GFX950-NEXT: v_and_b32_e32 v25, 0xffff0000, v96627; GFX950-NEXT: v_and_b32_e32 v26, 0xffff0000, v86628; GFX950-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc6629; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v186630; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v176631; GFX950-NEXT: v_and_b32_e32 v17, 0xffff0000, v66632; GFX950-NEXT: s_mov_b32 s0, 0x50401006633; GFX950-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc6634; GFX950-NEXT: v_lshrrev_b32_e32 v18, 16, v146635; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v176636; GFX950-NEXT: s_nop 16637; GFX950-NEXT: v_cndmask_b32_e32 v17, v19, v18, vcc6638; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v20, v206639; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v176640; GFX950-NEXT: s_nop 06641; GFX950-NEXT: v_cndmask_b32_e32 v18, v18, v17, vcc6642; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v186643; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v19, v206644; GFX950-NEXT: v_lshrrev_b32_e32 v20, 16, v56645; GFX950-NEXT: s_nop 06646; GFX950-NEXT: v_cndmask_b32_e32 v19, v18, v17, vcc6647; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v176648; GFX950-NEXT: s_nop 16649; GFX950-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc6650; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v186651; GFX950-NEXT: s_nop 16652; GFX950-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc6653; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v196654; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v186655; GFX950-NEXT: v_and_b32_e32 v18, 0xffff0000, v56656; GFX950-NEXT: s_nop 06657; GFX950-NEXT: v_cndmask_b32_e32 v17, v19, v17, vcc6658; GFX950-NEXT: v_lshrrev_b32_e32 v19, 16, v136659; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v18, v186660; GFX950-NEXT: s_nop 16661; GFX950-NEXT: v_cndmask_b32_e32 v18, v20, v19, vcc6662; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v21, v216663; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v186664; GFX950-NEXT: s_nop 06665; GFX950-NEXT: v_cndmask_b32_e32 v19, v19, v18, vcc6666; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v196667; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v20, v216668; GFX950-NEXT: v_lshrrev_b32_e32 v21, 16, v46669; GFX950-NEXT: s_nop 06670; GFX950-NEXT: v_cndmask_b32_e32 v20, v19, v18, vcc6671; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v186672; GFX950-NEXT: s_nop 16673; GFX950-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc6674; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v196675; GFX950-NEXT: s_nop 16676; GFX950-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc6677; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v206678; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v196679; GFX950-NEXT: v_and_b32_e32 v19, 0xffff0000, v46680; GFX950-NEXT: s_nop 06681; GFX950-NEXT: v_cndmask_b32_e32 v18, v20, v18, vcc6682; GFX950-NEXT: v_lshrrev_b32_e32 v20, 16, v126683; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v196684; GFX950-NEXT: s_nop 16685; GFX950-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc6686; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v22, v226687; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v196688; GFX950-NEXT: s_nop 06689; GFX950-NEXT: v_cndmask_b32_e32 v20, v20, v19, vcc6690; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v206691; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v21, v226692; GFX950-NEXT: v_lshrrev_b32_e32 v22, 16, v36693; GFX950-NEXT: s_nop 06694; GFX950-NEXT: v_cndmask_b32_e32 v21, v20, v19, vcc6695; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v196696; GFX950-NEXT: s_nop 16697; GFX950-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc6698; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v206699; GFX950-NEXT: s_nop 16700; GFX950-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc6701; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v216702; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v206703; GFX950-NEXT: v_and_b32_e32 v20, 0xffff0000, v36704; GFX950-NEXT: s_nop 06705; GFX950-NEXT: v_cndmask_b32_e32 v19, v21, v19, vcc6706; GFX950-NEXT: v_lshrrev_b32_e32 v21, 16, v116707; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v20, v206708; GFX950-NEXT: s_nop 16709; GFX950-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc6710; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v23, v236711; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v206712; GFX950-NEXT: s_nop 06713; GFX950-NEXT: v_cndmask_b32_e32 v21, v21, v20, vcc6714; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v216715; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v22, v236716; GFX950-NEXT: v_lshrrev_b32_e32 v23, 16, v26717; GFX950-NEXT: s_nop 06718; GFX950-NEXT: v_cndmask_b32_e32 v22, v21, v20, vcc6719; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v206720; GFX950-NEXT: s_nop 16721; GFX950-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc6722; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v216723; GFX950-NEXT: s_nop 16724; GFX950-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc6725; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v226726; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v216727; GFX950-NEXT: v_and_b32_e32 v21, 0xffff0000, v26728; GFX950-NEXT: s_nop 06729; GFX950-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc6730; GFX950-NEXT: v_lshrrev_b32_e32 v22, 16, v106731; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v21, v216732; GFX950-NEXT: s_nop 16733; GFX950-NEXT: v_cndmask_b32_e32 v21, v23, v22, vcc6734; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v246735; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v216736; GFX950-NEXT: s_nop 06737; GFX950-NEXT: v_cndmask_b32_e32 v22, v22, v21, vcc6738; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v226739; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v23, v246740; GFX950-NEXT: v_lshrrev_b32_e32 v24, 16, v16741; GFX950-NEXT: s_nop 06742; GFX950-NEXT: v_cndmask_b32_e32 v23, v22, v21, vcc6743; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v216744; GFX950-NEXT: s_nop 16745; GFX950-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc6746; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v226747; GFX950-NEXT: s_nop 16748; GFX950-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc6749; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v236750; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v226751; GFX950-NEXT: v_and_b32_e32 v22, 0xffff0000, v16752; GFX950-NEXT: s_nop 06753; GFX950-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc6754; GFX950-NEXT: v_lshrrev_b32_e32 v23, 16, v96755; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v22, v226756; GFX950-NEXT: s_nop 16757; GFX950-NEXT: v_cndmask_b32_e32 v22, v24, v23, vcc6758; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v25, v256759; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v226760; GFX950-NEXT: s_nop 06761; GFX950-NEXT: v_cndmask_b32_e32 v23, v23, v22, vcc6762; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v236763; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v24, v256764; GFX950-NEXT: v_lshrrev_b32_e32 v25, 16, v06765; GFX950-NEXT: s_nop 06766; GFX950-NEXT: v_cndmask_b32_e32 v24, v23, v22, vcc6767; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v226768; GFX950-NEXT: s_nop 16769; GFX950-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc6770; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v236771; GFX950-NEXT: s_nop 16772; GFX950-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc6773; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v246774; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v236775; GFX950-NEXT: v_and_b32_e32 v23, 0xffff0000, v06776; GFX950-NEXT: s_nop 06777; GFX950-NEXT: v_cndmask_b32_e32 v22, v24, v22, vcc6778; GFX950-NEXT: v_lshrrev_b32_e32 v24, 16, v86779; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v23, v236780; GFX950-NEXT: s_nop 16781; GFX950-NEXT: v_cndmask_b32_e32 v23, v25, v24, vcc6782; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v26, v266783; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v236784; GFX950-NEXT: s_nop 06785; GFX950-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc6786; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v246787; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v25, v266788; GFX950-NEXT: s_nop 16789; GFX950-NEXT: v_cndmask_b32_e32 v25, v24, v23, vcc6790; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v236791; GFX950-NEXT: s_nop 16792; GFX950-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc6793; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v246794; GFX950-NEXT: s_nop 16795; GFX950-NEXT: v_cndmask_b32_e32 v23, v23, v24, vcc6796; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v256797; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v246798; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v76799; GFX950-NEXT: s_nop 06800; GFX950-NEXT: v_cndmask_b32_e32 v23, v25, v23, vcc6801; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v246802; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v156803; GFX950-NEXT: s_nop 06804; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc6805; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v246806; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v76807; GFX950-NEXT: s_nop 06808; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc6809; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v156810; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v25, v246811; GFX950-NEXT: s_nop 16812; GFX950-NEXT: v_cndmask_b32_e32 v24, v15, v7, vcc6813; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v76814; GFX950-NEXT: s_nop 16815; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc6816; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v156817; GFX950-NEXT: s_nop 16818; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc6819; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v246820; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v156821; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v66822; GFX950-NEXT: s_nop 06823; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc6824; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v15, v156825; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v146826; GFX950-NEXT: v_perm_b32 v7, v16, v7, s06827; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc6828; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v15, v156829; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v66830; GFX950-NEXT: s_nop 06831; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc6832; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v146833; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v24, v156834; GFX950-NEXT: s_nop 16835; GFX950-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc6836; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v66837; GFX950-NEXT: s_nop 16838; GFX950-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc6839; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v146840; GFX950-NEXT: s_nop 16841; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc6842; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v156843; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v146844; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v56845; GFX950-NEXT: s_nop 06846; GFX950-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc6847; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v14, v146848; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v136849; GFX950-NEXT: v_perm_b32 v6, v17, v6, s06850; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc6851; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v14, v146852; GFX950-NEXT: v_lshlrev_b32_e32 v15, 16, v56853; GFX950-NEXT: s_nop 06854; GFX950-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc6855; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v136856; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v15, v146857; GFX950-NEXT: s_nop 16858; GFX950-NEXT: v_cndmask_b32_e32 v14, v13, v5, vcc6859; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v56860; GFX950-NEXT: s_nop 16861; GFX950-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6862; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v136863; GFX950-NEXT: s_nop 16864; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc6865; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v146866; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v136867; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v46868; GFX950-NEXT: s_nop 06869; GFX950-NEXT: v_cndmask_b32_e32 v5, v14, v5, vcc6870; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v13, v136871; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v126872; GFX950-NEXT: v_perm_b32 v5, v18, v5, s06873; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc6874; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v13, v136875; GFX950-NEXT: v_lshlrev_b32_e32 v14, 16, v46876; GFX950-NEXT: s_nop 06877; GFX950-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc6878; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v126879; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v14, v136880; GFX950-NEXT: s_nop 16881; GFX950-NEXT: v_cndmask_b32_e32 v13, v12, v4, vcc6882; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v46883; GFX950-NEXT: s_nop 16884; GFX950-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc6885; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v126886; GFX950-NEXT: s_nop 16887; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc6888; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v136889; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v126890; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v36891; GFX950-NEXT: s_nop 06892; GFX950-NEXT: v_cndmask_b32_e32 v4, v13, v4, vcc6893; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v126894; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v116895; GFX950-NEXT: v_perm_b32 v4, v19, v4, s06896; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc6897; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v12, v126898; GFX950-NEXT: v_lshlrev_b32_e32 v13, 16, v36899; GFX950-NEXT: s_nop 06900; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc6901; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v116902; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v13, v126903; GFX950-NEXT: s_nop 16904; GFX950-NEXT: v_cndmask_b32_e32 v12, v11, v3, vcc6905; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v36906; GFX950-NEXT: s_nop 16907; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc6908; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v116909; GFX950-NEXT: s_nop 16910; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc6911; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v126912; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v116913; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v26914; GFX950-NEXT: s_nop 06915; GFX950-NEXT: v_cndmask_b32_e32 v3, v12, v3, vcc6916; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v116917; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v106918; GFX950-NEXT: v_perm_b32 v3, v20, v3, s06919; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc6920; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v11, v116921; GFX950-NEXT: v_lshlrev_b32_e32 v12, 16, v26922; GFX950-NEXT: s_nop 06923; GFX950-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc6924; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v106925; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v12, v116926; GFX950-NEXT: s_nop 16927; GFX950-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc6928; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v26929; GFX950-NEXT: s_nop 16930; GFX950-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6931; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v106932; GFX950-NEXT: s_nop 16933; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc6934; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v116935; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v106936; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v16937; GFX950-NEXT: s_nop 06938; GFX950-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc6939; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v10, v106940; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v96941; GFX950-NEXT: v_perm_b32 v2, v21, v2, s06942; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc6943; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v10, v106944; GFX950-NEXT: v_lshlrev_b32_e32 v11, 16, v16945; GFX950-NEXT: s_nop 06946; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc6947; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v96948; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v11, v106949; GFX950-NEXT: s_nop 16950; GFX950-NEXT: v_cndmask_b32_e32 v10, v9, v1, vcc6951; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v16952; GFX950-NEXT: s_nop 16953; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc6954; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v96955; GFX950-NEXT: s_nop 16956; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc6957; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v106958; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v96959; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v06960; GFX950-NEXT: s_nop 06961; GFX950-NEXT: v_cndmask_b32_e32 v1, v10, v1, vcc6962; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v96963; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v86964; GFX950-NEXT: v_perm_b32 v1, v22, v1, s06965; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc6966; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v9, v96967; GFX950-NEXT: v_lshlrev_b32_e32 v10, 16, v06968; GFX950-NEXT: s_nop 06969; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc6970; GFX950-NEXT: v_lshlrev_b32_e32 v9, 16, v86971; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v10, v96972; GFX950-NEXT: s_nop 16973; GFX950-NEXT: v_cndmask_b32_e32 v9, v8, v0, vcc6974; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v06975; GFX950-NEXT: s_nop 16976; GFX950-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc6977; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v86978; GFX950-NEXT: s_nop 16979; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc6980; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v96981; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v86982; GFX950-NEXT: s_nop 16983; GFX950-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc6984; GFX950-NEXT: v_perm_b32 v0, v23, v0, s06985; GFX950-NEXT: s_setpc_b64 s[30:31]6986;6987; GFX10-LABEL: v_maximumnum_v16bf16:6988; GFX10: ; %bb.0:6989; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6990; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v76991; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v156992; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v76993; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v156994; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v66995; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v166996; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v146997; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v66998; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v136999; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v127000; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo7001; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v197002; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v47003; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v127004; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v17005; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v167006; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo7007; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v177008; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v197009; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v147010; GFX10-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo7011; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v207012; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo7013; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v167014; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo7015; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v197016; GFX10-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo7017; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v177018; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v207019; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v197020; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo7021; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v187022; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v177023; GFX10-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo7024; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v227025; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v57026; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v137027; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v57028; GFX10-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo7029; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v207030; GFX10-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo7031; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v187032; GFX10-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo7033; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v47034; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237035; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v187036; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo7037; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v227038; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v24, vcc_lo7039; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v197040; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v217041; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo7042; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v267043; GFX10-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo7044; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v257045; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v177046; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v227047; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v207048; GFX10-NEXT: v_cndmask_b32_e32 v23, v21, v18, vcc_lo7049; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v187050; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo7051; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v247052; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v37053; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo7054; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v267055; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v117056; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v37057; GFX10-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo7058; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v217059; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v197060; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo7061; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v237062; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v227063; GFX10-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo7064; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v217065; GFX10-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo7066; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v207067; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v27068; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v20, vcc_lo7069; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247070; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v117071; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v107072; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v25, vcc_lo7073; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v227074; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v27075; GFX10-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo7076; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237077; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v107078; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo7079; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v277080; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v227081; GFX10-NEXT: v_lshrrev_b32_e32 v27, 16, v97082; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo7083; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v217084; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v257085; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v17086; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v23, vcc_lo7087; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v267088; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v237089; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v247090; GFX10-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo7091; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v257092; GFX10-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo7093; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v217094; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v97095; GFX10-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo7096; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v297097; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v207098; GFX10-NEXT: v_cndmask_b32_e32 v26, v24, v23, vcc_lo7099; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v287100; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo7101; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v227102; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v277103; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc_lo7104; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v237105; GFX10-NEXT: v_cndmask_b32_e32 v22, v26, v23, vcc_lo7106; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v257107; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v247108; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo7109; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v287110; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v267111; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v157112; GFX10-NEXT: v_cndmask_b32_e32 v23, v27, v25, vcc_lo7113; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v297114; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo7115; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v247116; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v07117; GFX10-NEXT: v_cndmask_b32_e32 v21, v26, v22, vcc_lo7118; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v257119; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v07120; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo7121; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v277122; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v87123; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo7124; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v77125; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247126; GFX10-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo7127; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v87128; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v277129; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v237130; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo7131; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v267132; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v247133; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v77134; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo7135; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v287136; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v7, vcc_lo7137; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v277138; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v257139; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v157140; GFX10-NEXT: v_cndmask_b32_e32 v22, v23, v22, vcc_lo7141; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v67142; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237143; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v147144; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo7145; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v277146; GFX10-NEXT: v_cndmask_b32_e32 v26, v25, v24, vcc_lo7147; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v287148; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v67149; GFX10-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo7150; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237151; GFX10-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo7152; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v247153; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo7154; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v77155; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v147156; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo7157; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v257158; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo7159; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v157160; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v267161; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo7162; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v247163; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v277164; GFX10-NEXT: v_cndmask_b32_e32 v15, v14, v6, vcc_lo7165; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v257166; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v137167; GFX10-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo7168; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67169; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo7170; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v247171; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v57172; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo7173; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v147174; GFX10-NEXT: v_perm_b32 v7, v16, v7, 0x50401007175; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo7176; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v157177; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247178; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v47179; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo7180; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147181; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v127182; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo7183; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v257184; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v37185; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v57186; GFX10-NEXT: v_perm_b32 v6, v17, v6, 0x50401007187; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v5, vcc_lo7188; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247189; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v137190; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo7191; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v147192; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v117193; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo7194; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v157195; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo7196; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v247197; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v127198; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v47199; GFX10-NEXT: v_cndmask_b32_e32 v15, v13, v5, vcc_lo7200; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v147201; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo7202; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v57203; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo7204; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v247205; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v117206; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v37207; GFX10-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo7208; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v137209; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo7210; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v47211; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v157212; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo7213; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v247214; GFX10-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo7215; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v137216; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v147217; GFX10-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo7218; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v127219; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v247220; GFX10-NEXT: v_perm_b32 v5, v18, v5, 0x50401007221; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo7222; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v37223; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v27224; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo7225; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v117226; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo7227; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v127228; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v107229; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v17230; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo7231; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v157232; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v07233; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo7234; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v117235; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v97236; GFX10-NEXT: v_perm_b32 v3, v20, v3, 0x50401007237; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo7238; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v127239; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v87240; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo7241; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v157242; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v27243; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v17244; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo7245; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v117246; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v107247; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v07248; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v1, vcc_lo7249; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v127250; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v97251; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo7252; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v117253; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v87254; GFX10-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo7255; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v127256; GFX10-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo7257; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27258; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo7259; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v157260; GFX10-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo7261; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17262; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo7263; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v107264; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo7265; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v07266; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v157267; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo7268; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v97269; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo7270; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v127271; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v87272; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo7273; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v97274; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v117275; GFX10-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo7276; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v107277; GFX10-NEXT: v_perm_b32 v1, v22, v1, 0x50401007278; GFX10-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo7279; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v87280; GFX10-NEXT: v_perm_b32 v0, v23, v0, 0x50401007281; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo7282; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v137283; GFX10-NEXT: v_perm_b32 v2, v21, v2, 0x50401007284; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo7285; GFX10-NEXT: v_perm_b32 v4, v19, v4, 0x50401007286; GFX10-NEXT: s_setpc_b64 s[30:31]7287;7288; GFX11-TRUE16-LABEL: v_maximumnum_v16bf16:7289; GFX11-TRUE16: ; %bb.0:7290; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7291; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v77292; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v157293; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v67294; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v147295; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v137296; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v167297; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, 07298; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v127299; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v20, v207300; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v57301; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v7.h, v15.h, vcc_lo7302; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v177303; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l7304; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v217305; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v16.l7306; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.h7307; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.h, v15.h, v16.h, vcc_lo7308; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v47309; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v227310; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v16.l7311; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v37312; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v177313; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v117314; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l7315; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v107316; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l7317; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.h, v16.h, vcc_lo7318; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v237319; GFX11-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v27320; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v247321; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v17322; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v17.l, v16.h, s07323; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l7324; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v187325; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v16.l7326; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v97327; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v07328; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v167329; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v6.h, v14.h, s07330; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v87331; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v29, v297332; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v16.l7333; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v157334; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v14.h, v16.h, s17335; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v16.h7336; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v31, v317337; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v77338; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v32, v327339; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v187340; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v147341; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7342; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.h, v16.h, s07343; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v32, v327344; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v137345; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7346; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v18.l, v16.h, s17347; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v18.l7348; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v20, v207349; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v32, v327350; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v127351; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)7352; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v167353; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v5.h, v13.h, s17354; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7355; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v32, v327356; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v117357; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.h, v13.h, v16.h, s27358; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v16.h7359; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7360; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v32, v327361; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v107362; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v257363; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v25.h7364; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7365; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v32, v327366; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v25.h, v16.h, s17367; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v97368; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)7369; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v20.l, v16.h, s27370; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l7371; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v217372; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v32, v327373; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v16.l7374; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)7375; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v167376; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v4.h, v12.h, s27377; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7378; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.h, v12.h, v16.h, s37379; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v16.h7380; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v267381; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7382; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v26.h, v16.h, s27383; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.h, v21.l, v16.h, s37384; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v21.l7385; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v227386; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7387; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v167388; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.h, v11.h, s37389; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7390; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v16.h, s47391; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v16.h7392; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v16, v277393; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7394; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v27.h, v16.h, s37395; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.h, v22.l, v16.h, s47396; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v22.l7397; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v237398; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7399; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v167400; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v2.h, v10.h, s47401; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7402; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.h, v10.h, v16.h, s57403; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v16.h7404; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v16, v287405; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7406; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v28.h, v16.h, s47407; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.h, v23.l, v16.h, s57408; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l7409; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v247410; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7411; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v167412; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v1.h, v9.h, s57413; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7414; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v9.h, v16.h, s67415; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v16.h7416; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v16, v297417; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7418; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v29.h, v16.h, s57419; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.h, v24.l, v16.h, s67420; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l7421; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v30, v307422; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l7423; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7424; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v167425; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v0.h, v8.h, s67426; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7427; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v8.h, v16.h, s77428; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v16.h7429; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v16, v307430; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)7431; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v30.h, v16.h, s67432; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v31, v317433; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v67434; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v15.h, v16.h, s77435; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v15.h7436; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)7437; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v15.l, s67438; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v16.l7439; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v167440; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)7441; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v7.h, s87442; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v7.h7443; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s7, v7, v167444; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7445; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v16.h, v7.h, s77446; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v16.h7447; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s87448; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v31, v317449; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v57450; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7451; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v6.h, v16.h, s77452; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v7.l7453; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v14.l, s87454; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v16.l7455; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7456; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v167457; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v14.l, v6.h, s97458; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v6.h7459; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7460; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v14.h, s77461; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s8, v6, v167462; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7463; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.h, v6.h, s87464; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v16.h7465; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s97466; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v31, v317467; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v47468; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7469; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v5.h, v16.h, s87470; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v6.l7471; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.l, v13.l, s97472; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v16.l7473; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7474; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v167475; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v13.l, v5.h, s107476; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v5.h7477; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7478; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v13.h, s87479; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s9, v5, v167480; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7481; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.h, s97482; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v16.h7483; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s107484; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v31, v317485; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v37486; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7487; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.h, v16.h, s97488; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v5.l7489; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v12.l, s107490; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v16.l7491; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7492; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v167493; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v12.l, v4.h, s117494; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v4.h7495; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7496; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v12.h, s97497; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s10, v4, v167498; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7499; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v16.h, v4.h, s107500; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v16.h7501; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s117502; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v31, v317503; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v27504; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7505; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v16.h, s107506; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v4.l7507; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.l, v11.l, s117508; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v16.l7509; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7510; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v167511; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v11.l, v3.h, s127512; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v3.h7513; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7514; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v11.h, s107515; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s11, v3, v167516; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7517; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.h, v3.h, s117518; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v16.h7519; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v3.h, s127520; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v31, v317521; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v17522; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7523; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v2.h, v16.h, s117524; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v3.l7525; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v10.l, s127526; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l7527; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7528; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v167529; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v10.l, v2.h, s137530; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v2.h7531; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7532; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v10.h, s117533; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s12, v2, v167534; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7535; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v16.h, v2.h, s127536; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v16.h7537; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v2.h, s137538; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v31, v317539; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v07540; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7541; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v16.h, s127542; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v2.l7543; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v9.l, s137544; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.l7545; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7546; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v167547; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v9.l, v1.h, s147548; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v317549; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v1.h7550; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v87551; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v9.h, s127552; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s13, v1, v167553; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v0.l, v8.l, s147554; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v16.h7555; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v317556; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)7557; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v1.h, s137558; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v17.h7559; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v1.h, s157560; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)7561; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.l, v17.h, s137562; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v18.h7563; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v20.h, v25.h, s177564; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v32.h7565; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.h, s167566; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v1.l7567; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v0.h, vcc_lo7568; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.h, v18.h, s137569; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26.h7570; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v20.l, v1.h, s17571; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v167572; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v8.l, v32.h, s147573; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v18.l, v0.h, s07574; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v21.h, v26.h, vcc_lo7575; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.h7576; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27.h7577; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v32, v167578; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s137579; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v21.l, v0.h, s27580; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v29.h7581; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v23.h, v28.h, s17582; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.h, v32.h, s07583; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.h7584; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v22.h, v27.h, vcc_lo7585; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v24.h, v29.h, s27586; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30.h7587; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.l, v32.h, s157588; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v23.l, v1.h, s47589; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v22.l, v0.h, s37590; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v8.h, s57591; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v25.l, v30.h, vcc_lo7592; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v16.h, s07593; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v8.l7594; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)7595; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.h, v0.h, s67596; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v167597; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)7598; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v8.h, vcc_lo7599; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]7600;7601; GFX11-FAKE16-LABEL: v_maximumnum_v16bf16:7602; GFX11-FAKE16: ; %bb.0:7603; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7604; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v147605; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v77606; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v157607; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v77608; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v67609; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v127610; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v167611; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v157612; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v47613; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v17614; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v67615; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo7616; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v197617; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v137618; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)7619; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v167620; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo7621; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v177622; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)7623; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v197624; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo7625; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v207626; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v147627; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v167628; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo7629; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)7630; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v197631; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo7632; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v177633; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v207634; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)7635; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v197636; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v187637; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v177638; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)7639; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo7640; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v227641; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v137642; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v57643; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v57644; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v207645; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)7646; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo7647; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v187648; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo7649; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237650; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v47651; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7652; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v187653; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo7654; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v227655; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v127656; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7657; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v217658; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v197659; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo7660; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v267661; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)7662; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo7663; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v257664; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v177665; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v227666; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v207667; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v187668; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)7669; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo7670; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v247671; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo7672; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v267673; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v117674; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v37675; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo7676; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v217677; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)7678; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v197679; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v237680; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v227681; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo7682; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v217683; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo7684; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v207685; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)7686; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v27687; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v37688; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247689; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v107690; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v117691; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v27692; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)7693; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v227694; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo7695; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237696; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v107697; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo7698; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v277699; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v97700; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo7701; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v257702; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v17703; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)7704; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v247705; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v217706; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v227707; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v267708; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo7709; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v257710; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo7711; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v237712; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v217713; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo7714; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)7715; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v297716; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v207717; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v97718; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v287719; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo7720; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v227721; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)7722; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v277723; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v237724; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v257725; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v247726; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo7727; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)7728; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v287729; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v267730; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v297731; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo7732; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v247733; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v07734; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v257735; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v07736; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo7737; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v277738; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v87739; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7740; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo7741; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v77742; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247743; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo7744; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)7745; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v277746; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v237747; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v87748; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v77749; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v157750; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7751; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v267752; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo7753; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v287754; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v247755; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v277756; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)7757; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v257758; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v67759; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237760; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo7761; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v157762; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v277763; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v147764; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7765; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v287766; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo7767; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v237768; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo7769; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v247770; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo7771; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v77772; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)7773; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v147774; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v257775; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo7776; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v157777; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v267778; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v67779; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)7780; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v247781; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v277782; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v257783; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v137784; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo7785; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v67786; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo7787; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v247788; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v57789; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v147790; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7791; GFX11-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x50401007792; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo7793; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247794; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v47795; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v157796; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)7797; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v147798; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo7799; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v257800; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v37801; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v57802; GFX11-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x50401007803; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v127804; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v247805; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7806; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v137807; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo7808; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v147809; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)7810; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo7811; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v157812; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo7813; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v247814; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v127815; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v117816; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)7817; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v147818; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo7819; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v47820; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v57821; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo7822; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v247823; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v37824; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v117825; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo7826; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v137827; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo7828; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v47829; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)7830; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v14, v4 :: v_dual_lshlrev_b32 v13, 16, v157831; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v247832; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo7833; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v137834; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v147835; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo7836; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v127837; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)7838; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x50401007839; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo7840; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v37841; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo7842; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v117843; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v27844; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v107845; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)7846; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v127847; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v247848; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v157849; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo7850; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v117851; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v07852; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)7853; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x50401007854; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo7855; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17856; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v127857; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo7858; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v157859; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)7860; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v17861; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v97862; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v117863; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v87864; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v107865; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7866; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v127867; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v27868; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v97869; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)7870; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v117871; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo7872; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v127873; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo7874; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27875; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)7876; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v87877; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v07878; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v157879; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo7880; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v17881; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo7882; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v107883; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo7884; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v07885; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo7886; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v97887; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo7888; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v127889; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v87890; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo7891; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)7892; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v97893; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v157894; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v117895; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v107896; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7897; GFX11-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x50401007898; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo7899; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v87900; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)7901; GFX11-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x50401007902; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo7903; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v137904; GFX11-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x50401007905; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo7906; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)7907; GFX11-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x50401007908; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]7909;7910; GFX12-TRUE16-LABEL: v_maximumnum_v16bf16:7911; GFX12-TRUE16: ; %bb.0:7912; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x07913; GFX12-TRUE16-NEXT: s_wait_expcnt 0x07914; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x07915; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x07916; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x07917; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v77918; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v157919; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v67920; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v147921; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v137922; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v167923; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, 07924; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v127925; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v20, v207926; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v57927; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)7928; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v7.h, v15.h, vcc_lo7929; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v177930; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v16.l7931; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v217932; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v16.l7933; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.h7934; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)7935; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v15.h, v16.h, vcc_lo7936; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v47937; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v227938; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v16.l7939; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v37940; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v177941; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v117942; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v16.l7943; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v107944; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v16.l7945; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)7946; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.h, v16.h, vcc_lo7947; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v237948; GFX12-TRUE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v27949; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v247950; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v17951; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)7952; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v17.l, v16.h, s07953; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l7954; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v18, v187955; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v16.l7956; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v97957; GFX12-TRUE16-NEXT: v_and_b32_e32 v30, 0xffff0000, v07958; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v167959; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)7960; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v6.h, v14.h, s07961; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v87962; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v29, v297963; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v16.l7964; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v157965; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v14.h, v16.h, s17966; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v16.h7967; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v31, v317968; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v77969; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v32, v327970; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v187971; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v147972; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)7973; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7974; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.h, v16.h, s07975; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v32, v327976; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v137977; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7978; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v18.l, v16.h, s17979; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v18.l7980; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v20, v207981; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v32, v327982; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v127983; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)7984; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v167985; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)7986; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v5.h, v13.h, s17987; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v32, v327988; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v117989; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7990; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.h, v13.h, v16.h, s27991; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v16.h7992; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v32, v327993; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v107994; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)7995; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v257996; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v25.h7997; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v32, v327998; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)7999; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)8000; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v25.h, v16.h, s18001; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v98002; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v20.l, v16.h, s28003; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v20.l8004; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v21, v218005; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)8006; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v32, v328007; GFX12-TRUE16-NEXT: v_mov_b16_e32 v32.l, v16.l8008; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v168009; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8010; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v4.h, v12.h, s28011; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8012; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.h, v12.h, v16.h, s38013; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v16.h8014; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v268015; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8016; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8017; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v26.h, v16.h, s28018; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.h, v21.l, v16.h, s38019; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v21.l8020; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v228021; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8022; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v168023; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8024; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v3.h, v11.h, s38025; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8026; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v16.h, s48027; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v16.h8028; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v16, v278029; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8030; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8031; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v27.h, v16.h, s38032; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.h, v22.l, v16.h, s48033; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v22.l8034; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v23, v238035; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8036; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v168037; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8038; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v2.h, v10.h, s48039; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8040; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v10.h, v16.h, s58041; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v16.h8042; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v16, v288043; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8044; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8045; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v28.h, v16.h, s48046; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.h, v23.l, v16.h, s58047; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v23.l8048; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v24, v248049; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8050; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v168051; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8052; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v1.h, v9.h, s58053; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8054; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v9.h, v16.h, s68055; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v16.h8056; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v16, v298057; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8058; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8059; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v29.h, v16.h, s58060; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.h, v24.l, v16.h, s68061; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v24.l8062; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v30, v308063; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v16.l8064; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)8065; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v168066; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8067; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v0.h, v8.h, s68068; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8069; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v8.h, v16.h, s78070; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v16.h8071; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v16, v308072; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8073; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)8074; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v30.h, v16.h, s68075; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v31, v318076; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v68077; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v15.h, v16.h, s78078; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v15.h8079; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8080; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v15.l, s68081; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v16.l8082; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8083; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v168084; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v15.l, v7.h, s88085; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v7.h8086; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)8087; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s7, v7, v168088; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8089; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v16.h, v7.h, s78090; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v16.h8091; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)8092; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s88093; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v31, v318094; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v58095; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8096; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v6.h, v16.h, s78097; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v7.l8098; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v14.l, s88099; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v16.l8100; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8101; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v168102; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v14.l, v6.h, s98103; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v6.h8104; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8105; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8106; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v14.h, s78107; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s8, v6, v168108; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8109; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8110; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v16.h, v6.h, s88111; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v16.h8112; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s98113; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v31, v318114; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v48115; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8116; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)8117; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v5.h, v16.h, s88118; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v6.l8119; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.l, v13.l, s98120; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v16.l8121; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v168122; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8123; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v13.l, v5.h, s108124; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v5.h8125; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8126; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v13.h, s88127; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)8128; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s9, v5, v168129; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8130; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.h, v5.h, s98131; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v16.h8132; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)8133; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s108134; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v31, v318135; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v38136; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8137; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v4.h, v16.h, s98138; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v5.l8139; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v12.l, s108140; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v16.l8141; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8142; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v168143; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v12.l, v4.h, s118144; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v4.h8145; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8146; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8147; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v12.h, s98148; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s10, v4, v168149; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8150; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8151; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v16.h, v4.h, s108152; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v16.h8153; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s118154; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v31, v318155; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v28156; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8157; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)8158; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v3.h, v16.h, s108159; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v4.l8160; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v3.l, v11.l, s118161; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v16.l8162; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v168163; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8164; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v11.l, v3.h, s128165; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v3.h8166; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8167; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v11.h, s108168; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)8169; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s11, v3, v168170; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8171; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v16.h, v3.h, s118172; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v16.h8173; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)8174; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.l, v3.h, s128175; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v31, v318176; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v18177; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8178; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v2.h, v16.h, s118179; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v3.l8180; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v2.l, v10.l, s128181; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l8182; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8183; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v168184; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v10.l, v2.h, s138185; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v2.h8186; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8187; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8188; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v10.h, s118189; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s12, v2, v168190; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8191; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8192; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v16.h, v2.h, s128193; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v16.h8194; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, v2.h, s138195; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v31, v318196; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v08197; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8198; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)8199; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v1.h, v16.h, s128200; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v2.l8201; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v1.l, v9.l, s138202; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v16.l8203; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v168204; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)8205; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v9.l, v1.h, s148206; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v318207; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v1.h8208; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v88209; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8210; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v9.h, s128211; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s13, v1, v168212; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v0.l, v8.l, s148213; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v16.h8214; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v31, v318215; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8216; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v1.h, s138217; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v17.h8218; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8219; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v1.h, s158220; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8221; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.l, v17.h, s138222; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v18.h8223; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v20.h, v25.h, s178224; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v32.h8225; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.h, s168226; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v1.l8227; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)8228; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v17.l, v0.h, vcc_lo8229; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8230; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v19.h, v18.h, s138231; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v26.h8232; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v20.l, v1.h, s18233; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v168234; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v8.l, v32.h, s148235; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v18.l, v0.h, s08236; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)8237; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v21.h, v26.h, vcc_lo8238; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.h8239; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v27.h8240; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v32, v168241; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8242; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s138243; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v21.l, v0.h, s28244; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v29.h8245; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v23.h, v28.h, s18246; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.h, v32.h, s08247; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.h8248; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)8249; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v22.h, v27.h, vcc_lo8250; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)8251; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v24.h, v29.h, s28252; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v30.h8253; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v8.l, v32.h, s158254; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v23.l, v1.h, s48255; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v22.l, v0.h, s38256; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v24.l, v8.h, s58257; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)8258; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v25.l, v30.h, vcc_lo8259; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v16.h, s08260; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.h, v8.l8261; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)8262; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v15.h, v0.h, s68263; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v168264; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)8265; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v8.l, v8.h, vcc_lo8266; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]8267;8268; GFX12-FAKE16-LABEL: v_maximumnum_v16bf16:8269; GFX12-FAKE16: ; %bb.0:8270; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x08271; GFX12-FAKE16-NEXT: s_wait_expcnt 0x08272; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x08273; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x08274; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x08275; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v148276; GFX12-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v78277; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v158278; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v78279; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v68280; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v128281; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v168282; GFX12-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v158283; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v48284; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v18285; GFX12-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v68286; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8287; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v17, vcc_lo8288; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v198289; GFX12-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff0000, v138290; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)8291; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v168292; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8293; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v16, vcc_lo8294; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v178295; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)8296; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v198297; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8298; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v17, v16, vcc_lo8299; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v208300; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8301; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v148302; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v168303; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8304; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo8305; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)8306; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v198307; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8308; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v21, v20, vcc_lo8309; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v178310; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v208311; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v198312; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8313; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v188314; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8315; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v178316; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8317; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v16, vcc_lo8318; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v228319; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v138320; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v58321; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8322; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v58323; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v208324; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8325; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)8326; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v20, vcc_lo8327; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v188328; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8329; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v21, vcc_lo8330; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v238331; GFX12-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v48332; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8333; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v188334; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8335; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v18, vcc_lo8336; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v228337; GFX12-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v128338; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8339; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)8340; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v218341; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v198342; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8343; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v19, vcc_lo8344; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v268345; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8346; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v22, vcc_lo8347; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v258348; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v178349; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v228350; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8351; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v208352; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v188353; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8354; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)8355; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo8356; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v248357; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8358; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo8359; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v268360; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v118361; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v38362; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8363; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v20, v22, vcc_lo8364; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v218365; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8366; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)8367; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v198368; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v238369; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v228370; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8371; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v19, v22, vcc_lo8372; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v218373; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8374; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v23, v18, vcc_lo8375; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v208376; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8377; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v28378; GFX12-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v38379; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)8380; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v248381; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v108382; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8383; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v118384; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v28385; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v228386; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8387; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)8388; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v25, v21, vcc_lo8389; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v238390; GFX12-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v108391; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8392; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo8393; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v278394; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v98395; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8396; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo8397; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v258398; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8399; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v18400; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)8401; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v248402; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v218403; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v228404; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v268405; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8406; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v21, vcc_lo8407; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v258408; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8409; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v28, v27, vcc_lo8410; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v238411; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v218412; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8413; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v20, v21, vcc_lo8414; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)8415; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v298416; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8417; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v208418; GFX12-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v98419; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v288420; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8421; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v27, v25, vcc_lo8422; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v228423; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8424; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)8425; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v278426; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v238427; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8428; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v258429; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v248430; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8431; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)8432; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v24, vcc_lo8433; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v288434; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8435; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v268436; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v298437; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8438; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo8439; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)8440; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v248441; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8442; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v08443; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v258444; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v08445; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8446; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc_lo8447; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v278448; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v88449; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8450; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)8451; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v27, vcc_lo8452; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v78453; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v248454; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8455; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v26, v25, vcc_lo8456; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v278457; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v238458; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8459; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v88460; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)8461; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v78462; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v158463; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v268464; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8465; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v24, vcc_lo8466; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)8467; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v288468; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8469; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v248470; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v278471; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8472; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v258473; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v68474; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)8475; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v238476; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8477; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo8478; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v158479; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v278480; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8481; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v148482; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8483; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v288484; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8485; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v15, v7, vcc_lo8486; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v238487; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8488; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v6, vcc_lo8489; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v248490; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8491; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v24, vcc_lo8492; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v78493; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8494; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v148495; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v258496; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8497; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v25, vcc_lo8498; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v158499; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v268500; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8501; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v68502; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)8503; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v248504; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8505; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v278506; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v258507; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v138508; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8509; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v26, v23, vcc_lo8510; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v68511; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8512; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo8513; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v248514; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8515; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v58516; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v148517; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)8518; GFX12-FAKE16-NEXT: v_perm_b32 v7, v16, v7, 0x50401008519; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8520; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo8521; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v248522; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8523; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v48524; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v158525; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)8526; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v148527; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8528; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v15, v6, vcc_lo8529; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v258530; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v38531; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v58532; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)8533; GFX12-FAKE16-NEXT: v_perm_b32 v6, v17, v6, 0x50401008534; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8535; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v128536; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v248537; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v138538; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8539; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo8540; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v148541; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8542; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)8543; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v4, vcc_lo8544; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v158545; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8546; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo8547; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v248548; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8549; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v128550; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v118551; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)8552; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v148553; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8554; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v3, vcc_lo8555; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v48556; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v58557; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8558; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo8559; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)8560; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v248561; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v38562; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v118563; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8564; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v12, v4, vcc_lo8565; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v138566; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8567; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo8568; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48569; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8570; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v14, v4 :: v_dual_lshlrev_b32 v13, 16, v158571; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v248572; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8573; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v11, v3, vcc_lo8574; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)8575; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v138576; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v148577; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8578; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v15, v5, vcc_lo8579; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v128580; GFX12-FAKE16-NEXT: v_perm_b32 v5, v18, v5, 0x50401008581; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8582; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc_lo8583; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v38584; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8585; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo8586; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v118587; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8588; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8589; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v28590; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v108591; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v128592; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8593; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v248594; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)8595; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v158596; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8597; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo8598; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v118599; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v08600; GFX12-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0x50401008601; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8602; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v2, vcc_lo8603; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v18604; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)8605; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v128606; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8607; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo8608; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v158609; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v18610; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8611; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v98612; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)8613; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v118614; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8615; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v88616; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v108617; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v128618; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8619; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v28620; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v98621; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)8622; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v118623; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8624; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v10, v2, vcc_lo8625; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v128626; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8627; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v9, v1, vcc_lo8628; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v28629; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8630; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v88631; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v08632; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)8633; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v158634; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8635; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v8, v0, vcc_lo8636; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v18637; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8638; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v12, v1, vcc_lo8639; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v108640; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8641; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo8642; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v08643; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8644; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo8645; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v98646; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8647; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo8648; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v128649; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v88650; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8651; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo8652; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)8653; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v98654; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v158655; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8656; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v118657; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v108658; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)8659; GFX12-FAKE16-NEXT: v_perm_b32 v1, v22, v1, 0x50401008660; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8661; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v15, v0, vcc_lo8662; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v88663; GFX12-FAKE16-NEXT: v_perm_b32 v0, v23, v0, 0x50401008664; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8665; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v11, v2, vcc_lo8666; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v138667; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)8668; GFX12-FAKE16-NEXT: v_perm_b32 v2, v21, v2, 0x50401008669; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)8670; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v14, v4, vcc_lo8671; GFX12-FAKE16-NEXT: v_perm_b32 v4, v19, v4, 0x50401008672; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]8673 %result = call <16 x bfloat> @llvm.maximumnum.v16bf16(<16 x bfloat> %x, <16 x bfloat> %y)8674 ret <16 x bfloat> %result8675}8676 8677define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {8678; GFX7-LABEL: v_maximumnum_v32bf16:8679; GFX7: ; %bb.0:8680; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8681; GFX7-NEXT: buffer_load_dword v31, off, s[0:3], s328682; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1288683; GFX7-NEXT: v_mul_f32_e32 v30, 1.0, v308684; GFX7-NEXT: v_and_b32_e32 v30, 0xffff0000, v308685; GFX7-NEXT: v_mul_f32_e32 v29, 1.0, v298686; GFX7-NEXT: v_and_b32_e32 v29, 0xffff0000, v298687; GFX7-NEXT: v_mul_f32_e32 v28, 1.0, v288688; GFX7-NEXT: v_and_b32_e32 v28, 0xffff0000, v288689; GFX7-NEXT: v_mul_f32_e32 v27, 1.0, v278690; GFX7-NEXT: v_and_b32_e32 v27, 0xffff0000, v278691; GFX7-NEXT: v_mul_f32_e32 v26, 1.0, v268692; GFX7-NEXT: v_and_b32_e32 v26, 0xffff0000, v268693; GFX7-NEXT: v_mul_f32_e32 v25, 1.0, v258694; GFX7-NEXT: v_and_b32_e32 v25, 0xffff0000, v258695; GFX7-NEXT: v_mul_f32_e32 v24, 1.0, v248696; GFX7-NEXT: v_and_b32_e32 v24, 0xffff0000, v248697; GFX7-NEXT: v_mul_f32_e32 v23, 1.0, v238698; GFX7-NEXT: v_and_b32_e32 v23, 0xffff0000, v238699; GFX7-NEXT: v_mul_f32_e32 v22, 1.0, v228700; GFX7-NEXT: v_and_b32_e32 v22, 0xffff0000, v228701; GFX7-NEXT: v_mul_f32_e32 v21, 1.0, v218702; GFX7-NEXT: v_and_b32_e32 v21, 0xffff0000, v218703; GFX7-NEXT: v_mul_f32_e32 v20, 1.0, v208704; GFX7-NEXT: v_and_b32_e32 v20, 0xffff0000, v208705; GFX7-NEXT: v_mul_f32_e32 v19, 1.0, v198706; GFX7-NEXT: v_and_b32_e32 v19, 0xffff0000, v198707; GFX7-NEXT: v_mul_f32_e32 v18, 1.0, v188708; GFX7-NEXT: v_and_b32_e32 v18, 0xffff0000, v188709; GFX7-NEXT: v_mul_f32_e32 v17, 1.0, v178710; GFX7-NEXT: v_and_b32_e32 v17, 0xffff0000, v178711; GFX7-NEXT: v_mul_f32_e32 v16, 1.0, v168712; GFX7-NEXT: v_and_b32_e32 v16, 0xffff0000, v168713; GFX7-NEXT: v_mul_f32_e32 v15, 1.0, v158714; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v158715; GFX7-NEXT: v_mul_f32_e32 v14, 1.0, v148716; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v148717; GFX7-NEXT: v_mul_f32_e32 v13, 1.0, v138718; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v138719; GFX7-NEXT: v_mul_f32_e32 v12, 1.0, v128720; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v128721; GFX7-NEXT: v_mul_f32_e32 v11, 1.0, v118722; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v118723; GFX7-NEXT: v_mul_f32_e32 v10, 1.0, v108724; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v108725; GFX7-NEXT: v_mul_f32_e32 v9, 1.0, v98726; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v98727; GFX7-NEXT: v_mul_f32_e32 v8, 1.0, v88728; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v88729; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v78730; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v78731; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v68732; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v68733; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v58734; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v58735; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v48736; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v48737; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v38738; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v38739; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v28740; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v28741; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v18742; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v18743; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v08744; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v08745; GFX7-NEXT: s_waitcnt vmcnt(1)8746; GFX7-NEXT: v_mul_f32_e32 v31, 1.0, v318747; GFX7-NEXT: s_waitcnt vmcnt(0)8748; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328749; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328750; GFX7-NEXT: v_and_b32_e32 v31, 0xffff0000, v318751; GFX7-NEXT: v_max_f32_e32 v31, v31, v328752; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1248753; GFX7-NEXT: v_and_b32_e32 v31, 0xffff0000, v318754; GFX7-NEXT: s_waitcnt vmcnt(0)8755; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328756; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328757; GFX7-NEXT: v_max_f32_e32 v30, v30, v328758; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1208759; GFX7-NEXT: v_and_b32_e32 v30, 0xffff0000, v308760; GFX7-NEXT: s_waitcnt vmcnt(0)8761; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328762; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328763; GFX7-NEXT: v_max_f32_e32 v29, v29, v328764; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1168765; GFX7-NEXT: v_and_b32_e32 v29, 0xffff0000, v298766; GFX7-NEXT: s_waitcnt vmcnt(0)8767; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328768; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328769; GFX7-NEXT: v_max_f32_e32 v28, v28, v328770; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1128771; GFX7-NEXT: v_and_b32_e32 v28, 0xffff0000, v288772; GFX7-NEXT: s_waitcnt vmcnt(0)8773; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328774; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328775; GFX7-NEXT: v_max_f32_e32 v27, v27, v328776; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1088777; GFX7-NEXT: v_and_b32_e32 v27, 0xffff0000, v278778; GFX7-NEXT: s_waitcnt vmcnt(0)8779; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328780; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328781; GFX7-NEXT: v_max_f32_e32 v26, v26, v328782; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1048783; GFX7-NEXT: v_and_b32_e32 v26, 0xffff0000, v268784; GFX7-NEXT: s_waitcnt vmcnt(0)8785; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328786; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328787; GFX7-NEXT: v_max_f32_e32 v25, v25, v328788; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:1008789; GFX7-NEXT: v_and_b32_e32 v25, 0xffff0000, v258790; GFX7-NEXT: s_waitcnt vmcnt(0)8791; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328792; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328793; GFX7-NEXT: v_max_f32_e32 v24, v24, v328794; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:968795; GFX7-NEXT: v_and_b32_e32 v24, 0xffff0000, v248796; GFX7-NEXT: s_waitcnt vmcnt(0)8797; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328798; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328799; GFX7-NEXT: v_max_f32_e32 v23, v23, v328800; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:928801; GFX7-NEXT: v_and_b32_e32 v23, 0xffff0000, v238802; GFX7-NEXT: s_waitcnt vmcnt(0)8803; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328804; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328805; GFX7-NEXT: v_max_f32_e32 v22, v22, v328806; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:888807; GFX7-NEXT: v_and_b32_e32 v22, 0xffff0000, v228808; GFX7-NEXT: s_waitcnt vmcnt(0)8809; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328810; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328811; GFX7-NEXT: v_max_f32_e32 v21, v21, v328812; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:848813; GFX7-NEXT: v_and_b32_e32 v21, 0xffff0000, v218814; GFX7-NEXT: s_waitcnt vmcnt(0)8815; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328816; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328817; GFX7-NEXT: v_max_f32_e32 v20, v20, v328818; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:808819; GFX7-NEXT: v_and_b32_e32 v20, 0xffff0000, v208820; GFX7-NEXT: s_waitcnt vmcnt(0)8821; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328822; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328823; GFX7-NEXT: v_max_f32_e32 v19, v19, v328824; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:768825; GFX7-NEXT: v_and_b32_e32 v19, 0xffff0000, v198826; GFX7-NEXT: s_waitcnt vmcnt(0)8827; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328828; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328829; GFX7-NEXT: v_max_f32_e32 v18, v18, v328830; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:728831; GFX7-NEXT: v_and_b32_e32 v18, 0xffff0000, v188832; GFX7-NEXT: s_waitcnt vmcnt(0)8833; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328834; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328835; GFX7-NEXT: v_max_f32_e32 v17, v17, v328836; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:688837; GFX7-NEXT: v_and_b32_e32 v17, 0xffff0000, v178838; GFX7-NEXT: s_waitcnt vmcnt(0)8839; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328840; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328841; GFX7-NEXT: v_max_f32_e32 v16, v16, v328842; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:648843; GFX7-NEXT: v_and_b32_e32 v16, 0xffff0000, v168844; GFX7-NEXT: s_waitcnt vmcnt(0)8845; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328846; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328847; GFX7-NEXT: v_max_f32_e32 v15, v15, v328848; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:608849; GFX7-NEXT: v_and_b32_e32 v15, 0xffff0000, v158850; GFX7-NEXT: s_waitcnt vmcnt(0)8851; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328852; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328853; GFX7-NEXT: v_max_f32_e32 v14, v14, v328854; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:568855; GFX7-NEXT: v_and_b32_e32 v14, 0xffff0000, v148856; GFX7-NEXT: s_waitcnt vmcnt(0)8857; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328858; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328859; GFX7-NEXT: v_max_f32_e32 v13, v13, v328860; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:528861; GFX7-NEXT: v_and_b32_e32 v13, 0xffff0000, v138862; GFX7-NEXT: s_waitcnt vmcnt(0)8863; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328864; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328865; GFX7-NEXT: v_max_f32_e32 v12, v12, v328866; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:488867; GFX7-NEXT: v_and_b32_e32 v12, 0xffff0000, v128868; GFX7-NEXT: s_waitcnt vmcnt(0)8869; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328870; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328871; GFX7-NEXT: v_max_f32_e32 v11, v11, v328872; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:448873; GFX7-NEXT: v_and_b32_e32 v11, 0xffff0000, v118874; GFX7-NEXT: s_waitcnt vmcnt(0)8875; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328876; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328877; GFX7-NEXT: v_max_f32_e32 v10, v10, v328878; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408879; GFX7-NEXT: v_and_b32_e32 v10, 0xffff0000, v108880; GFX7-NEXT: s_waitcnt vmcnt(0)8881; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328882; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328883; GFX7-NEXT: v_max_f32_e32 v9, v9, v328884; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:368885; GFX7-NEXT: v_and_b32_e32 v9, 0xffff0000, v98886; GFX7-NEXT: s_waitcnt vmcnt(0)8887; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328888; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328889; GFX7-NEXT: v_max_f32_e32 v8, v8, v328890; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328891; GFX7-NEXT: v_and_b32_e32 v8, 0xffff0000, v88892; GFX7-NEXT: s_waitcnt vmcnt(0)8893; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328894; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328895; GFX7-NEXT: v_max_f32_e32 v7, v7, v328896; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:288897; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v78898; GFX7-NEXT: s_waitcnt vmcnt(0)8899; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328900; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328901; GFX7-NEXT: v_max_f32_e32 v6, v6, v328902; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:248903; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v68904; GFX7-NEXT: s_waitcnt vmcnt(0)8905; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328906; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328907; GFX7-NEXT: v_max_f32_e32 v5, v5, v328908; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:208909; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v58910; GFX7-NEXT: s_waitcnt vmcnt(0)8911; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328912; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328913; GFX7-NEXT: v_max_f32_e32 v4, v4, v328914; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:168915; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v48916; GFX7-NEXT: s_waitcnt vmcnt(0)8917; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328918; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328919; GFX7-NEXT: v_max_f32_e32 v3, v3, v328920; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128921; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v38922; GFX7-NEXT: s_waitcnt vmcnt(0)8923; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328924; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328925; GFX7-NEXT: v_max_f32_e32 v2, v2, v328926; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:88927; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v28928; GFX7-NEXT: s_waitcnt vmcnt(0)8929; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328930; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328931; GFX7-NEXT: v_max_f32_e32 v1, v1, v328932; GFX7-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:48933; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v18934; GFX7-NEXT: s_waitcnt vmcnt(0)8935; GFX7-NEXT: v_mul_f32_e32 v32, 1.0, v328936; GFX7-NEXT: v_and_b32_e32 v32, 0xffff0000, v328937; GFX7-NEXT: v_max_f32_e32 v0, v0, v328938; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v08939; GFX7-NEXT: s_setpc_b64 s[30:31]8940;8941; GFX8-LABEL: v_maximumnum_v32bf16:8942; GFX8: ; %bb.0:8943; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8944; GFX8-NEXT: buffer_load_dword v55, off, s[0:3], s328945; GFX8-NEXT: v_and_b32_e32 v31, 0xffff0000, v148946; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v308947; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v148948; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v138949; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v31, v318950; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v308951; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v298952; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v138953; GFX8-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc8954; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v378955; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v298956; GFX8-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc8957; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v368958; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc8959; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v488960; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v318961; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc8962; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v348963; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v358964; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v388965; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v37, v398966; GFX8-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc8967; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v36, v488968; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc8969; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v318970; GFX8-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc8971; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v358972; GFX8-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc8973; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v348974; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v378975; GFX8-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc8976; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v388977; GFX8-NEXT: v_and_b32_e32 v32, 0xffff0000, v158978; GFX8-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc8979; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v398980; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v158981; GFX8-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc8982; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v32, v328983; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v368984; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v278985; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v268986; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v248987; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v238988; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v228989; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v218990; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v208991; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v198992; GFX8-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill8993; GFX8-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill8994; GFX8-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill8995; GFX8-NEXT: v_and_b32_e32 v40, 0xffff0000, v188996; GFX8-NEXT: v_and_b32_e32 v41, 0xffff0000, v178997; GFX8-NEXT: v_and_b32_e32 v42, 0xffff0000, v168998; GFX8-NEXT: s_waitcnt vmcnt(3)8999; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v559000; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v559001; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc9002; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v379003; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc9004; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v329005; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v359006; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v33, v379007; GFX8-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc9008; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v329009; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc9010; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v339011; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359012; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc9013; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v379014; GFX8-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc9015; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v489016; GFX8-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc9017; GFX8-NEXT: v_and_b32_e32 v34, 0xffff0000, v129018; GFX8-NEXT: v_lshrrev_b32_e32 v35, 16, v289019; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v129020; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v34, v349021; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v289022; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v35, vcc9023; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v379024; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v34, vcc9025; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v349026; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v359027; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v36, v379028; GFX8-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc9029; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v349030; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc9031; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359032; GFX8-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc9033; GFX8-NEXT: v_lshlrev_b32_e32 v35, 16, v369034; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v359035; GFX8-NEXT: v_and_b32_e32 v35, 0xffff0000, v119036; GFX8-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc9037; GFX8-NEXT: v_lshrrev_b32_e32 v36, 16, v279038; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v119039; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v35, v359040; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc9041; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v389042; GFX8-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc9043; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v359044; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v369045; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v37, v389046; GFX8-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc9047; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359048; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc9049; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v369050; GFX8-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc9051; GFX8-NEXT: v_lshlrev_b32_e32 v36, 16, v379052; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v369053; GFX8-NEXT: v_and_b32_e32 v36, 0xffff0000, v109054; GFX8-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc9055; GFX8-NEXT: v_lshrrev_b32_e32 v37, 16, v269056; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v109057; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v36, v369058; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc9059; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v399060; GFX8-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc9061; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v369062; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v379063; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v38, v399064; GFX8-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc9065; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v369066; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc9067; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v379068; GFX8-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc9069; GFX8-NEXT: v_lshlrev_b32_e32 v37, 16, v389070; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v379071; GFX8-NEXT: v_and_b32_e32 v37, 0xffff0000, v99072; GFX8-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc9073; GFX8-NEXT: v_lshrrev_b32_e32 v38, 16, v259074; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v99075; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v37, v379076; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v259077; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v38, vcc9078; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v489079; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v37, vcc9080; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v379081; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v389082; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v39, v489083; GFX8-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc9084; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v379085; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc9086; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v389087; GFX8-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc9088; GFX8-NEXT: v_lshlrev_b32_e32 v38, 16, v399089; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v389090; GFX8-NEXT: v_and_b32_e32 v38, 0xffff0000, v89091; GFX8-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc9092; GFX8-NEXT: v_lshrrev_b32_e32 v39, 16, v249093; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v89094; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v38, v389095; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc9096; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v499097; GFX8-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc9098; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v389099; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v399100; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v48, v499101; GFX8-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc9102; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v389103; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc9104; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v399105; GFX8-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc9106; GFX8-NEXT: v_lshlrev_b32_e32 v39, 16, v489107; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v399108; GFX8-NEXT: v_and_b32_e32 v39, 0xffff0000, v79109; GFX8-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc9110; GFX8-NEXT: v_lshrrev_b32_e32 v48, 16, v239111; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v79112; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v39, v399113; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc9114; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v509115; GFX8-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc9116; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v399117; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v489118; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v49, v509119; GFX8-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc9120; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v399121; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc9122; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v489123; GFX8-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc9124; GFX8-NEXT: v_lshlrev_b32_e32 v48, 16, v499125; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v489126; GFX8-NEXT: v_and_b32_e32 v48, 0xffff0000, v69127; GFX8-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc9128; GFX8-NEXT: v_lshrrev_b32_e32 v49, 16, v229129; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v69130; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v48, v489131; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc9132; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v519133; GFX8-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc9134; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v489135; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v499136; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v50, v519137; GFX8-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc9138; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v489139; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc9140; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v499141; GFX8-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc9142; GFX8-NEXT: v_lshlrev_b32_e32 v49, 16, v509143; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v499144; GFX8-NEXT: v_and_b32_e32 v49, 0xffff0000, v59145; GFX8-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc9146; GFX8-NEXT: v_lshrrev_b32_e32 v50, 16, v219147; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v59148; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v49, v499149; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v50, vcc9150; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v529151; GFX8-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc9152; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v499153; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v509154; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v51, v529155; GFX8-NEXT: v_cndmask_b32_e32 v51, v50, v49, vcc9156; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v499157; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc9158; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v509159; GFX8-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc9160; GFX8-NEXT: v_lshlrev_b32_e32 v50, 16, v519161; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v509162; GFX8-NEXT: v_and_b32_e32 v50, 0xffff0000, v49163; GFX8-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc9164; GFX8-NEXT: v_lshrrev_b32_e32 v51, 16, v209165; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v49166; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v50, v509167; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v51, vcc9168; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v539169; GFX8-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc9170; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v509171; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v519172; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v52, v539173; GFX8-NEXT: v_cndmask_b32_e32 v52, v51, v50, vcc9174; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v509175; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc9176; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v519177; GFX8-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc9178; GFX8-NEXT: v_lshlrev_b32_e32 v51, 16, v529179; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v519180; GFX8-NEXT: v_and_b32_e32 v51, 0xffff0000, v39181; GFX8-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc9182; GFX8-NEXT: v_lshrrev_b32_e32 v52, 16, v199183; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v39184; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v51, v519185; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc9186; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v549187; GFX8-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc9188; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v519189; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v529190; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v53, v549191; GFX8-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc9192; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v519193; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc9194; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v529195; GFX8-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc9196; GFX8-NEXT: v_lshlrev_b32_e32 v52, 16, v539197; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v529198; GFX8-NEXT: v_and_b32_e32 v52, 0xffff0000, v29199; GFX8-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc9200; GFX8-NEXT: v_lshrrev_b32_e32 v53, 16, v189201; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v29202; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v52, v529203; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc9204; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v409205; GFX8-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc9206; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v529207; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v539208; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v54, v409209; GFX8-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc9210; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v529211; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc9212; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v539213; GFX8-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc9214; GFX8-NEXT: v_lshlrev_b32_e32 v53, 16, v549215; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v539216; GFX8-NEXT: v_and_b32_e32 v53, 0xffff0000, v19217; GFX8-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc9218; GFX8-NEXT: v_lshrrev_b32_e32 v54, 16, v179219; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v19220; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v53, v539221; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v54, vcc9222; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v41, v419223; GFX8-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc9224; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v539225; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v549226; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v40, v419227; GFX8-NEXT: v_cndmask_b32_e32 v40, v54, v53, vcc9228; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v539229; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc9230; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v549231; GFX8-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc9232; GFX8-NEXT: v_lshlrev_b32_e32 v54, 16, v409233; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v549234; GFX8-NEXT: v_and_b32_e32 v54, 0xffff0000, v09235; GFX8-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc9236; GFX8-NEXT: v_lshrrev_b32_e32 v40, 16, v169237; GFX8-NEXT: v_lshrrev_b32_e32 v41, 16, v09238; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v54, v549239; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v40, vcc9240; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v42, v429241; GFX8-NEXT: v_cndmask_b32_e32 v40, v40, v54, vcc9242; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v549243; GFX8-NEXT: v_lshlrev_b32_e32 v42, 16, v409244; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v41, v429245; GFX8-NEXT: v_cndmask_b32_e32 v41, v40, v54, vcc9246; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v549247; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc9248; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v409249; GFX8-NEXT: v_cndmask_b32_e32 v54, v54, v40, vcc9250; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v419251; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v409252; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v159253; GFX8-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc9254; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v409255; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v559256; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc9257; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v40, v409258; GFX8-NEXT: v_cndmask_b32_e32 v55, v55, v15, vcc9259; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v559260; GFX8-NEXT: v_lshlrev_b32_e32 v41, 16, v159261; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v41, v409262; GFX8-NEXT: v_cndmask_b32_e32 v40, v55, v15, vcc9263; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v159264; GFX8-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc9265; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v559266; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc9267; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v409268; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v559269; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v149270; GFX8-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc9271; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v55, v559272; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v309273; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc9274; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v55, v559275; GFX8-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc9276; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v309277; GFX8-NEXT: v_lshlrev_b32_e32 v40, 16, v149278; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v40, v559279; GFX8-NEXT: v_cndmask_b32_e32 v55, v30, v14, vcc9280; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v149281; GFX8-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc9282; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v309283; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc9284; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v559285; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v309286; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v139287; GFX8-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc9288; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v30, v309289; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v299290; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc9291; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v30, v309292; GFX8-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc9293; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v299294; GFX8-NEXT: v_lshlrev_b32_e32 v55, 16, v139295; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v55, v309296; GFX8-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc9297; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v139298; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc9299; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v299300; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc9301; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v309302; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v299303; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v129304; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc9305; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v29, v299306; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v289307; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc9308; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v29, v299309; GFX8-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc9310; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v289311; GFX8-NEXT: v_lshlrev_b32_e32 v30, 16, v129312; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v30, v299313; GFX8-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc9314; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v129315; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc9316; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v289317; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc9318; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v299319; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v289320; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v119321; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc9322; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v28, v289323; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v279324; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc9325; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v28, v289326; GFX8-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc9327; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v279328; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v119329; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v29, v289330; GFX8-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc9331; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v119332; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc9333; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v279334; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc9335; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v289336; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v279337; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v109338; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc9339; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v27, v279340; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v269341; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc9342; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v27, v279343; GFX8-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc9344; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v269345; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v109346; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v28, v279347; GFX8-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc9348; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v109349; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc9350; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v269351; GFX8-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc9352; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v279353; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v269354; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v99355; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc9356; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v269357; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v259358; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc9359; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v26, v269360; GFX8-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc9361; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v259362; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v99363; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v27, v269364; GFX8-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc9365; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v99366; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc9367; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v259368; GFX8-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc9369; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v269370; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v259371; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v89372; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc9373; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v259374; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v249375; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc9376; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v25, v259377; GFX8-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc9378; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v249379; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v89380; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v26, v259381; GFX8-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc9382; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v89383; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc9384; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v249385; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc9386; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v259387; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v249388; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v79389; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc9390; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v249391; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v239392; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc9393; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v24, v249394; GFX8-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc9395; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v239396; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v79397; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v25, v249398; GFX8-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc9399; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v79400; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc9401; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v239402; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc9403; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v249404; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v239405; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v69406; GFX8-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload9407; GFX8-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload9408; GFX8-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload9409; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc9410; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v239411; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v229412; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc9413; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v23, v239414; GFX8-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc9415; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v229416; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v69417; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v24, v239418; GFX8-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc9419; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v69420; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc9421; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v229422; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc9423; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v239424; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v229425; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v59426; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc9427; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v229428; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v219429; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc9430; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v22, v229431; GFX8-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc9432; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v219433; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v59434; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v23, v229435; GFX8-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc9436; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v59437; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc9438; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v219439; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc9440; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v229441; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v219442; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v49443; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc9444; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v219445; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v209446; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc9447; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v21, v219448; GFX8-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc9449; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v209450; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v49451; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v22, v219452; GFX8-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc9453; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v49454; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc9455; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v209456; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc9457; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v219458; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v209459; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v39460; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc9461; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v209462; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v199463; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc9464; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v20, v209465; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc9466; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v199467; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v39468; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v21, v209469; GFX8-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc9470; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v39471; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc9472; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v199473; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc9474; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v209475; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v199476; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v29477; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc9478; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v199479; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v189480; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc9481; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v19, v199482; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc9483; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v189484; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v29485; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v20, v199486; GFX8-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc9487; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v29488; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc9489; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v189490; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc9491; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v199492; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v189493; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v19494; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc9495; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v189496; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v179497; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc9498; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v18, v189499; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc9500; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v179501; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19502; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v19, v189503; GFX8-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc9504; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v19505; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc9506; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v179507; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc9508; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v189509; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v179510; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v09511; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc9512; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v179513; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v169514; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc9515; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v17, v179516; GFX8-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc9517; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v169518; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v09519; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v18, v179520; GFX8-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc9521; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v09522; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc9523; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v169524; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc9525; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v179526; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v169527; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc9528; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v549529; GFX8-NEXT: v_or_b32_sdwa v0, v0, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9530; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v539531; GFX8-NEXT: v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9532; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v529533; GFX8-NEXT: v_or_b32_sdwa v2, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9534; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v519535; GFX8-NEXT: v_or_b32_sdwa v3, v3, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9536; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v509537; GFX8-NEXT: v_or_b32_sdwa v4, v4, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9538; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v499539; GFX8-NEXT: v_or_b32_sdwa v5, v5, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9540; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v489541; GFX8-NEXT: v_or_b32_sdwa v6, v6, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9542; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v399543; GFX8-NEXT: v_or_b32_sdwa v7, v7, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9544; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v389545; GFX8-NEXT: v_or_b32_sdwa v8, v8, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9546; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v379547; GFX8-NEXT: v_or_b32_sdwa v9, v9, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9548; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v369549; GFX8-NEXT: v_or_b32_sdwa v10, v10, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9550; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v359551; GFX8-NEXT: v_or_b32_sdwa v11, v11, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9552; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v349553; GFX8-NEXT: v_or_b32_sdwa v12, v12, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9554; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v339555; GFX8-NEXT: v_or_b32_sdwa v13, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9556; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v319557; GFX8-NEXT: v_or_b32_sdwa v14, v14, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9558; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v329559; GFX8-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9560; GFX8-NEXT: s_waitcnt vmcnt(0)9561; GFX8-NEXT: s_setpc_b64 s[30:31]9562;9563; GFX900-LABEL: v_maximumnum_v32bf16:9564; GFX900: ; %bb.0:9565; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9566; GFX900-NEXT: buffer_load_dword v55, off, s[0:3], s329567; GFX900-NEXT: v_and_b32_e32 v31, 0xffff0000, v149568; GFX900-NEXT: v_lshrrev_b32_e32 v34, 16, v309569; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v149570; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v139571; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v31, v319572; GFX900-NEXT: v_and_b32_e32 v36, 0xffff0000, v309573; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v299574; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v139575; GFX900-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc9576; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v379577; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v299578; GFX900-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc9579; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v369580; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc9581; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v489582; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v319583; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc9584; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v349585; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v359586; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v389587; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v37, v399588; GFX900-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc9589; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v36, v489590; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc9591; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v319592; GFX900-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc9593; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359594; GFX900-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc9595; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v349596; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v379597; GFX900-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc9598; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v389599; GFX900-NEXT: v_and_b32_e32 v32, 0xffff0000, v159600; GFX900-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc9601; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v399602; GFX900-NEXT: v_lshrrev_b32_e32 v33, 16, v159603; GFX900-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc9604; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v32, v329605; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v369606; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v279607; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v269608; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v249609; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v239610; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v229611; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v219612; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v209613; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v199614; GFX900-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill9615; GFX900-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill9616; GFX900-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill9617; GFX900-NEXT: v_and_b32_e32 v40, 0xffff0000, v189618; GFX900-NEXT: v_and_b32_e32 v41, 0xffff0000, v179619; GFX900-NEXT: v_and_b32_e32 v42, 0xffff0000, v169620; GFX900-NEXT: s_mov_b32 s4, 0x50401009621; GFX900-NEXT: s_waitcnt vmcnt(3)9622; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v559623; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v559624; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc9625; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v379626; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc9627; GFX900-NEXT: v_lshlrev_b32_e32 v33, 16, v329628; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v359629; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v33, v379630; GFX900-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc9631; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v329632; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc9633; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v339634; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359635; GFX900-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc9636; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v379637; GFX900-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc9638; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v489639; GFX900-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc9640; GFX900-NEXT: v_and_b32_e32 v34, 0xffff0000, v129641; GFX900-NEXT: v_lshrrev_b32_e32 v35, 16, v289642; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v129643; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v34, v349644; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v289645; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v35, vcc9646; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v379647; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v34, vcc9648; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v349649; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v359650; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v36, v379651; GFX900-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc9652; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v349653; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc9654; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359655; GFX900-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc9656; GFX900-NEXT: v_lshlrev_b32_e32 v35, 16, v369657; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v359658; GFX900-NEXT: v_and_b32_e32 v35, 0xffff0000, v119659; GFX900-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc9660; GFX900-NEXT: v_lshrrev_b32_e32 v36, 16, v279661; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v119662; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v35, v359663; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc9664; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v389665; GFX900-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc9666; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v359667; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v369668; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v37, v389669; GFX900-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc9670; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v359671; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc9672; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v369673; GFX900-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc9674; GFX900-NEXT: v_lshlrev_b32_e32 v36, 16, v379675; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v369676; GFX900-NEXT: v_and_b32_e32 v36, 0xffff0000, v109677; GFX900-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc9678; GFX900-NEXT: v_lshrrev_b32_e32 v37, 16, v269679; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v109680; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v36, v369681; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc9682; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v399683; GFX900-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc9684; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v369685; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v379686; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v38, v399687; GFX900-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc9688; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v369689; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc9690; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v379691; GFX900-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc9692; GFX900-NEXT: v_lshlrev_b32_e32 v37, 16, v389693; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v379694; GFX900-NEXT: v_and_b32_e32 v37, 0xffff0000, v99695; GFX900-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc9696; GFX900-NEXT: v_lshrrev_b32_e32 v38, 16, v259697; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v99698; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v37, v379699; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v259700; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v38, vcc9701; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v489702; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v37, vcc9703; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v379704; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v389705; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v39, v489706; GFX900-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc9707; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v379708; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc9709; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v389710; GFX900-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc9711; GFX900-NEXT: v_lshlrev_b32_e32 v38, 16, v399712; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v389713; GFX900-NEXT: v_and_b32_e32 v38, 0xffff0000, v89714; GFX900-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc9715; GFX900-NEXT: v_lshrrev_b32_e32 v39, 16, v249716; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v89717; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v38, v389718; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc9719; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v499720; GFX900-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc9721; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v389722; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v399723; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v48, v499724; GFX900-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc9725; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v389726; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc9727; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v399728; GFX900-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc9729; GFX900-NEXT: v_lshlrev_b32_e32 v39, 16, v489730; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v399731; GFX900-NEXT: v_and_b32_e32 v39, 0xffff0000, v79732; GFX900-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc9733; GFX900-NEXT: v_lshrrev_b32_e32 v48, 16, v239734; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v79735; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v39, v399736; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc9737; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v509738; GFX900-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc9739; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v399740; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v489741; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v49, v509742; GFX900-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc9743; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v399744; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc9745; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v489746; GFX900-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc9747; GFX900-NEXT: v_lshlrev_b32_e32 v48, 16, v499748; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v489749; GFX900-NEXT: v_and_b32_e32 v48, 0xffff0000, v69750; GFX900-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc9751; GFX900-NEXT: v_lshrrev_b32_e32 v49, 16, v229752; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v69753; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v48, v489754; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v49, vcc9755; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v519756; GFX900-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc9757; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v489758; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v499759; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v50, v519760; GFX900-NEXT: v_cndmask_b32_e32 v50, v49, v48, vcc9761; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v489762; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc9763; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v499764; GFX900-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc9765; GFX900-NEXT: v_lshlrev_b32_e32 v49, 16, v509766; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v499767; GFX900-NEXT: v_and_b32_e32 v49, 0xffff0000, v59768; GFX900-NEXT: v_cndmask_b32_e32 v48, v50, v48, vcc9769; GFX900-NEXT: v_lshrrev_b32_e32 v50, 16, v219770; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v59771; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v49, v499772; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v50, vcc9773; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v529774; GFX900-NEXT: v_cndmask_b32_e32 v50, v50, v49, vcc9775; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v499776; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v509777; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v51, v529778; GFX900-NEXT: v_cndmask_b32_e32 v51, v50, v49, vcc9779; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v499780; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc9781; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v509782; GFX900-NEXT: v_cndmask_b32_e32 v49, v49, v50, vcc9783; GFX900-NEXT: v_lshlrev_b32_e32 v50, 16, v519784; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v509785; GFX900-NEXT: v_and_b32_e32 v50, 0xffff0000, v49786; GFX900-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc9787; GFX900-NEXT: v_lshrrev_b32_e32 v51, 16, v209788; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v49789; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v50, v509790; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v51, vcc9791; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v539792; GFX900-NEXT: v_cndmask_b32_e32 v51, v51, v50, vcc9793; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v509794; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v519795; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v52, v539796; GFX900-NEXT: v_cndmask_b32_e32 v52, v51, v50, vcc9797; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v509798; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc9799; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v519800; GFX900-NEXT: v_cndmask_b32_e32 v50, v50, v51, vcc9801; GFX900-NEXT: v_lshlrev_b32_e32 v51, 16, v529802; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v519803; GFX900-NEXT: v_and_b32_e32 v51, 0xffff0000, v39804; GFX900-NEXT: v_cndmask_b32_e32 v50, v52, v50, vcc9805; GFX900-NEXT: v_lshrrev_b32_e32 v52, 16, v199806; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v39807; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v51, v519808; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc9809; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v549810; GFX900-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc9811; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v519812; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v529813; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v53, v549814; GFX900-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc9815; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v519816; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc9817; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v529818; GFX900-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc9819; GFX900-NEXT: v_lshlrev_b32_e32 v52, 16, v539820; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v529821; GFX900-NEXT: v_and_b32_e32 v52, 0xffff0000, v29822; GFX900-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc9823; GFX900-NEXT: v_lshrrev_b32_e32 v53, 16, v189824; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v29825; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v52, v529826; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc9827; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v409828; GFX900-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc9829; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v529830; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v539831; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v54, v409832; GFX900-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc9833; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v529834; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc9835; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v539836; GFX900-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc9837; GFX900-NEXT: v_lshlrev_b32_e32 v53, 16, v549838; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v539839; GFX900-NEXT: v_and_b32_e32 v53, 0xffff0000, v19840; GFX900-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc9841; GFX900-NEXT: v_lshrrev_b32_e32 v54, 16, v179842; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v19843; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v53, v539844; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v54, vcc9845; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v41, v419846; GFX900-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc9847; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v539848; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v549849; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v40, v419850; GFX900-NEXT: v_cndmask_b32_e32 v40, v54, v53, vcc9851; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v539852; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc9853; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v549854; GFX900-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc9855; GFX900-NEXT: v_lshlrev_b32_e32 v54, 16, v409856; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v549857; GFX900-NEXT: v_and_b32_e32 v54, 0xffff0000, v09858; GFX900-NEXT: v_cndmask_b32_e32 v53, v40, v53, vcc9859; GFX900-NEXT: v_lshrrev_b32_e32 v40, 16, v169860; GFX900-NEXT: v_lshrrev_b32_e32 v41, 16, v09861; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v54, v549862; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v40, vcc9863; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v42, v429864; GFX900-NEXT: v_cndmask_b32_e32 v40, v40, v54, vcc9865; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v549866; GFX900-NEXT: v_lshlrev_b32_e32 v42, 16, v409867; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v41, v429868; GFX900-NEXT: v_cndmask_b32_e32 v41, v40, v54, vcc9869; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v549870; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc9871; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v409872; GFX900-NEXT: v_cndmask_b32_e32 v54, v54, v40, vcc9873; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v419874; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v409875; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v159876; GFX900-NEXT: v_cndmask_b32_e32 v54, v41, v54, vcc9877; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v409878; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v559879; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc9880; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v40, v409881; GFX900-NEXT: v_cndmask_b32_e32 v55, v55, v15, vcc9882; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v559883; GFX900-NEXT: v_lshlrev_b32_e32 v41, 16, v159884; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v41, v409885; GFX900-NEXT: v_cndmask_b32_e32 v40, v55, v15, vcc9886; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v159887; GFX900-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc9888; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v559889; GFX900-NEXT: v_cndmask_b32_e32 v15, v15, v55, vcc9890; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v409891; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v559892; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v149893; GFX900-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc9894; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v55, v559895; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v309896; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc9897; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v55, v559898; GFX900-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc9899; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v309900; GFX900-NEXT: v_lshlrev_b32_e32 v40, 16, v149901; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v40, v559902; GFX900-NEXT: v_cndmask_b32_e32 v55, v30, v14, vcc9903; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v149904; GFX900-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc9905; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v309906; GFX900-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc9907; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v559908; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v309909; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v139910; GFX900-NEXT: v_cndmask_b32_e32 v14, v55, v14, vcc9911; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v30, v309912; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v299913; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc9914; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v30, v309915; GFX900-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc9916; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v299917; GFX900-NEXT: v_lshlrev_b32_e32 v55, 16, v139918; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v55, v309919; GFX900-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc9920; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v139921; GFX900-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc9922; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v299923; GFX900-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc9924; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v309925; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v299926; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v129927; GFX900-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc9928; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v29, v299929; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v289930; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc9931; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v29, v299932; GFX900-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc9933; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v289934; GFX900-NEXT: v_lshlrev_b32_e32 v30, 16, v129935; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v30, v299936; GFX900-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc9937; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v129938; GFX900-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc9939; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v289940; GFX900-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc9941; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v299942; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v289943; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v119944; GFX900-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc9945; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v28, v289946; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v279947; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc9948; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v28, v289949; GFX900-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc9950; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v279951; GFX900-NEXT: v_lshlrev_b32_e32 v29, 16, v119952; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v29, v289953; GFX900-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc9954; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v119955; GFX900-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc9956; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v279957; GFX900-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc9958; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v289959; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v279960; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v109961; GFX900-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc9962; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v27, v279963; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v269964; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc9965; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v27, v279966; GFX900-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc9967; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v269968; GFX900-NEXT: v_lshlrev_b32_e32 v28, 16, v109969; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v28, v279970; GFX900-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc9971; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v109972; GFX900-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc9973; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v269974; GFX900-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc9975; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v279976; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v269977; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v99978; GFX900-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc9979; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v269980; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v259981; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc9982; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v26, v269983; GFX900-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc9984; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v259985; GFX900-NEXT: v_lshlrev_b32_e32 v27, 16, v99986; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v27, v269987; GFX900-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc9988; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v99989; GFX900-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc9990; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v259991; GFX900-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc9992; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v269993; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v259994; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v89995; GFX900-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc9996; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v259997; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v249998; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc9999; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v25, v2510000; GFX900-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc10001; GFX900-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload10002; GFX900-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload10003; GFX900-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload10004; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v2410005; GFX900-NEXT: v_lshlrev_b32_e32 v26, 16, v810006; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v26, v2510007; GFX900-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc10008; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v810009; GFX900-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc10010; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2410011; GFX900-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc10012; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v2510013; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2410014; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v710015; GFX900-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc10016; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v2410017; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v2310018; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc10019; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v24, v2410020; GFX900-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc10021; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v2310022; GFX900-NEXT: v_lshlrev_b32_e32 v25, 16, v710023; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v25, v2410024; GFX900-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc10025; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v710026; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc10027; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2310028; GFX900-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc10029; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v2410030; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2310031; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v610032; GFX900-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc10033; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v2310034; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v2210035; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc10036; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v23, v2310037; GFX900-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc10038; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v2210039; GFX900-NEXT: v_lshlrev_b32_e32 v24, 16, v610040; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v24, v2310041; GFX900-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc10042; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v610043; GFX900-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc10044; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2210045; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc10046; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v2310047; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2210048; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v510049; GFX900-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc10050; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v2210051; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v2110052; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc10053; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v22, v2210054; GFX900-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc10055; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v2110056; GFX900-NEXT: v_lshlrev_b32_e32 v23, 16, v510057; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v23, v2210058; GFX900-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc10059; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v510060; GFX900-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc10061; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2110062; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc10063; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v2210064; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2110065; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v410066; GFX900-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc10067; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v2110068; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v2010069; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc10070; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v21, v2110071; GFX900-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc10072; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v2010073; GFX900-NEXT: v_lshlrev_b32_e32 v22, 16, v410074; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v22, v2110075; GFX900-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc10076; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v410077; GFX900-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc10078; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2010079; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc10080; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v2110081; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2010082; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v310083; GFX900-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc10084; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v2010085; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v1910086; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc10087; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v20, v2010088; GFX900-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc10089; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v1910090; GFX900-NEXT: v_lshlrev_b32_e32 v21, 16, v310091; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v21, v2010092; GFX900-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc10093; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v310094; GFX900-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc10095; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1910096; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc10097; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v2010098; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1910099; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v210100; GFX900-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc10101; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v1910102; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v1810103; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc10104; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v19, v1910105; GFX900-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc10106; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v1810107; GFX900-NEXT: v_lshlrev_b32_e32 v20, 16, v210108; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v20, v1910109; GFX900-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc10110; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v210111; GFX900-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc10112; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1810113; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc10114; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v1910115; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1810116; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v110117; GFX900-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc10118; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v1810119; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v1710120; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc10121; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v18, v1810122; GFX900-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc10123; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v1710124; GFX900-NEXT: v_lshlrev_b32_e32 v19, 16, v110125; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v19, v1810126; GFX900-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc10127; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v110128; GFX900-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc10129; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1710130; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc10131; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v1810132; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1710133; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v010134; GFX900-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc10135; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v1710136; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v1610137; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc10138; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v17, v1710139; GFX900-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc10140; GFX900-NEXT: v_lshlrev_b32_e32 v17, 16, v1610141; GFX900-NEXT: v_lshlrev_b32_e32 v18, 16, v010142; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v18, v1710143; GFX900-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc10144; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v010145; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc10146; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1610147; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc10148; GFX900-NEXT: v_lshlrev_b32_e32 v16, 16, v1710149; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1610150; GFX900-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc10151; GFX900-NEXT: v_perm_b32 v0, v54, v0, s410152; GFX900-NEXT: v_perm_b32 v1, v53, v1, s410153; GFX900-NEXT: v_perm_b32 v2, v52, v2, s410154; GFX900-NEXT: v_perm_b32 v3, v51, v3, s410155; GFX900-NEXT: v_perm_b32 v4, v50, v4, s410156; GFX900-NEXT: v_perm_b32 v5, v49, v5, s410157; GFX900-NEXT: v_perm_b32 v6, v48, v6, s410158; GFX900-NEXT: v_perm_b32 v7, v39, v7, s410159; GFX900-NEXT: v_perm_b32 v8, v38, v8, s410160; GFX900-NEXT: v_perm_b32 v9, v37, v9, s410161; GFX900-NEXT: v_perm_b32 v10, v36, v10, s410162; GFX900-NEXT: v_perm_b32 v11, v35, v11, s410163; GFX900-NEXT: v_perm_b32 v12, v34, v12, s410164; GFX900-NEXT: v_perm_b32 v13, v33, v13, s410165; GFX900-NEXT: v_perm_b32 v14, v31, v14, s410166; GFX900-NEXT: v_perm_b32 v15, v32, v15, s410167; GFX900-NEXT: s_waitcnt vmcnt(0)10168; GFX900-NEXT: s_setpc_b64 s[30:31]10169;10170; GFX950-LABEL: v_maximumnum_v32bf16:10171; GFX950: ; %bb.0:10172; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10173; GFX950-NEXT: scratch_load_dword v50, off, s3210174; GFX950-NEXT: v_and_b32_e32 v31, 0xffff0000, v1410175; GFX950-NEXT: v_lshrrev_b32_e32 v34, 16, v3010176; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v1410177; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v1310178; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v31, v3110179; GFX950-NEXT: v_and_b32_e32 v36, 0xffff0000, v3010180; GFX950-NEXT: v_lshrrev_b32_e32 v38, 16, v2910181; GFX950-NEXT: v_lshrrev_b32_e32 v39, 16, v1310182; GFX950-NEXT: v_cndmask_b32_e32 v31, v35, v34, vcc10183; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v3710184; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v2910185; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v3110186; GFX950-NEXT: v_cndmask_b32_e32 v35, v39, v38, vcc10187; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v36, v3610188; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v3510189; GFX950-NEXT: v_and_b32_e32 v32, 0xffff0000, v1510190; GFX950-NEXT: v_cndmask_b32_e32 v34, v34, v31, vcc10191; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v48, v4810192; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v3410193; GFX950-NEXT: v_lshrrev_b32_e32 v33, 16, v1510194; GFX950-NEXT: v_cndmask_b32_e32 v38, v38, v35, vcc10195; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v3810196; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v37, v3910197; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v2410198; GFX950-NEXT: v_and_b32_e32 v51, 0xffff0000, v2310199; GFX950-NEXT: v_cndmask_b32_e32 v37, v34, v31, vcc10200; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v36, v4810201; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v3710202; GFX950-NEXT: v_and_b32_e32 v52, 0xffff0000, v2210203; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v35, vcc10204; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3110205; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v3610206; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v2110207; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc10208; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3510209; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v2010210; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v1910211; GFX950-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc10212; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3410213; GFX950-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse10214; GFX950-NEXT: v_and_b32_e32 v40, 0xffff0000, v1810215; GFX950-NEXT: v_cndmask_b32_e32 v31, v31, v34, vcc10216; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3810217; GFX950-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse10218; GFX950-NEXT: v_and_b32_e32 v41, 0xffff0000, v1710219; GFX950-NEXT: v_cndmask_b32_e32 v34, v35, v38, vcc10220; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3910221; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v2710222; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v2610223; GFX950-NEXT: v_cndmask_b32_e32 v31, v37, v31, vcc10224; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v32, v3210225; GFX950-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse10226; GFX950-NEXT: v_and_b32_e32 v42, 0xffff0000, v1610227; GFX950-NEXT: s_mov_b32 s0, 0x504010010228; GFX950-NEXT: s_waitcnt vmcnt(0)10229; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v5010230; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v5010231; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v35, vcc10232; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v3710233; GFX950-NEXT: v_lshlrev_b32_e32 v33, 16, v3210234; GFX950-NEXT: s_nop 010235; GFX950-NEXT: v_cndmask_b32_e32 v35, v35, v32, vcc10236; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v3510237; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v33, v3710238; GFX950-NEXT: s_nop 110239; GFX950-NEXT: v_cndmask_b32_e32 v33, v35, v32, vcc10240; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3210241; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v3310242; GFX950-NEXT: s_nop 010243; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc10244; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3510245; GFX950-NEXT: s_nop 110246; GFX950-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc10247; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3710248; GFX950-NEXT: v_lshrrev_b32_e32 v35, 16, v2810249; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v2810250; GFX950-NEXT: v_cndmask_b32_e32 v32, v33, v32, vcc10251; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4810252; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v2510253; GFX950-NEXT: s_nop 010254; GFX950-NEXT: v_cndmask_b32_e32 v33, v36, v34, vcc10255; GFX950-NEXT: v_and_b32_e32 v34, 0xffff0000, v1210256; GFX950-NEXT: v_lshrrev_b32_e32 v36, 16, v1210257; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v34, v3410258; GFX950-NEXT: s_nop 110259; GFX950-NEXT: v_cndmask_b32_e32 v34, v36, v35, vcc10260; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v3710261; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v3410262; GFX950-NEXT: s_nop 010263; GFX950-NEXT: v_cndmask_b32_e32 v35, v35, v34, vcc10264; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v3510265; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v36, v3710266; GFX950-NEXT: v_lshrrev_b32_e32 v37, 16, v1110267; GFX950-NEXT: s_nop 010268; GFX950-NEXT: v_cndmask_b32_e32 v36, v35, v34, vcc10269; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3410270; GFX950-NEXT: s_nop 110271; GFX950-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc10272; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3510273; GFX950-NEXT: s_nop 110274; GFX950-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc10275; GFX950-NEXT: v_lshlrev_b32_e32 v35, 16, v3610276; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3510277; GFX950-NEXT: v_and_b32_e32 v35, 0xffff0000, v1110278; GFX950-NEXT: s_nop 010279; GFX950-NEXT: v_cndmask_b32_e32 v34, v36, v34, vcc10280; GFX950-NEXT: v_lshrrev_b32_e32 v36, 16, v2710281; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v35, v3510282; GFX950-NEXT: s_nop 110283; GFX950-NEXT: v_cndmask_b32_e32 v35, v37, v36, vcc10284; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v38, v3810285; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v3510286; GFX950-NEXT: s_nop 010287; GFX950-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc10288; GFX950-NEXT: v_lshlrev_b32_e32 v38, 16, v3610289; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v37, v3810290; GFX950-NEXT: v_lshrrev_b32_e32 v38, 16, v1010291; GFX950-NEXT: s_nop 010292; GFX950-NEXT: v_cndmask_b32_e32 v37, v36, v35, vcc10293; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3510294; GFX950-NEXT: s_nop 110295; GFX950-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc10296; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3610297; GFX950-NEXT: s_nop 110298; GFX950-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc10299; GFX950-NEXT: v_lshlrev_b32_e32 v36, 16, v3710300; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3610301; GFX950-NEXT: v_and_b32_e32 v36, 0xffff0000, v1010302; GFX950-NEXT: s_nop 010303; GFX950-NEXT: v_cndmask_b32_e32 v35, v37, v35, vcc10304; GFX950-NEXT: v_lshrrev_b32_e32 v37, 16, v2610305; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v36, v3610306; GFX950-NEXT: s_nop 110307; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v37, vcc10308; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v39, v3910309; GFX950-NEXT: v_lshlrev_b32_e32 v38, 16, v3610310; GFX950-NEXT: s_nop 010311; GFX950-NEXT: v_cndmask_b32_e32 v37, v37, v36, vcc10312; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v3710313; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v38, v3910314; GFX950-NEXT: v_lshrrev_b32_e32 v39, 16, v910315; GFX950-NEXT: s_nop 010316; GFX950-NEXT: v_cndmask_b32_e32 v38, v37, v36, vcc10317; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3610318; GFX950-NEXT: s_nop 110319; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc10320; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3710321; GFX950-NEXT: s_nop 110322; GFX950-NEXT: v_cndmask_b32_e32 v36, v36, v37, vcc10323; GFX950-NEXT: v_lshlrev_b32_e32 v37, 16, v3810324; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3710325; GFX950-NEXT: v_and_b32_e32 v37, 0xffff0000, v910326; GFX950-NEXT: s_nop 010327; GFX950-NEXT: v_cndmask_b32_e32 v36, v38, v36, vcc10328; GFX950-NEXT: v_lshrrev_b32_e32 v38, 16, v2510329; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v37, v3710330; GFX950-NEXT: s_nop 110331; GFX950-NEXT: v_cndmask_b32_e32 v37, v39, v38, vcc10332; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v48, v4810333; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v3710334; GFX950-NEXT: s_nop 010335; GFX950-NEXT: v_cndmask_b32_e32 v38, v38, v37, vcc10336; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v3810337; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v39, v4810338; GFX950-NEXT: v_lshrrev_b32_e32 v48, 16, v810339; GFX950-NEXT: s_nop 010340; GFX950-NEXT: v_cndmask_b32_e32 v39, v38, v37, vcc10341; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3710342; GFX950-NEXT: s_nop 110343; GFX950-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc10344; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3810345; GFX950-NEXT: s_nop 110346; GFX950-NEXT: v_cndmask_b32_e32 v37, v37, v38, vcc10347; GFX950-NEXT: v_lshlrev_b32_e32 v38, 16, v3910348; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3810349; GFX950-NEXT: v_and_b32_e32 v38, 0xffff0000, v810350; GFX950-NEXT: s_nop 010351; GFX950-NEXT: v_cndmask_b32_e32 v37, v39, v37, vcc10352; GFX950-NEXT: v_lshrrev_b32_e32 v39, 16, v2410353; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v38, v3810354; GFX950-NEXT: s_nop 110355; GFX950-NEXT: v_cndmask_b32_e32 v38, v48, v39, vcc10356; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v49, v4910357; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v3810358; GFX950-NEXT: s_nop 010359; GFX950-NEXT: v_cndmask_b32_e32 v39, v39, v38, vcc10360; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v3910361; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v48, v4910362; GFX950-NEXT: v_lshrrev_b32_e32 v49, 16, v710363; GFX950-NEXT: s_nop 010364; GFX950-NEXT: v_cndmask_b32_e32 v48, v39, v38, vcc10365; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3810366; GFX950-NEXT: s_nop 110367; GFX950-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc10368; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3910369; GFX950-NEXT: s_nop 110370; GFX950-NEXT: v_cndmask_b32_e32 v38, v38, v39, vcc10371; GFX950-NEXT: v_lshlrev_b32_e32 v39, 16, v4810372; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3910373; GFX950-NEXT: v_and_b32_e32 v39, 0xffff0000, v710374; GFX950-NEXT: s_nop 010375; GFX950-NEXT: v_cndmask_b32_e32 v38, v48, v38, vcc10376; GFX950-NEXT: v_lshrrev_b32_e32 v48, 16, v2310377; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v39, v3910378; GFX950-NEXT: s_nop 110379; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v48, vcc10380; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v5110381; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v3910382; GFX950-NEXT: s_nop 010383; GFX950-NEXT: v_cndmask_b32_e32 v48, v48, v39, vcc10384; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v4810385; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v49, v5110386; GFX950-NEXT: v_lshrrev_b32_e32 v51, 16, v610387; GFX950-NEXT: s_nop 010388; GFX950-NEXT: v_cndmask_b32_e32 v49, v48, v39, vcc10389; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3910390; GFX950-NEXT: s_nop 110391; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc10392; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4810393; GFX950-NEXT: s_nop 110394; GFX950-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc10395; GFX950-NEXT: v_lshlrev_b32_e32 v48, 16, v4910396; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4810397; GFX950-NEXT: v_and_b32_e32 v48, 0xffff0000, v610398; GFX950-NEXT: s_nop 010399; GFX950-NEXT: v_cndmask_b32_e32 v39, v49, v39, vcc10400; GFX950-NEXT: v_lshrrev_b32_e32 v49, 16, v2210401; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v48, v4810402; GFX950-NEXT: s_nop 110403; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v49, vcc10404; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v52, v5210405; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v4810406; GFX950-NEXT: s_nop 010407; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v48, vcc10408; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v4910409; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v51, v5210410; GFX950-NEXT: v_lshrrev_b32_e32 v52, 16, v510411; GFX950-NEXT: s_nop 010412; GFX950-NEXT: v_cndmask_b32_e32 v51, v49, v48, vcc10413; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4810414; GFX950-NEXT: s_nop 110415; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc10416; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4910417; GFX950-NEXT: s_nop 110418; GFX950-NEXT: v_cndmask_b32_e32 v48, v48, v49, vcc10419; GFX950-NEXT: v_lshlrev_b32_e32 v49, 16, v5110420; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4910421; GFX950-NEXT: v_and_b32_e32 v49, 0xffff0000, v510422; GFX950-NEXT: s_nop 010423; GFX950-NEXT: v_cndmask_b32_e32 v48, v51, v48, vcc10424; GFX950-NEXT: v_lshrrev_b32_e32 v51, 16, v2110425; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v49, v4910426; GFX950-NEXT: s_nop 110427; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v51, vcc10428; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v53, v5310429; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v4910430; GFX950-NEXT: s_nop 010431; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v49, vcc10432; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v5110433; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v52, v5310434; GFX950-NEXT: v_lshrrev_b32_e32 v53, 16, v410435; GFX950-NEXT: s_nop 010436; GFX950-NEXT: v_cndmask_b32_e32 v52, v51, v49, vcc10437; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4910438; GFX950-NEXT: s_nop 110439; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc10440; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5110441; GFX950-NEXT: s_nop 110442; GFX950-NEXT: v_cndmask_b32_e32 v49, v49, v51, vcc10443; GFX950-NEXT: v_lshlrev_b32_e32 v51, 16, v5210444; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5110445; GFX950-NEXT: v_and_b32_e32 v51, 0xffff0000, v410446; GFX950-NEXT: s_nop 010447; GFX950-NEXT: v_cndmask_b32_e32 v49, v52, v49, vcc10448; GFX950-NEXT: v_lshrrev_b32_e32 v52, 16, v2010449; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v51, v5110450; GFX950-NEXT: s_nop 110451; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v52, vcc10452; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v54, v5410453; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v5110454; GFX950-NEXT: s_nop 010455; GFX950-NEXT: v_cndmask_b32_e32 v52, v52, v51, vcc10456; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v5210457; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v53, v5410458; GFX950-NEXT: v_lshrrev_b32_e32 v54, 16, v310459; GFX950-NEXT: s_nop 010460; GFX950-NEXT: v_cndmask_b32_e32 v53, v52, v51, vcc10461; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5110462; GFX950-NEXT: s_nop 110463; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc10464; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5210465; GFX950-NEXT: s_nop 110466; GFX950-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc10467; GFX950-NEXT: v_lshlrev_b32_e32 v52, 16, v5310468; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5210469; GFX950-NEXT: v_and_b32_e32 v52, 0xffff0000, v310470; GFX950-NEXT: s_nop 010471; GFX950-NEXT: v_cndmask_b32_e32 v51, v53, v51, vcc10472; GFX950-NEXT: v_lshrrev_b32_e32 v53, 16, v1910473; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v52, v5210474; GFX950-NEXT: s_nop 110475; GFX950-NEXT: v_cndmask_b32_e32 v52, v54, v53, vcc10476; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v55, v5510477; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v5210478; GFX950-NEXT: s_nop 010479; GFX950-NEXT: v_cndmask_b32_e32 v53, v53, v52, vcc10480; GFX950-NEXT: v_lshlrev_b32_e32 v55, 16, v5310481; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v54, v5510482; GFX950-NEXT: v_lshrrev_b32_e32 v55, 16, v210483; GFX950-NEXT: s_nop 010484; GFX950-NEXT: v_cndmask_b32_e32 v54, v53, v52, vcc10485; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5210486; GFX950-NEXT: s_nop 110487; GFX950-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc10488; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5310489; GFX950-NEXT: s_nop 110490; GFX950-NEXT: v_cndmask_b32_e32 v52, v52, v53, vcc10491; GFX950-NEXT: v_lshlrev_b32_e32 v53, 16, v5410492; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5310493; GFX950-NEXT: v_and_b32_e32 v53, 0xffff0000, v210494; GFX950-NEXT: s_nop 010495; GFX950-NEXT: v_cndmask_b32_e32 v52, v54, v52, vcc10496; GFX950-NEXT: v_lshrrev_b32_e32 v54, 16, v1810497; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v53, v5310498; GFX950-NEXT: s_nop 110499; GFX950-NEXT: v_cndmask_b32_e32 v53, v55, v54, vcc10500; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v4010501; GFX950-NEXT: v_lshlrev_b32_e32 v55, 16, v5310502; GFX950-NEXT: s_nop 010503; GFX950-NEXT: v_cndmask_b32_e32 v54, v54, v53, vcc10504; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v5410505; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v55, v4010506; GFX950-NEXT: v_lshrrev_b32_e32 v40, 16, v110507; GFX950-NEXT: s_nop 010508; GFX950-NEXT: v_cndmask_b32_e32 v55, v54, v53, vcc10509; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5310510; GFX950-NEXT: s_nop 110511; GFX950-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc10512; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5410513; GFX950-NEXT: s_nop 110514; GFX950-NEXT: v_cndmask_b32_e32 v53, v53, v54, vcc10515; GFX950-NEXT: v_lshlrev_b32_e32 v54, 16, v5510516; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5410517; GFX950-NEXT: v_and_b32_e32 v54, 0xffff0000, v110518; GFX950-NEXT: s_nop 010519; GFX950-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc10520; GFX950-NEXT: v_lshrrev_b32_e32 v55, 16, v1710521; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v54, v5410522; GFX950-NEXT: s_nop 110523; GFX950-NEXT: v_cndmask_b32_e32 v54, v40, v55, vcc10524; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v41, v4110525; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v5410526; GFX950-NEXT: s_nop 010527; GFX950-NEXT: v_cndmask_b32_e32 v55, v55, v54, vcc10528; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v5510529; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v40, v4110530; GFX950-NEXT: v_lshrrev_b32_e32 v41, 16, v010531; GFX950-NEXT: s_nop 010532; GFX950-NEXT: v_cndmask_b32_e32 v40, v55, v54, vcc10533; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5410534; GFX950-NEXT: s_nop 110535; GFX950-NEXT: v_cndmask_b32_e32 v54, v40, v54, vcc10536; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5510537; GFX950-NEXT: s_nop 110538; GFX950-NEXT: v_cndmask_b32_e32 v54, v54, v55, vcc10539; GFX950-NEXT: v_lshlrev_b32_e32 v55, 16, v4010540; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5510541; GFX950-NEXT: v_and_b32_e32 v55, 0xffff0000, v010542; GFX950-NEXT: s_nop 010543; GFX950-NEXT: v_cndmask_b32_e32 v54, v40, v54, vcc10544; GFX950-NEXT: v_lshrrev_b32_e32 v40, 16, v1610545; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v55, v5510546; GFX950-NEXT: s_nop 110547; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v40, vcc10548; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v42, v4210549; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v5510550; GFX950-NEXT: s_nop 010551; GFX950-NEXT: v_cndmask_b32_e32 v40, v40, v55, vcc10552; GFX950-NEXT: v_lshlrev_b32_e32 v42, 16, v4010553; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v41, v4210554; GFX950-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse10555; GFX950-NEXT: s_nop 010556; GFX950-NEXT: v_cndmask_b32_e32 v41, v40, v55, vcc10557; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5510558; GFX950-NEXT: s_nop 110559; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v55, vcc10560; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v4010561; GFX950-NEXT: s_nop 110562; GFX950-NEXT: v_cndmask_b32_e32 v55, v55, v40, vcc10563; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v4110564; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v4010565; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v1510566; GFX950-NEXT: s_nop 010567; GFX950-NEXT: v_cndmask_b32_e32 v55, v41, v55, vcc10568; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v4010569; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v5010570; GFX950-NEXT: s_nop 010571; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v50, vcc10572; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v40, v4010573; GFX950-NEXT: v_lshlrev_b32_e32 v41, 16, v1510574; GFX950-NEXT: s_nop 010575; GFX950-NEXT: v_cndmask_b32_e32 v50, v50, v15, vcc10576; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v5010577; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v41, v4010578; GFX950-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse10579; GFX950-NEXT: s_nop 010580; GFX950-NEXT: v_cndmask_b32_e32 v40, v50, v15, vcc10581; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1510582; GFX950-NEXT: s_nop 110583; GFX950-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc10584; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v5010585; GFX950-NEXT: s_nop 110586; GFX950-NEXT: v_cndmask_b32_e32 v15, v15, v50, vcc10587; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v4010588; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v5010589; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v1410590; GFX950-NEXT: s_nop 010591; GFX950-NEXT: v_cndmask_b32_e32 v15, v40, v15, vcc10592; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v5010593; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v3010594; GFX950-NEXT: v_perm_b32 v15, v32, v15, s010595; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc10596; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v50, v5010597; GFX950-NEXT: v_lshlrev_b32_e32 v40, 16, v1410598; GFX950-NEXT: s_nop 010599; GFX950-NEXT: v_cndmask_b32_e32 v30, v30, v14, vcc10600; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v3010601; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v40, v5010602; GFX950-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse10603; GFX950-NEXT: s_nop 010604; GFX950-NEXT: v_cndmask_b32_e32 v50, v30, v14, vcc10605; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1410606; GFX950-NEXT: s_nop 110607; GFX950-NEXT: v_cndmask_b32_e32 v14, v50, v14, vcc10608; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v3010609; GFX950-NEXT: s_nop 110610; GFX950-NEXT: v_cndmask_b32_e32 v14, v14, v30, vcc10611; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v5010612; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v3010613; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v1310614; GFX950-NEXT: s_nop 010615; GFX950-NEXT: v_cndmask_b32_e32 v14, v50, v14, vcc10616; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v30, v3010617; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v2910618; GFX950-NEXT: v_perm_b32 v14, v31, v14, s010619; GFX950-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc10620; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v30, v3010621; GFX950-NEXT: v_lshlrev_b32_e32 v50, 16, v1310622; GFX950-NEXT: s_nop 010623; GFX950-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc10624; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v2910625; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v50, v3010626; GFX950-NEXT: s_nop 110627; GFX950-NEXT: v_cndmask_b32_e32 v30, v29, v13, vcc10628; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1310629; GFX950-NEXT: s_nop 110630; GFX950-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc10631; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2910632; GFX950-NEXT: s_nop 110633; GFX950-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc10634; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v3010635; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2910636; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v1210637; GFX950-NEXT: s_nop 010638; GFX950-NEXT: v_cndmask_b32_e32 v13, v30, v13, vcc10639; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v29, v2910640; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v2810641; GFX950-NEXT: v_perm_b32 v13, v33, v13, s010642; GFX950-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc10643; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v29, v2910644; GFX950-NEXT: v_lshlrev_b32_e32 v30, 16, v1210645; GFX950-NEXT: s_nop 010646; GFX950-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc10647; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v2810648; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v30, v2910649; GFX950-NEXT: s_nop 110650; GFX950-NEXT: v_cndmask_b32_e32 v29, v28, v12, vcc10651; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1210652; GFX950-NEXT: s_nop 110653; GFX950-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc10654; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2810655; GFX950-NEXT: s_nop 110656; GFX950-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc10657; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v2910658; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2810659; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v1110660; GFX950-NEXT: s_nop 010661; GFX950-NEXT: v_cndmask_b32_e32 v12, v29, v12, vcc10662; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v28, v2810663; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v2710664; GFX950-NEXT: v_perm_b32 v12, v34, v12, s010665; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc10666; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v28, v2810667; GFX950-NEXT: v_lshlrev_b32_e32 v29, 16, v1110668; GFX950-NEXT: s_nop 010669; GFX950-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc10670; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v2710671; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v29, v2810672; GFX950-NEXT: s_nop 110673; GFX950-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc10674; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1110675; GFX950-NEXT: s_nop 110676; GFX950-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc10677; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2710678; GFX950-NEXT: s_nop 110679; GFX950-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc10680; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v2810681; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2710682; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v1010683; GFX950-NEXT: s_nop 010684; GFX950-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc10685; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v27, v2710686; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v2610687; GFX950-NEXT: v_perm_b32 v11, v35, v11, s010688; GFX950-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc10689; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v27, v2710690; GFX950-NEXT: v_lshlrev_b32_e32 v28, 16, v1010691; GFX950-NEXT: s_nop 010692; GFX950-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc10693; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v2610694; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v28, v2710695; GFX950-NEXT: s_nop 110696; GFX950-NEXT: v_cndmask_b32_e32 v27, v26, v10, vcc10697; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1010698; GFX950-NEXT: s_nop 110699; GFX950-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc10700; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2610701; GFX950-NEXT: s_nop 110702; GFX950-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc10703; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v2710704; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2610705; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v910706; GFX950-NEXT: s_nop 010707; GFX950-NEXT: v_cndmask_b32_e32 v10, v27, v10, vcc10708; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v26, v2610709; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v2510710; GFX950-NEXT: v_perm_b32 v10, v36, v10, s010711; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc10712; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v26, v2610713; GFX950-NEXT: v_lshlrev_b32_e32 v27, 16, v910714; GFX950-NEXT: s_nop 010715; GFX950-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc10716; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v2510717; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v27, v2610718; GFX950-NEXT: s_nop 110719; GFX950-NEXT: v_cndmask_b32_e32 v26, v25, v9, vcc10720; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v910721; GFX950-NEXT: s_nop 110722; GFX950-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc10723; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2510724; GFX950-NEXT: s_nop 110725; GFX950-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc10726; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v2610727; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2510728; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v810729; GFX950-NEXT: s_nop 010730; GFX950-NEXT: v_cndmask_b32_e32 v9, v26, v9, vcc10731; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v25, v2510732; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v2410733; GFX950-NEXT: v_perm_b32 v9, v37, v9, s010734; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc10735; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v25, v2510736; GFX950-NEXT: v_lshlrev_b32_e32 v26, 16, v810737; GFX950-NEXT: s_nop 010738; GFX950-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc10739; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v2410740; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v26, v2510741; GFX950-NEXT: s_nop 110742; GFX950-NEXT: v_cndmask_b32_e32 v25, v24, v8, vcc10743; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v810744; GFX950-NEXT: s_nop 110745; GFX950-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc10746; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2410747; GFX950-NEXT: s_nop 110748; GFX950-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc10749; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v2510750; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2410751; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v710752; GFX950-NEXT: s_nop 010753; GFX950-NEXT: v_cndmask_b32_e32 v8, v25, v8, vcc10754; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v2410755; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v2310756; GFX950-NEXT: v_perm_b32 v8, v38, v8, s010757; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc10758; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v24, v2410759; GFX950-NEXT: v_lshlrev_b32_e32 v25, 16, v710760; GFX950-NEXT: s_nop 010761; GFX950-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc10762; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v2310763; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v25, v2410764; GFX950-NEXT: s_nop 110765; GFX950-NEXT: v_cndmask_b32_e32 v24, v23, v7, vcc10766; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v710767; GFX950-NEXT: s_nop 110768; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc10769; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2310770; GFX950-NEXT: s_nop 110771; GFX950-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc10772; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v2410773; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2310774; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v610775; GFX950-NEXT: s_nop 010776; GFX950-NEXT: v_cndmask_b32_e32 v7, v24, v7, vcc10777; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v23, v2310778; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v2210779; GFX950-NEXT: v_perm_b32 v7, v39, v7, s010780; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc10781; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v23, v2310782; GFX950-NEXT: v_lshlrev_b32_e32 v24, 16, v610783; GFX950-NEXT: s_nop 010784; GFX950-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc10785; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v2210786; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v24, v2310787; GFX950-NEXT: s_nop 110788; GFX950-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc10789; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v610790; GFX950-NEXT: s_nop 110791; GFX950-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc10792; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2210793; GFX950-NEXT: s_nop 110794; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc10795; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v2310796; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2210797; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v510798; GFX950-NEXT: s_nop 010799; GFX950-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc10800; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v22, v2210801; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v2110802; GFX950-NEXT: v_perm_b32 v6, v48, v6, s010803; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc10804; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v22, v2210805; GFX950-NEXT: v_lshlrev_b32_e32 v23, 16, v510806; GFX950-NEXT: s_nop 010807; GFX950-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc10808; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v2110809; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v23, v2210810; GFX950-NEXT: s_nop 110811; GFX950-NEXT: v_cndmask_b32_e32 v22, v21, v5, vcc10812; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v510813; GFX950-NEXT: s_nop 110814; GFX950-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc10815; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2110816; GFX950-NEXT: s_nop 110817; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc10818; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v2210819; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2110820; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v410821; GFX950-NEXT: s_nop 010822; GFX950-NEXT: v_cndmask_b32_e32 v5, v22, v5, vcc10823; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v21, v2110824; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v2010825; GFX950-NEXT: v_perm_b32 v5, v49, v5, s010826; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc10827; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v21, v2110828; GFX950-NEXT: v_lshlrev_b32_e32 v22, 16, v410829; GFX950-NEXT: s_nop 010830; GFX950-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc10831; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v2010832; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v22, v2110833; GFX950-NEXT: s_nop 110834; GFX950-NEXT: v_cndmask_b32_e32 v21, v20, v4, vcc10835; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v410836; GFX950-NEXT: s_nop 110837; GFX950-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc10838; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v2010839; GFX950-NEXT: s_nop 110840; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc10841; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v2110842; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v2010843; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v310844; GFX950-NEXT: s_nop 010845; GFX950-NEXT: v_cndmask_b32_e32 v4, v21, v4, vcc10846; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v20, v2010847; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v1910848; GFX950-NEXT: v_perm_b32 v4, v51, v4, s010849; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc10850; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v20, v2010851; GFX950-NEXT: v_lshlrev_b32_e32 v21, 16, v310852; GFX950-NEXT: s_nop 010853; GFX950-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc10854; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v1910855; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v21, v2010856; GFX950-NEXT: s_nop 110857; GFX950-NEXT: v_cndmask_b32_e32 v20, v19, v3, vcc10858; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v310859; GFX950-NEXT: s_nop 110860; GFX950-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc10861; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1910862; GFX950-NEXT: s_nop 110863; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc10864; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v2010865; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1910866; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v210867; GFX950-NEXT: s_nop 010868; GFX950-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc10869; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v1910870; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v1810871; GFX950-NEXT: v_perm_b32 v3, v52, v3, s010872; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc10873; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v19, v1910874; GFX950-NEXT: v_lshlrev_b32_e32 v20, 16, v210875; GFX950-NEXT: s_nop 010876; GFX950-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc10877; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v1810878; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v20, v1910879; GFX950-NEXT: s_nop 110880; GFX950-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc10881; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v210882; GFX950-NEXT: s_nop 110883; GFX950-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc10884; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1810885; GFX950-NEXT: s_nop 110886; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc10887; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v1910888; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1810889; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v110890; GFX950-NEXT: s_nop 010891; GFX950-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc10892; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v18, v1810893; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v1710894; GFX950-NEXT: v_perm_b32 v2, v53, v2, s010895; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc10896; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v18, v1810897; GFX950-NEXT: v_lshlrev_b32_e32 v19, 16, v110898; GFX950-NEXT: s_nop 010899; GFX950-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc10900; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v1710901; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v19, v1810902; GFX950-NEXT: s_nop 110903; GFX950-NEXT: v_cndmask_b32_e32 v18, v17, v1, vcc10904; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v110905; GFX950-NEXT: s_nop 110906; GFX950-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc10907; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1710908; GFX950-NEXT: s_nop 110909; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc10910; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v1810911; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1710912; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v010913; GFX950-NEXT: s_nop 010914; GFX950-NEXT: v_cndmask_b32_e32 v1, v18, v1, vcc10915; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v1710916; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v1610917; GFX950-NEXT: v_perm_b32 v1, v54, v1, s010918; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc10919; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v17, v1710920; GFX950-NEXT: v_lshlrev_b32_e32 v18, 16, v010921; GFX950-NEXT: s_nop 010922; GFX950-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc10923; GFX950-NEXT: v_lshlrev_b32_e32 v17, 16, v1610924; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v18, v1710925; GFX950-NEXT: s_nop 110926; GFX950-NEXT: v_cndmask_b32_e32 v17, v16, v0, vcc10927; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v010928; GFX950-NEXT: s_nop 110929; GFX950-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc10930; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v1610931; GFX950-NEXT: s_nop 110932; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc10933; GFX950-NEXT: v_lshlrev_b32_e32 v16, 16, v1710934; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v1610935; GFX950-NEXT: s_nop 110936; GFX950-NEXT: v_cndmask_b32_e32 v0, v17, v0, vcc10937; GFX950-NEXT: v_perm_b32 v0, v55, v0, s010938; GFX950-NEXT: s_setpc_b64 s[30:31]10939;10940; GFX10-LABEL: v_maximumnum_v32bf16:10941; GFX10: ; %bb.0:10942; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10943; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v1310944; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v2910945; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v1310946; GFX10-NEXT: v_and_b32_e32 v33, 0xffff0000, v1210947; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v2810948; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v3110949; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v1210950; GFX10-NEXT: v_and_b32_e32 v37, 0xffff0000, v1110951; GFX10-NEXT: v_and_b32_e32 v36, 0xffff0000, v2910952; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v2710953; GFX10-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo10954; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v3310955; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v1110956; GFX10-NEXT: v_and_b32_e32 v49, 0xffff0000, v2810957; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v1010958; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v3210959; GFX10-NEXT: v_cndmask_b32_e32 v34, v34, v38, vcc_lo10960; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v3710961; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v2610962; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v1010963; GFX10-NEXT: v_cmp_u_f32_e64 s6, v51, v5110964; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v810965; GFX10-NEXT: v_cndmask_b32_e32 v33, v48, v39, vcc_lo10966; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v3610967; GFX10-NEXT: v_and_b32_e32 v48, 0xffff0000, v2710968; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v2310969; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v710970; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v2210971; GFX10-NEXT: v_cndmask_b32_e32 v37, v35, v32, vcc_lo10972; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v4910973; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v3310974; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v610975; GFX10-NEXT: v_lshrrev_b32_e32 v70, 16, v410976; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v2010977; GFX10-NEXT: v_cndmask_b32_e32 v36, v38, v34, vcc_lo10978; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v4810979; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v3710980; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v310981; GFX10-NEXT: v_lshrrev_b32_e32 v85, 16, v1410982; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v3610983; GFX10-NEXT: v_cndmask_b32_e32 v35, v39, v33, vcc_lo10984; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3410985; GFX10-NEXT: v_cmp_gt_f32_e64 s5, v31, v3810986; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v2610987; GFX10-NEXT: v_cndmask_b32_e64 v38, v53, v52, s610988; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v3510989; GFX10-NEXT: v_cmp_gt_f32_e64 s4, v39, v4810990; GFX10-NEXT: v_and_b32_e32 v39, 0xffff0000, v910991; GFX10-NEXT: v_cmp_u_f32_e64 s6, v31, v3110992; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v2510993; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v49, v5010994; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v2510995; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v910996; GFX10-NEXT: v_cndmask_b32_e64 v48, v52, v38, s610997; GFX10-NEXT: v_cmp_u_f32_e64 s6, v39, v3910998; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v810999; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v3811000; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v2411001; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v4811002; GFX10-NEXT: v_cndmask_b32_e64 v39, v50, v49, s611003; GFX10-NEXT: v_cmp_u_f32_e64 s6, v31, v3111004; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v3911005; GFX10-NEXT: v_cndmask_b32_e64 v50, v49, v39, s611006; GFX10-NEXT: v_cmp_u_f32_e64 s6, v52, v5211007; GFX10-NEXT: v_and_b32_e32 v52, 0xffff0000, v2411008; GFX10-NEXT: v_cndmask_b32_e64 v49, v54, v53, s611009; GFX10-NEXT: v_cmp_gt_f32_e64 s6, v51, v5511010; GFX10-NEXT: v_and_b32_e32 v55, 0xffff0000, v711011; GFX10-NEXT: v_cmp_u_f32_e64 s7, v52, v5211012; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5011013; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v4911014; GFX10-NEXT: v_cndmask_b32_e64 v52, v53, v49, s711015; GFX10-NEXT: v_and_b32_e32 v53, 0xffff0000, v2311016; GFX10-NEXT: v_cmp_u_f32_e64 s7, v55, v5511017; GFX10-NEXT: v_cmp_gt_f32_e64 s8, v31, v5111018; GFX10-NEXT: v_cndmask_b32_e64 v55, v65, v64, s711019; GFX10-NEXT: v_and_b32_e32 v65, 0xffff0000, v611020; GFX10-NEXT: v_cmp_u_f32_e64 s7, v53, v5311021; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5511022; GFX10-NEXT: v_cndmask_b32_e64 v53, v64, v55, s711023; GFX10-NEXT: v_cmp_u_f32_e64 s7, v65, v6511024; GFX10-NEXT: v_and_b32_e32 v64, 0xffff0000, v2211025; GFX10-NEXT: v_lshlrev_b32_e32 v69, 16, v5311026; GFX10-NEXT: v_cndmask_b32_e64 v65, v67, v66, s711027; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v5211028; GFX10-NEXT: v_cmp_u_f32_e64 s7, v64, v6411029; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v6511030; GFX10-NEXT: v_cmp_gt_f32_e64 s9, v54, v6711031; GFX10-NEXT: v_and_b32_e32 v54, 0xffff0000, v511032; GFX10-NEXT: v_cndmask_b32_e64 v64, v66, v65, s711033; GFX10-NEXT: v_cmp_gt_f32_e64 s7, v68, v6911034; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v2111035; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v511036; GFX10-NEXT: v_and_b32_e32 v68, 0xffff0000, v411037; GFX10-NEXT: v_cmp_u_f32_e64 s10, v54, v5411038; GFX10-NEXT: v_lshrrev_b32_e32 v69, 16, v2011039; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v6411040; GFX10-NEXT: v_cndmask_b32_e64 v54, v67, v66, s1011041; GFX10-NEXT: v_and_b32_e32 v67, 0xffff0000, v2111042; GFX10-NEXT: v_cmp_u_f32_e64 s10, v68, v6811043; GFX10-NEXT: v_cndmask_b32_e64 v68, v70, v69, s1011044; GFX10-NEXT: v_cmp_u_f32_e64 s10, v67, v6711045; GFX10-NEXT: v_lshlrev_b32_e32 v70, 16, v5411046; GFX10-NEXT: v_lshlrev_b32_e32 v82, 16, v6811047; GFX10-NEXT: v_cndmask_b32_e64 v66, v66, v54, s1011048; GFX10-NEXT: v_cmp_u_f32_e64 s10, v71, v7111049; GFX10-NEXT: v_lshrrev_b32_e32 v71, 16, v1911050; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v6611051; GFX10-NEXT: v_cndmask_b32_e64 v67, v69, v68, s1011052; GFX10-NEXT: v_and_b32_e32 v69, 0xffff0000, v311053; GFX10-NEXT: v_cmp_gt_f32_e64 s11, v70, v8111054; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v6711055; GFX10-NEXT: v_cmp_u_f32_e64 s10, v69, v6911056; GFX10-NEXT: v_and_b32_e32 v70, 0xffff0000, v211057; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v211058; GFX10-NEXT: v_cmp_gt_f32_e64 s12, v82, v8311059; GFX10-NEXT: v_cndmask_b32_e64 v69, v80, v71, s1011060; GFX10-NEXT: v_cmp_gt_f32_e64 s10, v31, v5111061; GFX10-NEXT: v_and_b32_e32 v51, 0xffff0000, v1911062; GFX10-NEXT: v_lshrrev_b32_e32 v80, 16, v1811063; GFX10-NEXT: v_and_b32_e32 v82, 0xffff0000, v1811064; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v6911065; GFX10-NEXT: v_cmp_u_f32_e64 s13, v51, v5111066; GFX10-NEXT: v_cndmask_b32_e64 v51, v71, v69, s1311067; GFX10-NEXT: v_cmp_u_f32_e64 s13, v70, v7011068; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v111069; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v5111070; GFX10-NEXT: v_cndmask_b32_e64 v70, v81, v80, s1311071; GFX10-NEXT: v_cmp_u_f32_e64 s13, v82, v8211072; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v1711073; GFX10-NEXT: v_lshrrev_b32_e32 v82, 16, v111074; GFX10-NEXT: v_cndmask_b32_e64 v80, v80, v70, s1311075; GFX10-NEXT: v_cmp_u_f32_e64 s13, v71, v7111076; GFX10-NEXT: v_and_b32_e32 v71, 0xffff0000, v1711077; GFX10-NEXT: v_cndmask_b32_e64 v82, v82, v81, s1311078; GFX10-NEXT: v_cmp_u_f32_e64 s14, v71, v7111079; GFX10-NEXT: v_cmp_gt_f32_e64 s13, v31, v8311080; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v7011081; GFX10-NEXT: v_lshlrev_b32_e32 v83, 16, v8011082; GFX10-NEXT: v_cndmask_b32_e64 v71, v81, v82, s1411083; GFX10-NEXT: v_cmp_gt_f32_e64 s14, v31, v8311084; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v8211085; GFX10-NEXT: v_lshlrev_b32_e32 v81, 16, v7111086; GFX10-NEXT: v_lshrrev_b32_e32 v83, 16, v011087; GFX10-NEXT: v_cmp_gt_f32_e64 s15, v31, v8111088; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v011089; GFX10-NEXT: v_lshrrev_b32_e32 v81, 16, v1611090; GFX10-NEXT: v_cmp_u_f32_e64 s16, v31, v3111091; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v1611092; GFX10-NEXT: v_cndmask_b32_e64 v83, v83, v81, s1611093; GFX10-NEXT: v_cmp_u_f32_e64 s16, v31, v3111094; GFX10-NEXT: v_lshlrev_b32_e32 v31, 16, v8311095; GFX10-NEXT: v_cndmask_b32_e64 v81, v81, v83, s1611096; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v8111097; GFX10-NEXT: v_cmp_gt_f32_e64 s16, v31, v8411098; GFX10-NEXT: v_and_b32_e32 v31, 0xffff0000, v1411099; GFX10-NEXT: v_lshrrev_b32_e32 v84, 16, v3011100; GFX10-NEXT: v_cmp_u_f32_e64 s17, v31, v3111101; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v84, s1711102; GFX10-NEXT: v_and_b32_e32 v85, 0xffff0000, v3011103; GFX10-NEXT: v_cmp_u_f32_e64 s17, v85, v8511104; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v3111105; GFX10-NEXT: v_cndmask_b32_e64 v84, v84, v31, s1711106; GFX10-NEXT: v_lshlrev_b32_e32 v86, 16, v8411107; GFX10-NEXT: v_cmp_gt_f32_e64 s17, v85, v8611108; GFX10-NEXT: v_lshrrev_b32_e32 v86, 16, v1511109; GFX10-NEXT: v_cndmask_b32_e64 v85, v84, v31, s1711110; GFX10-NEXT: v_cmp_eq_u16_e64 s17, 0, v3111111; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v31, s1711112; GFX10-NEXT: v_cmp_eq_u16_e64 s17, 0, v8411113; GFX10-NEXT: v_cndmask_b32_e64 v31, v31, v84, s1711114; GFX10-NEXT: v_lshlrev_b32_e32 v84, 16, v8511115; GFX10-NEXT: v_cmp_eq_f32_e64 s17, 0, v8411116; GFX10-NEXT: v_cndmask_b32_e64 v84, v37, v32, s511117; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v3211118; GFX10-NEXT: v_cndmask_b32_e64 v31, v85, v31, s1711119; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v1511120; GFX10-NEXT: v_cndmask_b32_e64 v32, v84, v32, s511121; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v3711122; GFX10-NEXT: v_cndmask_b32_e64 v32, v32, v37, s511123; GFX10-NEXT: v_cndmask_b32_e64 v37, v36, v34, s411124; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v3411125; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v3911126; GFX10-NEXT: v_cndmask_b32_e64 v34, v37, v34, s411127; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v3611128; GFX10-NEXT: v_cndmask_b32_e64 v34, v34, v36, s411129; GFX10-NEXT: v_cndmask_b32_e32 v36, v35, v33, vcc_lo11130; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3311131; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v3811132; GFX10-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc_lo11133; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3511134; GFX10-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo11135; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v3611136; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3511137; GFX10-NEXT: v_cndmask_b32_e64 v35, v48, v38, s611138; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v4911139; GFX10-NEXT: v_cndmask_b32_e32 v33, v36, v33, vcc_lo11140; GFX10-NEXT: v_cndmask_b32_e64 v38, v35, v38, s411141; GFX10-NEXT: v_cmp_eq_u16_e64 s4, 0, v4811142; GFX10-NEXT: v_cndmask_b32_e64 v38, v38, v48, s411143; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v3511144; GFX10-NEXT: v_cmp_eq_f32_e64 s4, 0, v4811145; GFX10-NEXT: v_cndmask_b32_e64 v48, v50, v39, s811146; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v6511147; GFX10-NEXT: v_cndmask_b32_e64 v39, v48, v39, s511148; GFX10-NEXT: v_cmp_eq_u16_e64 s5, 0, v5011149; GFX10-NEXT: v_cndmask_b32_e64 v39, v39, v50, s511150; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v4811151; GFX10-NEXT: v_cmp_eq_f32_e64 s5, 0, v5011152; GFX10-NEXT: v_cndmask_b32_e64 v50, v52, v49, s911153; GFX10-NEXT: v_cmp_eq_u16_e64 s9, 0, v6811154; GFX10-NEXT: v_cndmask_b32_e64 v49, v50, v49, s611155; GFX10-NEXT: v_cmp_eq_u16_e64 s6, 0, v5211156; GFX10-NEXT: v_cndmask_b32_e64 v49, v49, v52, s611157; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v5011158; GFX10-NEXT: v_cmp_eq_f32_e64 s6, 0, v5211159; GFX10-NEXT: v_cndmask_b32_e64 v52, v53, v55, s711160; GFX10-NEXT: v_cmp_eq_u16_e64 s7, 0, v5511161; GFX10-NEXT: v_cndmask_b32_e64 v55, v52, v55, s711162; GFX10-NEXT: v_cmp_eq_u16_e64 s7, 0, v5311163; GFX10-NEXT: v_cndmask_b32_e64 v53, v55, v53, s711164; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v5211165; GFX10-NEXT: v_cmp_eq_f32_e64 s7, 0, v5511166; GFX10-NEXT: v_cndmask_b32_e64 v55, v64, v65, s1011167; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v6911168; GFX10-NEXT: v_cndmask_b32_e64 v36, v52, v53, s711169; GFX10-NEXT: v_cndmask_b32_e64 v65, v55, v65, s811170; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v6411171; GFX10-NEXT: v_cndmask_b32_e64 v64, v65, v64, s811172; GFX10-NEXT: v_cndmask_b32_e64 v65, v66, v54, s1111173; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v5411174; GFX10-NEXT: v_cndmask_b32_e64 v54, v65, v54, s811175; GFX10-NEXT: v_cmp_eq_u16_e64 s8, 0, v6611176; GFX10-NEXT: v_cndmask_b32_e64 v54, v54, v66, s811177; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6511178; GFX10-NEXT: v_cmp_eq_f32_e64 s8, 0, v6611179; GFX10-NEXT: v_cndmask_b32_e64 v66, v67, v68, s1211180; GFX10-NEXT: v_cndmask_b32_e64 v68, v66, v68, s911181; GFX10-NEXT: v_cmp_eq_u16_e64 s9, 0, v6711182; GFX10-NEXT: v_cndmask_b32_e64 v67, v68, v67, s911183; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v6611184; GFX10-NEXT: v_cmp_eq_f32_e64 s9, 0, v6811185; GFX10-NEXT: v_cndmask_b32_e64 v68, v51, v69, s1311186; GFX10-NEXT: v_cndmask_b32_e64 v69, v68, v69, s1011187; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v5111188; GFX10-NEXT: v_cndmask_b32_e64 v51, v69, v51, s1011189; GFX10-NEXT: v_cndmask_b32_e64 v69, v80, v70, s1411190; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v7011191; GFX10-NEXT: v_cndmask_b32_e64 v70, v69, v70, s1011192; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v8011193; GFX10-NEXT: v_cndmask_b32_e64 v70, v70, v80, s1011194; GFX10-NEXT: v_cndmask_b32_e64 v80, v71, v82, s1511195; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v8211196; GFX10-NEXT: v_cndmask_b32_e64 v82, v80, v82, s1011197; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v7111198; GFX10-NEXT: v_cndmask_b32_e64 v71, v82, v71, s1011199; GFX10-NEXT: v_cndmask_b32_e64 v82, v81, v83, s1611200; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v8311201; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v8211202; GFX10-NEXT: v_cndmask_b32_e64 v83, v82, v83, s1011203; GFX10-NEXT: v_cmp_eq_u16_e64 s10, 0, v8111204; GFX10-NEXT: v_cndmask_b32_e64 v81, v83, v81, s1011205; GFX10-NEXT: buffer_load_dword v83, off, s[0:3], s3211206; GFX10-NEXT: v_cmp_u_f32_e64 s10, v85, v8511207; GFX10-NEXT: v_lshlrev_b32_e32 v85, 16, v1411208; GFX10-NEXT: v_cmp_u_f32_e64 s11, v85, v8511209; GFX10-NEXT: v_cndmask_b32_e64 v85, v14, v30, s1111210; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v3011211; GFX10-NEXT: v_cmp_u_f32_e64 s11, v14, v1411212; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v8411213; GFX10-NEXT: v_cndmask_b32_e64 v87, v30, v85, s1111214; GFX10-NEXT: v_cmp_eq_f32_e64 s12, 0, v1411215; GFX10-NEXT: v_cndmask_b32_e64 v30, v35, v38, s411216; GFX10-NEXT: v_cndmask_b32_e64 v35, v50, v49, s611217; GFX10-NEXT: v_cndmask_b32_e64 v38, v65, v54, s811218; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v8011219; GFX10-NEXT: v_cndmask_b32_e64 v14, v84, v32, s1211220; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v3711221; GFX10-NEXT: v_and_b32_e32 v84, 0xffff0000, v1511222; GFX10-NEXT: v_cmp_eq_f32_e64 s12, 0, v3211223; GFX10-NEXT: v_cndmask_b32_e64 v32, v37, v34, s1211224; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v5511225; GFX10-NEXT: v_cndmask_b32_e64 v34, v48, v39, s511226; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v6811227; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v6911228; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3711229; GFX10-NEXT: v_cndmask_b32_e32 v37, v55, v64, vcc_lo11230; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v84, v8411231; GFX10-NEXT: s_waitcnt vmcnt(0)11232; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v8311233; GFX10-NEXT: v_and_b32_e32 v53, 0xffff0000, v8311234; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v8311235; GFX10-NEXT: v_cndmask_b32_e64 v64, v15, v83, s1011236; GFX10-NEXT: v_cndmask_b32_e64 v15, v66, v67, s911237; GFX10-NEXT: v_cndmask_b32_e32 v54, v86, v50, vcc_lo11238; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v5311239; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v6411240; GFX10-NEXT: v_cndmask_b32_e32 v53, v50, v54, vcc_lo11241; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5511242; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v5411243; GFX10-NEXT: v_cndmask_b32_e32 v55, v83, v64, vcc_lo11244; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3911245; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v5511246; GFX10-NEXT: v_cndmask_b32_e32 v39, v68, v51, vcc_lo11247; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5311248; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4811249; GFX10-NEXT: v_cndmask_b32_e32 v48, v69, v70, vcc_lo11250; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v5111251; GFX10-NEXT: v_cndmask_b32_e32 v51, v53, v54, vcc_lo11252; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v6611253; GFX10-NEXT: v_cndmask_b32_e32 v65, v55, v64, vcc_lo11254; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4911255; GFX10-NEXT: v_cndmask_b32_e32 v50, v80, v71, vcc_lo11256; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5411257; GFX10-NEXT: v_cndmask_b32_e32 v49, v51, v54, vcc_lo11258; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6411259; GFX10-NEXT: v_cndmask_b32_e32 v54, v65, v64, vcc_lo11260; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5311261; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v5111262; GFX10-NEXT: v_cndmask_b32_e32 v49, v49, v53, vcc_lo11263; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5511264; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6511265; GFX10-NEXT: v_cndmask_b32_e32 v54, v54, v55, vcc_lo11266; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6411267; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v1311268; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v2911269; GFX10-NEXT: v_cndmask_b32_e32 v49, v51, v49, vcc_lo11270; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5211271; GFX10-NEXT: v_cndmask_b32_e32 v52, v82, v81, vcc_lo11272; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5311273; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v8711274; GFX10-NEXT: v_cndmask_b32_e32 v51, v65, v54, vcc_lo11275; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8511276; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5511277; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v1211278; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo11279; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v5311280; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v2811281; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v1311282; GFX10-NEXT: v_cndmask_b32_e32 v53, v87, v85, vcc_lo11283; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v64, v6411284; GFX10-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo11285; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5511286; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v2911287; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo11288; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8511289; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v1211290; GFX10-NEXT: v_cndmask_b32_e32 v55, v53, v85, vcc_lo11291; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v5411292; GFX10-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo11293; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8711294; GFX10-NEXT: v_cndmask_b32_e32 v28, v55, v87, vcc_lo11295; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v6411296; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v5311297; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v5411298; GFX10-NEXT: v_cndmask_b32_e32 v55, v29, v13, vcc_lo11299; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1311300; GFX10-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo11301; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6411302; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v5511303; GFX10-NEXT: v_cndmask_b32_e32 v28, v53, v28, vcc_lo11304; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v6511305; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v2711306; GFX10-NEXT: v_cndmask_b32_e32 v53, v54, v12, vcc_lo11307; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2911308; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo11309; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v1111310; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1211311; GFX10-NEXT: v_cndmask_b32_e32 v12, v53, v12, vcc_lo11312; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2911313; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v5311314; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo11315; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5411316; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v54, vcc_lo11317; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6511318; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v1011319; GFX10-NEXT: v_cndmask_b32_e32 v27, v27, v11, vcc_lo11320; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6411321; GFX10-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo11322; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2911323; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v2711324; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v2611325; GFX10-NEXT: v_perm_b32 v13, v14, v13, 0x504010011326; GFX10-NEXT: v_cndmask_b32_e32 v12, v53, v12, vcc_lo11327; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v1111328; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v5411329; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v911330; GFX10-NEXT: v_perm_b32 v14, v31, v28, 0x504010011331; GFX10-NEXT: v_perm_b32 v12, v32, v12, 0x504010011332; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo11333; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v2911334; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v2511335; GFX10-NEXT: v_cndmask_b32_e32 v29, v27, v11, vcc_lo11336; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5511337; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v1011338; GFX10-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo11339; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v5411340; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v2611341; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo11342; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1111343; GFX10-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc_lo11344; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v5311345; GFX10-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo11346; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2711347; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo11348; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v2911349; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v5411350; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v2511351; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v911352; GFX10-NEXT: v_cndmask_b32_e32 v53, v26, v10, vcc_lo11353; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2711354; GFX10-NEXT: v_cndmask_b32_e32 v11, v29, v11, vcc_lo11355; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1011356; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v5311357; GFX10-NEXT: v_perm_b32 v11, v33, v11, 0x504010011358; GFX10-NEXT: v_cndmask_b32_e32 v10, v53, v10, vcc_lo11359; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v5411360; GFX10-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo11361; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2611362; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo11363; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v911364; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v811365; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo11366; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2911367; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v2311368; GFX10-NEXT: v_cndmask_b32_e32 v10, v53, v10, vcc_lo11369; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2511370; GFX10-NEXT: v_perm_b32 v10, v30, v10, 0x504010011371; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo11372; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v711373; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v2611374; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v2411375; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo11376; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2511377; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v2711378; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo11379; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v2611380; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v711381; GFX10-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo11382; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2911383; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v2411384; GFX10-NEXT: v_cndmask_b32_e32 v23, v23, v7, vcc_lo11385; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2511386; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v611387; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v2311388; GFX10-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo11389; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v811390; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2511391; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v2211392; GFX10-NEXT: v_perm_b32 v9, v34, v9, 0x504010011393; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo11394; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v2611395; GFX10-NEXT: v_cndmask_b32_e32 v26, v24, v8, vcc_lo11396; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v2911397; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v611398; GFX10-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo11399; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2511400; GFX10-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo11401; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v811402; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v2211403; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo11404; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v711405; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo11406; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2411407; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo11408; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2311409; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v2611410; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v23, vcc_lo11411; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v2511412; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v2711413; GFX10-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo11414; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2411415; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v511416; GFX10-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo11417; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v611418; GFX10-NEXT: v_perm_b32 v8, v35, v8, 0x504010011419; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo11420; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2511421; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v2111422; GFX10-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo11423; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2211424; GFX10-NEXT: v_perm_b32 v7, v36, v7, 0x504010011425; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo11426; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v2311427; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v2411428; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v411429; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo11430; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2211431; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v2011432; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo11433; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2511434; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v311435; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v511436; GFX10-NEXT: v_perm_b32 v6, v37, v6, 0x504010011437; GFX10-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo11438; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v2411439; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v2111440; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo11441; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v2211442; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v1911443; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo11444; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v2311445; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo11446; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2411447; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v2011448; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v411449; GFX10-NEXT: v_cndmask_b32_e32 v23, v21, v5, vcc_lo11450; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v2211451; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo11452; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v511453; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo11454; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2411455; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v1911456; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v311457; GFX10-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo11458; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2111459; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo11460; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v411461; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v2311462; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo11463; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2411464; GFX10-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo11465; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2111466; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v2211467; GFX10-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo11468; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2011469; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v2411470; GFX10-NEXT: v_perm_b32 v5, v38, v5, 0x504010011471; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo11472; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v311473; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v211474; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo11475; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1911476; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo11477; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2011478; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v1811479; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v111480; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo11481; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2311482; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v011483; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo11484; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v1911485; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v1711486; GFX10-NEXT: v_perm_b32 v3, v39, v3, 0x504010011487; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo11488; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2011489; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1611490; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo11491; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v2311492; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v211493; GFX10-NEXT: v_lshlrev_b32_e32 v24, 16, v111494; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo11495; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v1911496; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v1811497; GFX10-NEXT: v_lshlrev_b32_e32 v25, 16, v011498; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v1, vcc_lo11499; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2011500; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1711501; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc_lo11502; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v1911503; GFX10-NEXT: v_lshlrev_b32_e32 v23, 16, v1611504; GFX10-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo11505; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v2011506; GFX10-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo11507; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v211508; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo11509; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2311510; GFX10-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo11511; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v111512; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo11513; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1811514; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo11515; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v011516; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v2311517; GFX10-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo11518; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1711519; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo11520; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v2011521; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1611522; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo11523; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1711524; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v1911525; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo11526; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1811527; GFX10-NEXT: v_perm_b32 v1, v50, v1, 0x504010011528; GFX10-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo11529; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1611530; GFX10-NEXT: v_perm_b32 v0, v52, v0, 0x504010011531; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo11532; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2111533; GFX10-NEXT: v_perm_b32 v2, v48, v2, 0x504010011534; GFX10-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo11535; GFX10-NEXT: v_perm_b32 v4, v15, v4, 0x504010011536; GFX10-NEXT: v_perm_b32 v15, v49, v51, 0x504010011537; GFX10-NEXT: s_setpc_b64 s[30:31]11538;11539; GFX11-TRUE16-LABEL: v_maximumnum_v32bf16:11540; GFX11-TRUE16: ; %bb.0:11541; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11542; GFX11-TRUE16-NEXT: scratch_load_b32 v68, off, s3211543; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v1511544; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, 011545; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v1411546; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v3011547; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v2911548; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v3111549; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v36.l11550; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.l, v36.l11551; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v3311552; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v1311553; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v3411554; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v36.l11555; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v1211556; GFX11-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v2811557; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v1111558; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v2711559; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v2611560; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v2511561; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v39, v3911562; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v36.l11563; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v4911564; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v1011565; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v50, v5011566; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v911567; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v51, v5111568; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v811569; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v2411570; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v2311571; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v2211572; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v2111573; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v2011574; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v52, v5211575; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v711576; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v53, v5311577; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v611578; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v54, v5411579; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v511580; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v55, v5511581; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v411582; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v64, v6411583; GFX11-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v311584; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v1911585; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v1811586; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v1711587; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v1611588; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l11589; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v65, v6511590; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v211591; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v66, v6611592; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v111593; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v67, v6711594; GFX11-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v011595; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v8111596; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1511597; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v3011598; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v211599; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v011600; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v1711601; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v1611602; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v83, v8311603; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v36.l11604; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v86, v8611605; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v36.l11606; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)11607; GFX11-TRUE16-NEXT: v_cndmask_b16 v96.h, v0.l, v16.l, s4211608; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s43, 0, v96.h11609; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)11610; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v6811611; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v15.h, v68.h, vcc_lo11612; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11613; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v3111614; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h11615; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v68.h, v36.h, vcc_lo11616; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)11617; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v3511618; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s42, 0, v35.h11619; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v35.h, v36.h, vcc_lo11620; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v31.l, v36.h, s011621; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v31.l11622; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v3211623; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11624; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3611625; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v14.h, v30.h, s011626; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11627; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v30.h, v36.h, s111628; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v36.h11629; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v36, v3711630; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s44, 0, v37.h11631; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)11632; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v37.h, v36.h, s011633; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.l, v36.h, s111634; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v32.l11635; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v3311636; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11637; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3611638; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v13.h, v29.h, s111639; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11640; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v29.h, v36.h, s211641; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.h11642; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v36, v3811643; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11644; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v38.h, v36.h, s111645; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.l, v36.h, s211646; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v33.l11647; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v3411648; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11649; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3611650; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v12.h, v28.h, s211651; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11652; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v28.h, v36.h, s311653; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v36.h11654; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v36, v3911655; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11656; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v39.h, v36.h, s211657; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v34.l, v36.h, s311658; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v34.l11659; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v4811660; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v36.l11661; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11662; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v3611663; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v11.h, v27.h, s311664; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11665; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v27.h, v36.h, s411666; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v36.h11667; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v36, v4811668; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11669; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v48.h, v36.h, s311670; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v35.l, v36.h, s411671; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v35.l11672; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v4911673; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v36.l11674; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11675; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v3611676; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v10.h, v26.h, s411677; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11678; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v26.h, v36.h, s511679; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v36.h11680; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v36, v4911681; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11682; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v49.h, v36.h, s411683; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v38.l, v36.h, s511684; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v38.l11685; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v50, v5011686; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v36.l11687; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11688; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v3611689; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v9.h, v25.h, s511690; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11691; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.h, v25.h, v36.h, s611692; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v36.h11693; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v36, v5011694; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11695; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v50.h, v36.h, s511696; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v48.l, v36.h, s611697; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v48.l11698; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v51, v5111699; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v36.l11700; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11701; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v3611702; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v8.h, v24.h, s611703; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11704; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.h, v24.h, v36.h, s711705; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v36.h11706; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v36, v5111707; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11708; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v51.h, v36.h, s611709; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v50.l, v36.h, s711710; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v50.l11711; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v52, v5211712; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v36.l11713; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11714; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v3611715; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v7.h, v23.h, s711716; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11717; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.h, v23.h, v36.h, s811718; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v36.h11719; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s7, v36, v5211720; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11721; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.h, v36.h, s711722; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v52.l, v36.h, s811723; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v52.l11724; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v53, v5311725; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v36.l11726; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11727; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v3611728; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v6.h, v22.h, s811729; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11730; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.h, v22.h, v36.h, s911731; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v36.h11732; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s8, v36, v5311733; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11734; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.h, v36.h, s811735; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.h, v53.l, v36.h, s911736; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v53.l11737; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v54, v5411738; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v36.l11739; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11740; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v3611741; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v5.h, v21.h, s911742; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11743; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.h, v21.h, v36.h, s1011744; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v36.h11745; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s9, v36, v5411746; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11747; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.h, v36.h, s911748; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v54.l, v36.h, s1011749; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v54.l11750; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v55, v5511751; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v36.l11752; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11753; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v3611754; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v4.h, v20.h, s1011755; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11756; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.h, v20.h, v36.h, s1111757; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v36.h11758; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s10, v36, v5511759; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11760; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.h, v36.h, s1011761; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.h, v55.l, v36.h, s1111762; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v55.l11763; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v64, v6411764; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v36.l11765; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11766; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v3611767; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v3.h, v19.h, s1111768; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11769; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.h, v19.h, v36.h, s1211770; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v36.h11771; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s11, v36, v6411772; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11773; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.h, v36.h, s1111774; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v64.l, v36.h, s1211775; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v64.l11776; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v65, v6511777; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v36.l11778; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11779; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v3611780; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v2.h, v18.h, s1211781; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11782; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.h, v18.h, v36.h, s1311783; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v36.h11784; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s12, v36, v6511785; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11786; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.h, v36.h, s1211787; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.h, v65.l, v36.h, s1311788; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v65.l11789; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v66, v6611790; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v36.l11791; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11792; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v3611793; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v1.h, v17.h, s1311794; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11795; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.h, v17.h, v36.h, s1411796; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v36.h11797; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s13, v36, v6611798; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11799; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.h, v36.h, s1311800; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v66.l, v36.h, s1411801; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v66.l11802; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v67, v6711803; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v36.l11804; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11805; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v3611806; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v0.h, v16.h, s1411807; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)11808; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.h, v16.h, v36.h, s1511809; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v8111810; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v36.h11811; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6811812; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s14, v36, v6711813; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)11814; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.h, v15.l, v68.l, s1511815; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v8111816; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1411817; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)11818; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.h, v36.h, s1411819; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v67.l, v36.h, s1611820; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v67.l11821; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v82.h11822; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)11823; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v3611824; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v68.l, v82.h, s1511825; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v82, v3611826; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11827; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v36.h, v82.h, s1511828; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v36.h11829; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v68.l, v82.h, s1611830; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v81, v8111831; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1311832; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2911833; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)11834; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v14.h, v36.h, s1511835; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v68.l11836; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v14.l, v30.l, s1611837; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v36.l11838; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v82, v8211839; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2811840; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v3611841; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v30.l, v14.h, s1711842; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v14.h11843; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)11844; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v82, v8211845; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2711846; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v14, v3611847; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11848; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v82, v8211849; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v36.h, v14.h, s1611850; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v36.h11851; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2611852; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)11853; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v14.l, v14.h, s1711854; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v81, v8111855; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1211856; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v82, v8211857; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2511858; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v13.h, v36.h, s1611859; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v14.l11860; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.l, v29.l, s1711861; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v36.l11862; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v82, v8211863; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2411864; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v3611865; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v29.l, v13.h, s1811866; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v13.h11867; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)11868; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v82, v8211869; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2311870; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v13, v3611871; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v29.h, s1611872; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11873; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v82, v8211874; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v36.h, v13.h, s1711875; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v36.h11876; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2211877; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)11878; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v13.l, v13.h, s1811879; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v81, v8111880; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1111881; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v8211882; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2111883; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.h, v12.h, v36.h, s1711884; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v13.l11885; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.l, v28.l, s1811886; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v36.l11887; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v8211888; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2011889; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v3611890; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v28.l, v12.h, s1911891; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v12.h11892; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)11893; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v82, v8211894; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v1911895; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v12, v3611896; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v28.h, s1711897; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11898; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v82, v8211899; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v36.h, v12.h, s1811900; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v36.h11901; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l11902; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)11903; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v12.l, v12.h, s1911904; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v81, v8111905; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1011906; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v36.h, s1811907; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v12.l11908; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11909; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.l, v27.l, s1911910; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l11911; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v3611912; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11913; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v27.l, v11.h, s2011914; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v11.h11915; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v27.h, s1811916; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11917; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v11, v3611918; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v36.h, v11.h, s1911919; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v36.h11920; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11921; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v11.l, v11.h, s2011922; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v81, v8111923; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v911924; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.h, v10.h, v36.h, s1911925; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v11.l11926; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11927; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.l, v26.l, s2011928; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v36.l11929; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v3611930; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11931; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v26.l, v10.h, s2111932; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v10.h11933; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v26.h, s1911934; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11935; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v10, v3611936; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v36.h, v10.h, s2011937; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v36.h11938; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11939; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v10.l, v10.h, s2111940; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v81, v8111941; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v811942; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.h, v9.h, v36.h, s2011943; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v10.l11944; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11945; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v25.l, s2111946; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v36.l11947; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v3611948; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11949; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v25.l, v9.h, s2211950; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v9.h11951; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v25.h, s2011952; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11953; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v9, v3611954; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v36.h, v9.h, s2111955; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v36.h11956; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11957; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v9.h, s2211958; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v81, v8111959; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v711960; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.h, v8.h, v36.h, s2111961; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v9.l11962; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11963; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.l, v24.l, s2211964; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v36.l11965; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v3611966; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11967; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v24.l, v8.h, s2311968; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v8.h11969; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v24.h, s2111970; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11971; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v8, v3611972; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v36.h, v8.h, s2211973; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v36.h11974; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11975; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v8.h, s2311976; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v81, v8111977; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v611978; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.h, v7.h, v36.h, s2211979; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v8.l11980; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11981; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v23.l, s2311982; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v36.l11983; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v3611984; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11985; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v23.l, v7.h, s2411986; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v7.h11987; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v23.h, s2211988; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11989; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v7, v3611990; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v36.h, v7.h, s2311991; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v36.h11992; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11993; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s2411994; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v8111995; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v511996; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.h, v6.h, v36.h, s2311997; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v7.l11998; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11999; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v22.l, s2412000; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v36.l12001; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v3612002; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12003; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v22.l, v6.h, s2512004; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v6.h12005; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v22.h, s2312006; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12007; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v6, v3612008; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v36.h, v6.h, s2412009; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v36.h12010; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12011; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s2512012; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v8112013; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v412014; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.h, v5.h, v36.h, s2412015; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v6.l12016; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12017; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.l, v21.l, s2512018; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v36.l12019; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v3612020; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12021; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v21.l, v5.h, s2612022; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v5.h12023; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v21.h, s2412024; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12025; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v5, v3612026; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v36.h, v5.h, s2512027; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v36.h12028; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12029; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s2612030; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v81, v8112031; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v312032; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v4.h, v36.h, s2512033; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v5.l12034; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12035; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v20.l, s2612036; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v36.l12037; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v3612038; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12039; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v20.l, v4.h, s2712040; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0, v4.h12041; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v20.h, s2512042; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12043; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v4, v3612044; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v36.h, v4.h, s2612045; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v36.h12046; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12047; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s2712048; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v81, v8112049; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1812050; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v3.h, v36.h, s2612051; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v4.l12052; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)12053; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.h, v3.l, v19.l, s2712054; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v112055; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v81, v8112056; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v3612057; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)12058; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v19.l, v83.h, s2812059; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v8412060; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v3, v312061; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0, v83.h12062; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v36.l12063; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v83, v3612064; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.h, v2.l, v18.l, s2812065; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v36.h12066; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v1.l, v17.l, s4012067; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v32.h, v37.h, s4412068; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v36.h, v83.h, s2712069; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s40, 0, v82.h12070; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v85, v8512071; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v18.h, s2612072; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v32.l, v1.l, s012073; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v83.h, s4112074; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v8712075; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)12076; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v36.h, s2812077; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v3.l12078; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v31.h, v35.h, s4212079; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s42, 0, v39.h12080; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v19.h12081; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s45, 0, v3612082; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v18.l, v82.h, s2912083; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0, v38.h12084; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v31.l, v0.h, vcc_lo12085; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v34.h, v39.h, s4212086; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48.h12087; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v82, v3612088; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v33.h, v38.h, s2912089; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h12090; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v34.l, v1.h, s212091; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v37.l, v48.h, vcc_lo12092; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v36.h, v82.h, s4412093; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v33.l, v0.h, s112094; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49.h12095; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v50.h12096; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v35.l, v1.h, s312097; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v82.h, s4012098; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v51.h12099; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v54.h12100; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v49.l, v50.h, s112101; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s4512102; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v36.h, s012103; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v1.l12104; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v39.l, v49.h, vcc_lo12105; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v52.h12106; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v51.l, v51.h, s212107; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v53.h12108; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3612109; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v17.l, v19.h, s2712110; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v38.l, v0.h, s412111; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v69.l, v52.h, s012112; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v55.h12113; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.h, v48.l, v1.h, s512114; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v3612115; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h12116; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v69.h, v53.h, s212117; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v70.h, v55.h, s412118; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v66.h12119; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v36.h, v19.h, s112120; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v65.h12121; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v50.l, v2.h, s612122; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v70.l, v54.h, s312123; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v52.l, v0.h, s712124; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v16.h, v19.h, s2812125; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v53.l, v1.h, s812126; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v71.h, v65.h, s112127; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v54.l, v2.h, s912128; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v67.h12129; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v36.h, s012130; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.h12131; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v64.h12132; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v65.l, v1.h, s1212133; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v67.h, s312134; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v55.l, v3.h, s1012135; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v3612136; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v16.l, v96.h, s4112137; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v71.l, v64.h, s012138; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v80.l, v66.h, s212139; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v2.l, vcc_lo12140; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v17.l, s412141; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v3612142; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v64.l, v0.h, s1112143; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v66.l, v16.l, s1312144; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v67.l, v15.l, s1412145; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v68.l, v30.h, s1512146; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v36.h, v96.h, s012147; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h12148; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)12149; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.h, v16.l, v96.h, s4312150; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.h, v17.h, v36.h, s012151; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.l12152; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12153; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3612154; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v17.h, s012155; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]12156;12157; GFX11-FAKE16-LABEL: v_maximumnum_v32bf16:12158; GFX11-FAKE16: ; %bb.0:12159; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12160; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2512161; GFX11-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v1212162; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2812163; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v1212164; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2912165; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1312166; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v5012167; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3012168; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v1412169; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2412170; GFX11-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v912171; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s112172; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v1312173; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v912174; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v2112175; GFX11-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v812176; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v812177; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v3812178; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v2312179; GFX11-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v712180; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v712181; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v2212182; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s012183; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v1412184; GFX11-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v612185; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v612186; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v2012187; GFX11-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v512188; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v3412189; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v3012190; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v512191; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v1912192; GFX11-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v412193; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo12194; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v7012195; GFX11-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v2912196; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v412197; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v1812198; GFX11-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v312199; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo12200; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v8212201; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v2812202; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v312203; GFX11-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v212204; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v212205; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo12206; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v8612207; GFX11-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v2612208; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v1712209; GFX11-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v112210; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2712211; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo12212; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v9812213; GFX11-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2512214; GFX11-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v1112215; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v112216; GFX11-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v012217; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo12218; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v10212219; GFX11-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v2412220; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v1612221; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v012222; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v5412223; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo12224; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v11412225; GFX11-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v2212226; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v1412227; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v1112228; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2612229; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo12230; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v11812231; GFX11-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v2112232; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s212233; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v1012234; GFX11-FAKE16-NEXT: scratch_load_b32 v31, off, s3212235; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo12236; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v13012237; GFX11-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v2012238; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v1512239; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo12240; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v13412241; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v102, v144, v135 :: v_dual_and_b32 v133, 0xffff0000, v1812242; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v14612243; GFX11-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v1712244; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v9612245; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo12246; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v5412247; GFX11-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v2712248; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v54, v14, v30 :: v_dual_and_b32 v97, 0xffff0000, v2312249; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v3712250; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v1512251; GFX11-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v1912252; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo12253; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v4912254; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo12255; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v5312256; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo12257; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6512258; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v10012259; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)12260; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v55, v55, v64 :: v_dual_lshlrev_b32 v130, 16, v5112261; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v6912262; GFX11-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v1012263; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v3412264; GFX11-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v6612265; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12266; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s312267; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo12268; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v8112269; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v6812270; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v8012271; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)12272; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6712273; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v8512274; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo12275; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v9712276; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v3012277; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v8412278; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)12279; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v8312280; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v10112281; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v1612282; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo12283; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v11312284; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9912285; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v11712286; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v3612287; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo12288; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v12912289; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v8212290; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)12291; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v115, v119, v98 :: v_dual_lshlrev_b32 v146, 16, v11312292; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v13312293; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v4812294; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo12295; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v14512296; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v8612297; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo12298; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v3812299; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v147, v34 :: v_dual_lshlrev_b32 v49, 16, v5212300; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v6612301; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)12302; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v49, v13012303; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v66, v30, v54 :: v_dual_lshlrev_b32 v53, 16, v6412304; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v3512305; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v3012306; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v7012307; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11712308; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v130, v35, v36 :: v_dual_lshlrev_b32 v129, 16, v3912309; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)12310; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v37, v12912311; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v129, v51, v52, s012312; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v37, v39, v48 :: v_dual_lshlrev_b32 v118, 16, v10212313; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v5512314; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v13112315; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v50, 16, v1512316; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v7112317; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v13212318; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo12319; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12320; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v13312321; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v8712322; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6512323; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v13412324; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo12325; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)12326; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v13512327; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v10312328; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v82, vcc_lo12329; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v97, v14412330; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v9812331; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v101, v14512332; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v11512333; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)12334; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9712335; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v14612336; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v96, vcc_lo12337; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v114, v14712338; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11912339; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v3812340; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo12341; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v116, v1412342; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo12343; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v118, v3012344; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo12345; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v128, v4912346; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v128, v38, v34, vcc_lo12347; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3612348; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v36, vcc_lo12349; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4812350; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v37, v48, vcc_lo12351; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5212352; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v129, v52, vcc_lo12353; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6412354; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v12912355; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo12356; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6812357; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo12358; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7012359; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo12360; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8012361; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo12362; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8212363; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo12364; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8412365; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo12366; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8612367; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo12368; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9612369; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo12370; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9812371; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v5312372; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10012373; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v133, 16, v6912374; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3512375; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v135, 16, v8512376; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10212377; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo12378; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3912379; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v36, v36, v39 :: v_dual_lshlrev_b32 v145, 16, v10112380; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3412381; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v128, v34, vcc_lo12382; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5112383; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v51, vcc_lo12384; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5512385; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12812386; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v64, v55, vcc_lo12387; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6712388; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo12389; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7112390; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v147, 16, v11412391; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8312392; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo12393; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8712394; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo12395; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9912396; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo12397; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10312398; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v71, v86, v103 :: v_dual_lshlrev_b32 v30, 16, v13012399; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11312400; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v3712401; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo12402; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11512403; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo12404; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11712405; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v8112406; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo12407; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11912408; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo12409; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3812410; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v86, v34, v38, vcc_lo12411; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3012412; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v14, vcc_lo12413; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4812414; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v36, vcc_lo12415; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5212416; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)12417; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3112418; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v129, v39, vcc_lo12419; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13112420; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v49, vcc_lo12421; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13212422; GFX11-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v3112423; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo12424; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13312425; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo12426; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13412427; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo12428; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13512429; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo12430; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14412431; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo12432; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14512433; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo12434; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v5012435; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v15, v31, vcc_lo12436; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v3212437; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v3112438; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v11612439; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)12440; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v5512441; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo12442; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v11212443; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v3312444; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)12445; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14612446; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo12447; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v5312448; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v52, v33, vcc_lo12449; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v3212450; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v11812451; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)12452; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v31, v55 :: v_dual_lshlrev_b32 v64, 16, v5212453; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14712454; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v5312455; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo12456; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14812457; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo12458; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v6412459; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v64, v52, v33, vcc_lo12460; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v6712461; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)12462; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v6412463; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v65, v53, v55, vcc_lo12464; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10212465; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v6512466; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo12467; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3312468; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo12469; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5512470; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v55, vcc_lo12471; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5212472; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)12473; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo12474; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5312475; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc_lo12476; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6712477; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v1312478; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo12479; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5112480; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo12481; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6812482; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v53, vcc_lo12483; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5512484; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v6612485; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2912486; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v1212487; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v64, 16, v5412488; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)12489; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v5312490; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v54, vcc_lo12491; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6512492; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v1312493; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo12494; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5512495; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v2812496; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)12497; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v2912498; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo12499; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5412500; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v53, v54, vcc_lo12501; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5512502; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo12503; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6612504; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)12505; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v66, vcc_lo12506; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v6412507; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v5312508; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2812509; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v55, v29, v13 :: v_dual_lshlrev_b32 v66, 16, v1212510; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1312511; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)12512; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo12513; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6412514; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v5512515; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v6512516; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2712517; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x504010012518; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo12519; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2912520; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo12521; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v1112522; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1212523; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo12524; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)12525; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2912526; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v1012527; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo12528; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2812529; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo12530; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6512531; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)12532; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v5412533; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6412534; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo12535; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2812536; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v2612537; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)12538; GFX11-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x504010012539; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo12540; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2912541; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v1112542; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v912543; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2712544; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)12545; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v2812546; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo12547; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5512548; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo12549; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2912550; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v2512551; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo12552; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1112553; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v2612554; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)12555; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2912556; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo12557; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2712558; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)12559; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo12560; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v2812561; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v1012562; GFX11-FAKE16-NEXT: v_perm_b32 v12, v34, v12, 0x504010012563; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v5412564; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v2512565; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v912566; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo12567; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2712568; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo12569; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1012570; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)12571; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2912572; GFX11-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x504010012573; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo12574; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v5412575; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo12576; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2612577; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)12578; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo12579; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v912580; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo12581; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2812582; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2312583; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo12584; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2512585; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v26, 16, v812586; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v712587; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)12588; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v2612589; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo12590; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2512591; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2712592; GFX11-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x504010012593; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v2412594; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)12595; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v712596; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v2612597; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo12598; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v2812599; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12600; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v2412601; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2512602; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v612603; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v2312604; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)12605; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2512606; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v812607; GFX11-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x504010012608; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo12609; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)12610; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v2612611; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v8 :: v_dual_lshlrev_b32 v25, 16, v2212612; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v2812613; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo12614; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2512615; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo12616; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v812617; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo12618; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v712619; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo12620; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2412621; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)12622; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo12623; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2312624; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v2612625; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2212626; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v612627; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)12628; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v2512629; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2712630; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo12631; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2412632; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v512633; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo12634; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v612635; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo12636; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2512637; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2112638; GFX11-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x504010012639; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo12640; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2212641; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)12642; GFX11-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x504010012643; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo12644; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v2412645; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v412646; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2312647; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2212648; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2012649; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo12650; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2512651; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v312652; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v512653; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo12654; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v2412655; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)12656; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2112657; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo12658; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v2212659; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo12660; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v2312661; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo12662; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2412663; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)12664; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2012665; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v412666; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x504010012667; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v1912668; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v2212669; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo12670; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v512671; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)12672; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo12673; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2412674; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v312675; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1912676; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo12677; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2112678; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo12679; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v412680; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)12681; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v22, v4 :: v_dual_lshlrev_b32 v21, 16, v2312682; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2412683; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo12684; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2112685; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v2212686; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo12687; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2012688; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)12689; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x504010012690; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo12691; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v312692; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo12693; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1912694; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v20, 16, v212695; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v1812696; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)12697; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2012698; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v18 :: v_dual_lshlrev_b32 v23, 16, v2412699; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2312700; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo12701; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v1912702; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v012703; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)12704; GFX11-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x504010012705; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo12706; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v112707; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2012708; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo12709; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v2312710; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v1712711; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12712; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v112713; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo12714; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v1912715; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v1 :: v_dual_lshlrev_b32 v20, 16, v1612716; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v212717; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)12718; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2012719; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v0 :: v_dual_lshlrev_b32 v19, 16, v1812720; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1712721; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)12722; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v1912723; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo12724; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v2012725; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo12726; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v212727; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)12728; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_lshlrev_b32 v23, 16, v1612729; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v012730; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2312731; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo12732; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v112733; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo12734; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1812735; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo12736; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v012737; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo12738; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1712739; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo12740; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2012741; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1612742; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo12743; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)12744; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1712745; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2312746; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v1912747; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1812748; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)12749; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x504010012750; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo12751; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1612752; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)12753; GFX11-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x504010012754; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo12755; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2112756; GFX11-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x504010012757; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo12758; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)12759; GFX11-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x504010012760; GFX11-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x504010012761; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]12762;12763; GFX12-TRUE16-LABEL: v_maximumnum_v32bf16:12764; GFX12-TRUE16: ; %bb.0:12765; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x012766; GFX12-TRUE16-NEXT: s_wait_expcnt 0x012767; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x012768; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x012769; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x012770; GFX12-TRUE16-NEXT: scratch_load_b32 v68, off, s3212771; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v1512772; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.l, 012773; GFX12-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v1412774; GFX12-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v3012775; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v2912776; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v3112777; GFX12-TRUE16-NEXT: v_mov_b16_e32 v35.l, v36.l12778; GFX12-TRUE16-NEXT: v_mov_b16_e32 v37.l, v36.l12779; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v3312780; GFX12-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v1312781; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v3412782; GFX12-TRUE16-NEXT: v_mov_b16_e32 v38.l, v36.l12783; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v1212784; GFX12-TRUE16-NEXT: v_and_b32_e32 v39, 0xffff0000, v2812785; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v1112786; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v2712787; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v2612788; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v2512789; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v39, v3912790; GFX12-TRUE16-NEXT: v_mov_b16_e32 v39.l, v36.l12791; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v4912792; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v1012793; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v50, v5012794; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v912795; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v51, v5112796; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v812797; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v2412798; GFX12-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v2312799; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v2212800; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v2112801; GFX12-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v2012802; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v52, v5212803; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v712804; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v53, v5312805; GFX12-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v612806; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v54, v5412807; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v512808; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v55, v5512809; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v412810; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v64, v6412811; GFX12-TRUE16-NEXT: v_and_b32_e32 v64, 0xffff0000, v312812; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v1912813; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v1812814; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v1712815; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v1612816; GFX12-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l12817; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v65, v6512818; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v212819; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v66, v6612820; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v112821; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v67, v6712822; GFX12-TRUE16-NEXT: v_and_b32_e32 v67, 0xffff0000, v012823; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v8112824; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1512825; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v83, 16, v3012826; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v212827; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v012828; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v1712829; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v1612830; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v83, v8312831; GFX12-TRUE16-NEXT: v_mov_b16_e32 v83.l, v36.l12832; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v86, v8612833; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v36.l12834; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12835; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)12836; GFX12-TRUE16-NEXT: v_cndmask_b16 v96.h, v0.l, v16.l, s4212837; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s43, 0, v96.h12838; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x012839; GFX12-TRUE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v6812840; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)12841; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v15.h, v68.h, vcc_lo12842; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)12843; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v3112844; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h12845; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)12846; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v68.h, v36.h, vcc_lo12847; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)12848; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v3512849; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s42, 0, v35.h12850; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)12851; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v35.h, v36.h, vcc_lo12852; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12853; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v31.l, v36.h, s012854; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v31.l12855; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v32, v3212856; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)12857; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3612858; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12859; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v14.h, v30.h, s012860; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12861; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v30.h, v36.h, s112862; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v36.h12863; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v36, v3712864; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s44, 0, v37.h12865; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12866; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)12867; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v37.h, v36.h, s012868; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v32.l, v36.h, s112869; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v32.l12870; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v33, v3312871; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)12872; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3612873; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12874; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v13.h, v29.h, s112875; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12876; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v29.h, v36.h, s212877; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.h12878; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v36, v3812879; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12880; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12881; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v38.h, v36.h, s112882; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v33.l, v36.h, s212883; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v33.l12884; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v34, v3412885; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)12886; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3612887; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12888; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v12.h, v28.h, s212889; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12890; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v28.h, v36.h, s312891; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v36.h12892; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v36, v3912893; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12894; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12895; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v39.h, v36.h, s212896; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v34.l, v36.h, s312897; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v34.l12898; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v4812899; GFX12-TRUE16-NEXT: v_mov_b16_e32 v48.l, v36.l12900; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12901; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v3612902; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12903; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v11.h, v27.h, s312904; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12905; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v27.h, v36.h, s412906; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v36.h12907; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v36, v4812908; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12909; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12910; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v48.h, v36.h, s312911; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v35.l, v36.h, s412912; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v35.l12913; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v4912914; GFX12-TRUE16-NEXT: v_mov_b16_e32 v49.l, v36.l12915; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12916; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v3612917; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12918; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v10.h, v26.h, s412919; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12920; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v26.h, v36.h, s512921; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v36.h12922; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s4, v36, v4912923; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12924; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12925; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v49.h, v36.h, s412926; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v38.l, v36.h, s512927; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v38.l12928; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v50, v5012929; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v36.l12930; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12931; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v3612932; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12933; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v9.h, v25.h, s512934; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12935; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.h, v25.h, v36.h, s612936; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v36.h12937; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s5, v36, v5012938; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12939; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12940; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v50.h, v36.h, s512941; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v48.l, v36.h, s612942; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v48.l12943; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v51, v5112944; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v36.l12945; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12946; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v3612947; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12948; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v8.h, v24.h, s612949; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12950; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.h, v24.h, v36.h, s712951; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v36.h12952; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s6, v36, v5112953; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12954; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12955; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v51.h, v36.h, s612956; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v50.l, v36.h, s712957; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v50.l12958; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v52, v5212959; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v36.l12960; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12961; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v3612962; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12963; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v7.h, v23.h, s712964; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12965; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.h, v23.h, v36.h, s812966; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v36.h12967; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s7, v36, v5212968; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12969; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12970; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v52.h, v36.h, s712971; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v52.l, v36.h, s812972; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v52.l12973; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v53, v5312974; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v36.l12975; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12976; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s7, 0, v3612977; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12978; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v6.h, v22.h, s812979; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12980; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.h, v22.h, v36.h, s912981; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v36.h12982; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s8, v36, v5312983; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12984; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12985; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v53.h, v36.h, s812986; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.h, v53.l, v36.h, s912987; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v53.l12988; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v54, v5412989; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v36.l12990; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12991; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s8, 0, v3612992; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12993; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v5.h, v21.h, s912994; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12995; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.h, v21.h, v36.h, s1012996; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v36.h12997; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s9, v36, v5412998; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)12999; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13000; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v54.h, v36.h, s913001; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v54.l, v36.h, s1013002; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v54.l13003; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v55, v5513004; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v36.l13005; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13006; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s9, 0, v3613007; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13008; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v4.h, v20.h, s1013009; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13010; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.h, v20.h, v36.h, s1113011; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v36.h13012; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s10, v36, v5513013; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13014; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13015; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v55.h, v36.h, s1013016; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.h, v55.l, v36.h, s1113017; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v55.l13018; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v64, v6413019; GFX12-TRUE16-NEXT: v_mov_b16_e32 v64.l, v36.l13020; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13021; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s10, 0, v3613022; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13023; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v3.h, v19.h, s1113024; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13025; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.h, v19.h, v36.h, s1213026; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v36.h13027; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s11, v36, v6413028; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13029; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13030; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v64.h, v36.h, s1113031; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v64.l, v36.h, s1213032; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v64.l13033; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v65, v6513034; GFX12-TRUE16-NEXT: v_mov_b16_e32 v65.l, v36.l13035; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13036; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s11, 0, v3613037; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13038; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v2.h, v18.h, s1213039; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13040; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.h, v18.h, v36.h, s1313041; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v36.h13042; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s12, v36, v6513043; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13044; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13045; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.h, v36.h, s1213046; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.h, v65.l, v36.h, s1313047; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v65.l13048; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v66, v6613049; GFX12-TRUE16-NEXT: v_mov_b16_e32 v66.l, v36.l13050; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13051; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s12, 0, v3613052; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13053; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v1.h, v17.h, s1313054; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13055; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.h, v17.h, v36.h, s1413056; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v36.h13057; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s13, v36, v6613058; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13059; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13060; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.h, v36.h, s1313061; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v66.l, v36.h, s1413062; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v66.l13063; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v67, v6713064; GFX12-TRUE16-NEXT: v_mov_b16_e32 v67.l, v36.l13065; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13066; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s13, 0, v3613067; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13068; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v0.h, v16.h, s1413069; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)13070; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.h, v16.h, v36.h, s1513071; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v8113072; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v36.h13073; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v6813074; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s14, v36, v6713075; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13076; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.h, v15.l, v68.l, s1513077; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)13078; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v81, v8113079; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1413080; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.h, v36.h, s1413081; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v67.l, v36.h, s1613082; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v67.l13083; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v82.h13084; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)13085; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s14, 0, v3613086; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13087; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v68.l, v82.h, s1513088; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v82, v3613089; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13090; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13091; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v36.h, v82.h, s1513092; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v36.h13093; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v68.l, v82.h, s1613094; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v81, v8113095; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1313096; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2913097; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13098; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v14.h, v36.h, s1513099; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v68.l13100; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v14.l, v30.l, s1613101; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v36.l13102; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v82, v8213103; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2813104; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v3613105; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v30.l, v14.h, s1713106; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v14.h13107; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)13108; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v82, v8213109; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2713110; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v14, v3613111; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)13112; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v82, v8213113; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13114; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v36.h, v14.h, s1613115; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v36.h13116; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2613117; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)13118; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v14.l, v14.h, s1713119; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v81, v8113120; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1213121; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v82, v8213122; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2513123; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13124; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v13.h, v36.h, s1613125; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v14.l13126; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v13.l, v29.l, s1713127; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v36.l13128; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v82, v8213129; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2413130; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v3613131; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v29.l, v13.h, s1813132; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v13.h13133; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)13134; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v82, v8213135; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2313136; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v13, v3613137; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13138; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v29.h, s1613139; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13140; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v82, v8213141; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v36.h, v13.h, s1713142; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 0, v36.h13143; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2213144; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)13145; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v13.l, v13.h, s1813146; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v81, v8113147; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1113148; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v82, v8213149; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2113150; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13151; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v12.h, v36.h, s1713152; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v13.l13153; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v12.l, v28.l, s1813154; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v36.l13155; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v82, v8213156; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v2013157; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v3613158; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v28.l, v12.h, s1913159; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v12.h13160; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)13161; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v82, v8213162; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v1913163; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v12, v3613164; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13165; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v28.h, s1713166; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13167; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v82, v8213168; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v36.h, v12.h, s1813169; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 0, v36.h13170; GFX12-TRUE16-NEXT: v_mov_b16_e32 v82.l, v36.l13171; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13172; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v12.l, v12.h, s1913173; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v81, v8113174; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1013175; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13176; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v11.h, v36.h, s1813177; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v12.l13178; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v11.l, v27.l, s1913179; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v36.l13180; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13181; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v3613182; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v27.l, v11.h, s2013183; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v11.h13184; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13185; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13186; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v27.h, s1813187; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v11, v3613188; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13189; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13190; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v36.h, v11.h, s1913191; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 0, v36.h13192; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v11.l, v11.h, s2013193; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v81, v8113194; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v913195; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13196; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13197; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.h, v10.h, v36.h, s1913198; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v11.l13199; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v10.l, v26.l, s2013200; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v36.l13201; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v3613202; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13203; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v26.l, v10.h, s2113204; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v10.h13205; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13206; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v26.h, s1913207; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13208; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v10, v3613209; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13210; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v36.h, v10.h, s2013211; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 0, v36.h13212; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13213; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v10.l, v10.h, s2113214; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v81, v8113215; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v813216; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13217; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.h, v9.h, v36.h, s2013218; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v10.l13219; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v9.l, v25.l, s2113220; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v36.l13221; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13222; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v3613223; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v25.l, v9.h, s2213224; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v9.h13225; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13226; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13227; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v25.h, s2013228; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v9, v3613229; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13230; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13231; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v36.h, v9.h, s2113232; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 0, v36.h13233; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v9.h, s2213234; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v81, v8113235; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v713236; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13237; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13238; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.h, v8.h, v36.h, s2113239; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v9.l13240; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v8.l, v24.l, s2213241; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v36.l13242; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v3613243; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13244; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v24.l, v8.h, s2313245; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v8.h13246; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13247; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v24.h, s2113248; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13249; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v8, v3613250; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13251; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v36.h, v8.h, s2213252; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 0, v36.h13253; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13254; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v8.l, v8.h, s2313255; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v81, v8113256; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v613257; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13258; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.h, v7.h, v36.h, s2213259; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v8.l13260; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v23.l, s2313261; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v36.l13262; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13263; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v3613264; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v23.l, v7.h, s2413265; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v7.h13266; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13267; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13268; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v23.h, s2213269; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v7, v3613270; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13271; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13272; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v36.h, v7.h, s2313273; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 0, v36.h13274; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v7.h, s2413275; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v81, v8113276; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v513277; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13278; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13279; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.h, v6.h, v36.h, s2313280; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v7.l13281; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v6.l, v22.l, s2413282; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v36.l13283; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v3613284; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13285; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v22.l, v6.h, s2513286; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v6.h13287; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13288; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v22.h, s2313289; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13290; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v6, v3613291; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13292; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v36.h, v6.h, s2413293; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 0, v36.h13294; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13295; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v6.l, v6.h, s2513296; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v81, v8113297; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v413298; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13299; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.h, v5.h, v36.h, s2413300; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v6.l13301; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v5.l, v21.l, s2513302; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v36.l13303; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13304; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v3613305; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v21.l, v5.h, s2613306; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v5.h13307; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13308; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13309; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v21.h, s2413310; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v5, v3613311; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13312; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13313; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v36.h, v5.h, s2513314; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 0, v36.h13315; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v5.l, v5.h, s2613316; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v81, v8113317; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v313318; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13319; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13320; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v4.h, v36.h, s2513321; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v5.l13322; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v20.l, s2613323; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v36.l13324; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v3613325; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13326; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v20.l, v4.h, s2713327; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 0, v4.h13328; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13329; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v20.h, s2513330; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13331; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v4, v3613332; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13333; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v36.h, v4.h, s2613334; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 0, v36.h13335; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13336; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v4.l, v4.h, s2713337; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v81, v8113338; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v1813339; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13340; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v3.h, v36.h, s2613341; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v4.l13342; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.h, v3.l, v19.l, s2713343; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v113344; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v81, v8113345; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)13346; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v3613347; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v19.l, v83.h, s2813348; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v84, v8413349; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v3, v313350; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s41, 0, v83.h13351; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v36.l13352; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v83, v3613353; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13354; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.h, v2.l, v18.l, s2813355; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v36.h13356; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v1.l, v17.l, s4013357; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v32.h, v37.h, s4413358; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v36.h, v83.h, s2713359; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s40, 0, v82.h13360; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v85, v8513361; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v18.h, s2613362; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v32.l, v1.l, s013363; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, v83.h, s4113364; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v87, v8713365; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13366; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)13367; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.h, v36.h, s2813368; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v3.l13369; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v31.h, v35.h, s4213370; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s42, 0, v39.h13371; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 0, v19.h13372; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s45, 0, v3613373; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v18.l, v82.h, s2913374; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 0, v38.h13375; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)13376; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v31.l, v0.h, vcc_lo13377; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13378; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v34.h, v39.h, s4213379; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v48.h13380; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v82, v3613381; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v33.h, v38.h, s2913382; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h13383; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v34.l, v1.h, s213384; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)13385; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v37.l, v48.h, vcc_lo13386; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13387; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v36.h, v82.h, s4413388; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v33.l, v0.h, s113389; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v49.h13390; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v50.h13391; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v35.l, v1.h, s313392; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v82.h, s4013393; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v51.h13394; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v54.h13395; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13396; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v49.l, v50.h, s113397; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s4513398; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v36.h, s013399; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v1.l13400; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)13401; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v39.l, v49.h, vcc_lo13402; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v52.h13403; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v51.l, v51.h, s213404; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v53.h13405; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3613406; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v17.l, v19.h, s2713407; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v38.l, v0.h, s413408; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13409; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v69.l, v52.h, s013410; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v55.h13411; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.h, v48.l, v1.h, s513412; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v3613413; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h13414; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v69.h, v53.h, s213415; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13416; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v70.h, v55.h, s413417; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v66.h13418; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v36.h, v19.h, s113419; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v65.h13420; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v50.l, v2.h, s613421; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v70.l, v54.h, s313422; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v52.l, v0.h, s713423; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v16.h, v19.h, s2813424; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v53.l, v1.h, s813425; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13426; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v71.h, v65.h, s113427; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v54.l, v2.h, s913428; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v67.h13429; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v36.h, s013430; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.h13431; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v64.h13432; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v65.l, v1.h, s1213433; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13434; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v67.h, s313435; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v55.l, v3.h, s1013436; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v3613437; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v16.l, v96.h, s4113438; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v71.l, v64.h, s013439; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v80.l, v66.h, s213440; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)13441; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v1.l, v2.l, vcc_lo13442; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13443; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v16.h, v17.l, s413444; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v3613445; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v64.l, v0.h, s1113446; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v66.l, v16.l, s1313447; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v67.l, v15.l, s1413448; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v68.l, v30.h, s1513449; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13450; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v36.h, v96.h, s013451; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v36.h13452; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)13453; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v16.l, v96.h, s4313454; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13455; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v17.h, v36.h, s013456; GFX12-TRUE16-NEXT: v_mov_b16_e32 v36.h, v16.l13457; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)13458; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3613459; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)13460; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v16.l, v17.h, s013461; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]13462;13463; GFX12-FAKE16-LABEL: v_maximumnum_v32bf16:13464; GFX12-FAKE16: ; %bb.0:13465; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x013466; GFX12-FAKE16-NEXT: s_wait_expcnt 0x013467; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x013468; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x013469; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x013470; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2513471; GFX12-FAKE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v1213472; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2813473; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v1213474; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2913475; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1313476; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s1, v50, v5013477; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v3013478; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v1413479; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v2413480; GFX12-FAKE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v913481; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)13482; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v52, v52, v51, s113483; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v1313484; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v913485; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v2113486; GFX12-FAKE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v813487; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v813488; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s0, v38, v3813489; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v2313490; GFX12-FAKE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v713491; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v713492; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v2213493; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)13494; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v48, v48, v39, s013495; GFX12-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v1413496; GFX12-FAKE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v613497; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v613498; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v2013499; GFX12-FAKE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v513500; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v3413501; GFX12-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v3013502; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v513503; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v1913504; GFX12-FAKE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v413505; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13506; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v35, vcc_lo13507; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v7013508; GFX12-FAKE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v2913509; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v413510; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v1813511; GFX12-FAKE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v313512; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13513; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v80, v71, vcc_lo13514; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v82, v8213515; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v2813516; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v313517; GFX12-FAKE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v213518; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v213519; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13520; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v84, v83, vcc_lo13521; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v86, v8613522; GFX12-FAKE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v2613523; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v1713524; GFX12-FAKE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v113525; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2713526; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13527; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v96, v87, vcc_lo13528; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v9813529; GFX12-FAKE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v2513530; GFX12-FAKE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v1113531; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v113532; GFX12-FAKE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v013533; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13534; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v100, v99, vcc_lo13535; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v102, v10213536; GFX12-FAKE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v2413537; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v1613538; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v013539; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s2, v54, v5413540; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13541; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v112, v103, vcc_lo13542; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v114, v11413543; GFX12-FAKE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v2213544; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v1413545; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v1113546; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v2613547; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13548; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v116, v115, vcc_lo13549; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v118, v11813550; GFX12-FAKE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v2113551; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)13552; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v64, v64, v55, s213553; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v1013554; GFX12-FAKE16-NEXT: scratch_load_b32 v31, off, s3213555; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13556; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v98, v128, v119, vcc_lo13557; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v130, v13013558; GFX12-FAKE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v2013559; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v1513560; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13561; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v100, v132, v131, vcc_lo13562; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v134, v13413563; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13564; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v102, v144, v135 :: v_dual_and_b32 v133, 0xffff0000, v1813565; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v146, v14613566; GFX12-FAKE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v1713567; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v112, 16, v9613568; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13569; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v147, vcc_lo13570; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v54, v5413571; GFX12-FAKE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v2713572; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13573; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v54, v14, v30 :: v_dual_and_b32 v97, 0xffff0000, v2313574; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v3713575; GFX12-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v1513576; GFX12-FAKE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v1913577; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13578; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v35, v36, vcc_lo13579; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v4913580; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13581; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v48, vcc_lo13582; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v5313583; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13584; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v51, v52, vcc_lo13585; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6513586; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v116, 16, v10013587; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13588; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)13589; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v55, v55, v64 :: v_dual_lshlrev_b32 v130, 16, v5113590; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v69, v6913591; GFX12-FAKE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v1013592; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v128, 16, v3413593; GFX12-FAKE16-NEXT: v_cmp_u_f32_e64 s3, v66, v6613594; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)13595; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)13596; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v68, v68, v67, s313597; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13598; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v67, v68, vcc_lo13599; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v81, v8113600; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v6813601; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v81, 16, v8013602; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13603; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6713604; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v85, v8513605; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13606; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v83, v80, vcc_lo13607; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v9713608; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v66, 16, v3013609; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v97, 16, v8413610; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13611; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v8313612; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v101, v10113613; GFX12-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v1613614; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13615; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v99, v99, v84, vcc_lo13616; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v113, v11313617; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13618; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)13619; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9913620; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v117, v11713621; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v3613622; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13623; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v113, v115, v96, vcc_lo13624; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v129, v12913625; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v85, 16, v8213626; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13627; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)13628; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v115, v119, v98 :: v_dual_lshlrev_b32 v146, 16, v11313629; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v133, v13313630; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v4813631; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13632; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v117, v131, v100, vcc_lo13633; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v145, v14513634; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v101, 16, v8613635; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13636; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v119, v135, v102, vcc_lo13637; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v3813638; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13639; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v38, v147, v34 :: v_dual_lshlrev_b32 v49, 16, v5213640; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v66, v6613641; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)13642; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e64 s0, v49, v13013643; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13644; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v66, v30, v54 :: v_dual_lshlrev_b32 v53, 16, v6413645; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v3513646; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v3013647; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v69, 16, v7013648; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v11713649; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13650; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v130, v35, v36 :: v_dual_lshlrev_b32 v129, 16, v3913651; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)13652; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v37, v12913653; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_sdst(0)13654; GFX12-FAKE16-NEXT: v_cndmask_b32_e64 v129, v51, v52, s013655; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13656; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v37, v39, v48 :: v_dual_lshlrev_b32 v118, 16, v10213657; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v131, 16, v5513658; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)13659; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v53, v13113660; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13661; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v50, 16, v1513662; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v133, 16, v7113663; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v13213664; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13665; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v67, v68, vcc_lo13666; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13667; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v69, v13313668; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v135, 16, v8713669; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13670; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6513671; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v81, v13413672; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13673; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v81, v83, v80, vcc_lo13674; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v85, v13513675; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v145, 16, v10313676; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13677; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v85, v87, v82, vcc_lo13678; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v97, v14413679; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13680; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v9813681; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v101, v14513682; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v147, 16, v11513683; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13684; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)13685; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9713686; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v112, v14613687; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13688; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v112, v113, v96, vcc_lo13689; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v114, v14713690; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11913691; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v49, 16, v3813692; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13693; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v114, v115, v98, vcc_lo13694; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v116, v1413695; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13696; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v116, v117, v100, vcc_lo13697; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v118, v3013698; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13699; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v118, v119, v102, vcc_lo13700; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v128, v4913701; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13702; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v128, v38, v34, vcc_lo13703; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3613704; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13705; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v36, vcc_lo13706; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4813707; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13708; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v37, v48, vcc_lo13709; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5213710; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13711; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v129, v52, vcc_lo13712; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6413713; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v52, 16, v12913714; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13715; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v53, v64, vcc_lo13716; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6813717; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13718; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v65, v68, vcc_lo13719; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7013720; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13721; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v69, v70, vcc_lo13722; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8013723; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13724; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v81, v80, vcc_lo13725; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8213726; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13727; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v85, v82, vcc_lo13728; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8413729; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13730; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v97, v84, vcc_lo13731; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8613732; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13733; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v101, v86, vcc_lo13734; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9613735; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13736; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v96, v112, v96, vcc_lo13737; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9813738; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13739; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v5313740; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10013741; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13742; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v133, 16, v6913743; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3513744; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13745; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v135, 16, v8513746; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10213747; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13748; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v118, v102, vcc_lo13749; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3913750; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13751; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v36, v36, v39 :: v_dual_lshlrev_b32 v145, 16, v10113752; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3413753; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13754; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v128, v34, vcc_lo13755; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5113756; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13757; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v49, v51, vcc_lo13758; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5513759; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12813760; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13761; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v64, v55, vcc_lo13762; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6713763; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13764; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v68, v67, vcc_lo13765; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7113766; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13767; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v147, 16, v11413768; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8313769; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13770; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v67, v80, v83, vcc_lo13771; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8713772; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13773; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v68, v82, v87, vcc_lo13774; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v9913775; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13776; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v70, v84, v99, vcc_lo13777; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v10313778; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13779; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v71, v86, v103 :: v_dual_lshlrev_b32 v30, 16, v13013780; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11313781; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v3713782; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13783; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v80, v96, v113, vcc_lo13784; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11513785; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13786; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v82, v98, v115, vcc_lo13787; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11713788; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v134, 16, v8113789; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13790; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v83, v100, v117, vcc_lo13791; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v11913792; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13793; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v84, v35, v119, vcc_lo13794; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3813795; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13796; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v86, v34, v38, vcc_lo13797; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v3013798; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13799; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v14, v130, v14, vcc_lo13800; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v4813801; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13802; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v30, v37, v36, vcc_lo13803; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5213804; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x013805; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3113806; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13807; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v34, v129, v39, vcc_lo13808; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13113809; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13810; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v35, v53, v49, vcc_lo13811; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13213812; GFX12-FAKE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v3113813; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13814; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v36, v65, v55, vcc_lo13815; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13313816; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13817; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v37, v69, v64, vcc_lo13818; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13413819; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13820; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v38, v81, v67, vcc_lo13821; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13513822; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13823; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v39, v85, v68, vcc_lo13824; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14413825; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13826; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v48, v97, v70, vcc_lo13827; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14513828; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13829; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v49, v101, v71, vcc_lo13830; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v5013831; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13832; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v15, v31, vcc_lo13833; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v3213834; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v32, 16, v3113835; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v148, 16, v11613836; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)13837; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v5513838; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13839; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo13840; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v146, 16, v11213841; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v3313842; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)13843; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14613844; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13845; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v15, v112, v80, vcc_lo13846; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v53, v5313847; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13848; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v52, v33, vcc_lo13849; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v3213850; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v102, 16, v11813851; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13852; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)13853; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v31, v55 :: v_dual_lshlrev_b32 v64, 16, v5213854; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14713855; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v5313856; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13857; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v31, v114, v82, vcc_lo13858; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v14813859; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13860; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v32, v116, v83, vcc_lo13861; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v50, v6413862; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13863; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v64, v52, v33, vcc_lo13864; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v6713865; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)13866; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v67, 16, v6413867; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13868; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v65, v53, v55, vcc_lo13869; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10213870; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v68, 16, v6513871; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13872; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v50, v118, v84, vcc_lo13873; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3313874; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13875; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo13876; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5513877; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13878; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v55, v65, v55, vcc_lo13879; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5213880; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13881; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v52, vcc_lo13882; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5313883; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13884; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v55, v53, vcc_lo13885; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6713886; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v1313887; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13888; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v33, v64, v33, vcc_lo13889; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v5113890; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13891; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v52, v128, v86, vcc_lo13892; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6813893; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13894; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v51, v65, v53, vcc_lo13895; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5513896; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v53, 16, v6613897; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2913898; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v1213899; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13900; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v64, 16, v5413901; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)13902; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v64, v5313903; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13904; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v53, v66, v54, vcc_lo13905; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6513906; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v1313907; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13908; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v13, vcc_lo13909; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5513910; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v2813911; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)13912; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v2913913; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13914; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo13915; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v5413916; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13917; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v53, v54, vcc_lo13918; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5513919; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13920; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v12, vcc_lo13921; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6613922; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13923; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v54, v66, vcc_lo13924; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v65, v6413925; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v64, 16, v5313926; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2813927; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13928; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v55, v29, v13 :: v_dual_lshlrev_b32 v66, 16, v1213929; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1313930; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13931; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)13932; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo13933; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6413934; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13935; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v5513936; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v66, v6513937; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v65, 16, v2713938; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)13939; GFX12-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0x504010013940; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13941; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v54, v28, v12, vcc_lo13942; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2913943; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13944; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v29, vcc_lo13945; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v1113946; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1213947; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13948; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo13949; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)13950; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2913951; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v1013952; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13953; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo13954; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2813955; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13956; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v12, v28, vcc_lo13957; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v65, v6513958; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13959; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v5413960; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v6413961; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13962; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v13, v55, v13, vcc_lo13963; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13964; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2813965; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v2613966; GFX12-FAKE16-NEXT: v_perm_b32 v13, v30, v13, 0x504010013967; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13968; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v12, v54, v12, vcc_lo13969; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2913970; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v1113971; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13972; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v913973; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2713974; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)13975; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v54, v2813976; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13977; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v28, v27, v11, vcc_lo13978; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v55, v5513979; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13980; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v10, vcc_lo13981; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2913982; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v2513983; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13984; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v25, vcc_lo13985; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1113986; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13987; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v2613988; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v2913989; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13990; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v9, vcc_lo13991; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2713992; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)13993; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v27, vcc_lo13994; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v2813995; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v1013996; GFX12-FAKE16-NEXT: v_perm_b32 v12, v34, v12, 0x504010013997; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)13998; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v5413999; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v54, 16, v2514000; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v55, 16, v914001; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14002; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v29, v26, v10, vcc_lo14003; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2714004; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14005; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v11, v28, v11, vcc_lo14006; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1014007; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2914008; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)14009; GFX12-FAKE16-NEXT: v_perm_b32 v11, v35, v11, 0x504010014010; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14011; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo14012; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v55, v5414013; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14014; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v25, v9, vcc_lo14015; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2614016; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14017; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v26, vcc_lo14018; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v914019; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14020; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v9, v27, v9, vcc_lo14021; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2814022; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v2314023; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14024; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v10, vcc_lo14025; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2514026; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14027; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v26, 16, v814028; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v714029; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)14030; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v2614031; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14032; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo14033; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2514034; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2714035; GFX12-FAKE16-NEXT: v_perm_b32 v10, v36, v10, 0x504010014036; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14037; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v2414038; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)14039; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 16, v714040; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v2614041; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14042; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v8, vcc_lo14043; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v2814044; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14045; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)14046; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v2414047; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2514048; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v614049; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14050; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v2314051; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14052; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2514053; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v814054; GFX12-FAKE16-NEXT: v_perm_b32 v9, v37, v9, 0x504010014055; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14056; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo14057; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)14058; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v27, v2614059; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14060; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v26, v24, v8 :: v_dual_lshlrev_b32 v25, 16, v2214061; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v29, v2814062; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14063; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v27, v23, v7, vcc_lo14064; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)14065; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2514066; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14067; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v6, vcc_lo14068; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v814069; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14070; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo14071; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v714072; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14073; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo14074; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2414075; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14076; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v24, vcc_lo14077; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2314078; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14079; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v2614080; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2214081; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v614082; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)14083; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v28, v2514084; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2714085; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14086; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v22, v6, vcc_lo14087; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2414088; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v514089; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14090; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v26, v8, vcc_lo14091; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v614092; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14093; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo14094; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2514095; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v2114096; GFX12-FAKE16-NEXT: v_perm_b32 v8, v38, v8, 0x504010014097; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14098; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v27, v7, vcc_lo14099; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2214100; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)14101; GFX12-FAKE16-NEXT: v_perm_b32 v7, v39, v7, 0x504010014102; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14103; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v22, vcc_lo14104; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v2414105; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14106; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v414107; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2314108; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)14109; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2214110; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2014111; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14112; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v6, vcc_lo14113; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v2514114; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v314115; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v514116; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14117; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v5, vcc_lo14118; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v2414119; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)14120; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2114121; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14122; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo14123; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v2214124; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14125; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v4, vcc_lo14126; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v2314127; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14128; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v19, vcc_lo14129; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2414130; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v2014131; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v414132; GFX12-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0x504010014133; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14134; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v23, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v1914135; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)14136; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v2214137; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14138; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v3, vcc_lo14139; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v514140; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14141; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo14142; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2414143; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v314144; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v1914145; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14146; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v22, v20, v4, vcc_lo14147; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2114148; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14149; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v21, vcc_lo14150; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v414151; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14152; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v22, v4 :: v_dual_lshlrev_b32 v21, 16, v2314153; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2414154; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14155; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v24, v19, v3, vcc_lo14156; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)14157; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2114158; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v2214159; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14160; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v23, v5, vcc_lo14161; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2014162; GFX12-FAKE16-NEXT: v_perm_b32 v5, v49, v5, 0x504010014163; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14164; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v20, vcc_lo14165; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v314166; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14167; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo14168; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1914169; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14170; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14171; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v20, 16, v214172; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v1814173; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2014174; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14175; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v18 :: v_dual_lshlrev_b32 v23, 16, v2414176; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)14177; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2314178; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14179; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo14180; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v1914181; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v014182; GFX12-FAKE16-NEXT: v_perm_b32 v3, v31, v3, 0x504010014183; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14184; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v2, vcc_lo14185; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v114186; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)14187; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2014188; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14189; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo14190; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v2314191; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v1714192; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v114193; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14194; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo14195; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)14196; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v1914197; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14198; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v17, v17, v1 :: v_dual_lshlrev_b32 v20, 16, v1614199; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v214200; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v2014201; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14202; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v0 :: v_dual_lshlrev_b32 v19, 16, v1814203; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1714204; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)14205; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v1914206; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14207; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v19, v18, v2, vcc_lo14208; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v2014209; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14210; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v1, vcc_lo14211; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v214212; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14213; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v2 :: v_dual_lshlrev_b32 v23, 16, v1614214; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v014215; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)14216; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v25, v2314217; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14218; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v23, v16, v0, vcc_lo14219; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114220; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14221; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v20, v1, vcc_lo14222; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1814223; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14224; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v18, vcc_lo14225; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014226; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14227; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo14228; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1714229; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14230; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo14231; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2014232; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1614233; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14234; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo14235; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)14236; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1714237; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2314238; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14239; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v1914240; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1814241; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)14242; GFX12-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0x504010014243; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14244; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v23, v0, vcc_lo14245; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1614246; GFX12-FAKE16-NEXT: v_perm_b32 v0, v52, v0, 0x504010014247; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14248; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo14249; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2114250; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)14251; GFX12-FAKE16-NEXT: v_perm_b32 v2, v32, v2, 0x504010014252; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14253; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v4, vcc_lo14254; GFX12-FAKE16-NEXT: v_perm_b32 v4, v15, v4, 0x504010014255; GFX12-FAKE16-NEXT: v_perm_b32 v15, v33, v51, 0x504010014256; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]14257 %result = call <32 x bfloat> @llvm.maximumnum.v32bf16(<32 x bfloat> %x, <32 x bfloat> %y)14258 ret <32 x bfloat> %result14259}14260 14261define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {14262; GFX7-LABEL: v_maximumnum_bf16_no_ieee:14263; GFX7: ; %bb.0:14264; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14265; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v014266; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v114267; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v114268; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v014269; GFX7-NEXT: v_max_f32_e32 v0, v0, v114270; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v014271; GFX7-NEXT: s_setpc_b64 s[30:31]14272;14273; GFX8-LABEL: v_maximumnum_bf16_no_ieee:14274; GFX8: ; %bb.0:14275; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14276; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v014277; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v214278; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v114279; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14280; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v214281; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc14282; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v114283; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v014284; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v3, v214285; GFX8-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc14286; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014287; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc14288; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114289; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14290; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v214291; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114292; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc14293; GFX8-NEXT: s_setpc_b64 s[30:31]14294;14295; GFX900-LABEL: v_maximumnum_bf16_no_ieee:14296; GFX900: ; %bb.0:14297; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14298; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v014299; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v214300; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v114301; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14302; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v314303; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc14304; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v014305; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v114306; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v2, v314307; GFX900-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc14308; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014309; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc14310; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114311; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14312; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v214313; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114314; GFX900-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc14315; GFX900-NEXT: s_setpc_b64 s[30:31]14316;14317; GFX950-LABEL: v_maximumnum_bf16_no_ieee:14318; GFX950: ; %bb.0:14319; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14320; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v014321; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v2, v214322; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v114323; GFX950-NEXT: s_nop 014324; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14325; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v314326; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v014327; GFX950-NEXT: s_nop 014328; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc14329; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v114330; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v2, v314331; GFX950-NEXT: s_nop 114332; GFX950-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc14333; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014334; GFX950-NEXT: s_nop 114335; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc14336; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114337; GFX950-NEXT: s_nop 114338; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14339; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v214340; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114341; GFX950-NEXT: s_nop 114342; GFX950-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc14343; GFX950-NEXT: s_setpc_b64 s[30:31]14344;14345; GFX10-LABEL: v_maximumnum_bf16_no_ieee:14346; GFX10: ; %bb.0:14347; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14348; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v014349; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v114350; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214351; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14352; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v314353; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v014354; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo14355; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v114356; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v314357; GFX10-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo14358; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014359; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v214360; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo14361; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114362; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14363; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v314364; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo14365; GFX10-NEXT: s_setpc_b64 s[30:31]14366;14367; GFX11-TRUE16-LABEL: v_maximumnum_bf16_no_ieee:14368; GFX11-TRUE16: ; %bb.0:14369; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14370; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 014371; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l14372; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l14373; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)14374; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214375; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l14376; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l14377; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo14378; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14379; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214380; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h14381; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo14382; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)14383; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v214384; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo14385; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h14386; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s014387; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14388; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo14389; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l14390; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v214391; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)14392; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo14393; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]14394;14395; GFX11-FAKE16-LABEL: v_maximumnum_bf16_no_ieee:14396; GFX11-FAKE16: ; %bb.0:14397; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14398; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v014399; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)14400; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214401; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14402; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v114403; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v014404; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)14405; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v314406; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo14407; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v114408; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14409; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v314410; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo14411; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v214412; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014413; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo14414; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114415; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14416; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14417; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v314418; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo14419; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]14420;14421; GFX12-TRUE16-LABEL: v_maximumnum_bf16_no_ieee:14422; GFX12-TRUE16: ; %bb.0:14423; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x014424; GFX12-TRUE16-NEXT: s_wait_expcnt 0x014425; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x014426; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x014427; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x014428; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, 014429; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l14430; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l14431; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)14432; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214433; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l14434; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l14435; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14436; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo14437; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214438; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)14439; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.h14440; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14441; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo14442; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v214443; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14444; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo14445; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.h14446; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)14447; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)14448; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v1.h, s014449; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14450; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo14451; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l14452; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)14453; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v214454; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14455; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo14456; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]14457;14458; GFX12-FAKE16-LABEL: v_maximumnum_bf16_no_ieee:14459; GFX12-FAKE16: ; %bb.0:14460; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x014461; GFX12-FAKE16-NEXT: s_wait_expcnt 0x014462; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x014463; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x014464; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x014465; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v014466; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)14467; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214468; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14469; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14470; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v114471; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v014472; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)14473; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v314474; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14475; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo14476; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v114477; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)14478; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v314479; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14480; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc_lo14481; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v214482; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014483; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14484; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo14485; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114486; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14487; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)14488; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14489; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v314490; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14491; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo14492; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]14493 %result = call bfloat @llvm.maximumnum.bf16(bfloat %x, bfloat %y)14494 ret bfloat %result14495}14496 14497define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %y) #0 {14498; GFX7-LABEL: v_maximumnum_v2bf16_no_ieee:14499; GFX7: ; %bb.0:14500; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14501; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v014502; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v214503; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v114504; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v314505; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v314506; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v114507; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v214508; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v014509; GFX7-NEXT: v_max_f32_e32 v1, v1, v314510; GFX7-NEXT: v_max_f32_e32 v0, v0, v214511; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v014512; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v114513; GFX7-NEXT: s_setpc_b64 s[30:31]14514;14515; GFX8-LABEL: v_maximumnum_v2bf16_no_ieee:14516; GFX8: ; %bb.0:14517; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14518; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v014519; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v2, v214520; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v114521; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v114522; GFX8-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14523; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v514524; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc14525; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v314526; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v214527; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v514528; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc14529; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v314530; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc14531; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v214532; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc14533; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v414534; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v314535; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v014536; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc14537; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v314538; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v114539; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14540; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v314541; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc14542; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v114543; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v014544; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v4, v314545; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc14546; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014547; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14548; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114549; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14550; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v314551; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114552; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v214553; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14554; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD14555; GFX8-NEXT: s_setpc_b64 s[30:31]14556;14557; GFX900-LABEL: v_maximumnum_v2bf16_no_ieee:14558; GFX900: ; %bb.0:14559; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14560; GFX900-NEXT: v_and_b32_e32 v2, 0xffff0000, v014561; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v2, v214562; GFX900-NEXT: v_lshrrev_b32_e32 v2, 16, v114563; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v114564; GFX900-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14565; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v514566; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc14567; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v314568; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v214569; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v514570; GFX900-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc14571; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v314572; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc14573; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v214574; GFX900-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc14575; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v414576; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v314577; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v014578; GFX900-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc14579; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v314580; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v114581; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14582; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v314583; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc14584; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v114585; GFX900-NEXT: v_lshlrev_b32_e32 v4, 16, v014586; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v4, v314587; GFX900-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc14588; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014589; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14590; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114591; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14592; GFX900-NEXT: v_lshlrev_b32_e32 v1, 16, v314593; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114594; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14595; GFX900-NEXT: s_mov_b32 s4, 0x504010014596; GFX900-NEXT: v_perm_b32 v0, v2, v0, s414597; GFX900-NEXT: s_setpc_b64 s[30:31]14598;14599; GFX950-LABEL: v_maximumnum_v2bf16_no_ieee:14600; GFX950: ; %bb.0:14601; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14602; GFX950-NEXT: v_and_b32_e32 v2, 0xffff0000, v014603; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v2, v214604; GFX950-NEXT: v_lshrrev_b32_e32 v2, 16, v114605; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v114606; GFX950-NEXT: v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14607; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v514608; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v314609; GFX950-NEXT: s_mov_b32 s0, 0x504010014610; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc14611; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v214612; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v514613; GFX950-NEXT: s_nop 114614; GFX950-NEXT: v_cndmask_b32_e32 v4, v2, v3, vcc14615; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v314616; GFX950-NEXT: s_nop 114617; GFX950-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc14618; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v214619; GFX950-NEXT: s_nop 114620; GFX950-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc14621; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v414622; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v314623; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v014624; GFX950-NEXT: s_nop 014625; GFX950-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc14626; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v314627; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v114628; GFX950-NEXT: s_nop 014629; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14630; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v314631; GFX950-NEXT: v_lshlrev_b32_e32 v4, 16, v014632; GFX950-NEXT: s_nop 014633; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc14634; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v114635; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v4, v314636; GFX950-NEXT: s_nop 114637; GFX950-NEXT: v_cndmask_b32_e32 v3, v1, v0, vcc14638; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014639; GFX950-NEXT: s_nop 114640; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14641; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114642; GFX950-NEXT: s_nop 114643; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc14644; GFX950-NEXT: v_lshlrev_b32_e32 v1, 16, v314645; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v114646; GFX950-NEXT: s_nop 114647; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14648; GFX950-NEXT: v_perm_b32 v0, v2, v0, s014649; GFX950-NEXT: s_setpc_b64 s[30:31]14650;14651; GFX10-LABEL: v_maximumnum_v2bf16_no_ieee:14652; GFX10: ; %bb.0:14653; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14654; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v014655; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v014656; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v114657; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v114658; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214659; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v114660; GFX10-NEXT: v_cndmask_b32_sdwa v6, v0, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14661; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v414662; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14663; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v314664; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v614665; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo14666; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v514667; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v014668; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v214669; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc_lo14670; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v414671; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v114672; GFX10-NEXT: v_cndmask_b32_e32 v3, v2, v6, vcc_lo14673; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v714674; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v314675; GFX10-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc_lo14676; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v614677; GFX10-NEXT: v_cndmask_b32_e32 v5, v3, v6, vcc_lo14678; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014679; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v414680; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo14681; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v214682; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo14683; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114684; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14685; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v714686; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo14687; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v614688; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo14689; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x504010014690; GFX10-NEXT: s_setpc_b64 s[30:31]14691;14692; GFX11-TRUE16-LABEL: v_maximumnum_v2bf16_no_ieee:14693; GFX11-TRUE16: ; %bb.0:14694; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14695; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v014696; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v114697; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, 014698; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v114699; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14700; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214701; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v314702; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)14703; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l14704; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v014705; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v514706; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo14707; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s014708; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h14709; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)14710; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v214711; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo14712; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v314713; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l14714; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s014715; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l14716; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo14717; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)14718; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v414719; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s114720; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.h14721; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)14722; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v3, v414723; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s014724; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h14725; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14726; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s114727; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.h14728; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s014729; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l14730; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14731; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s114732; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v414733; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)14734; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo14735; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s014736; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]14737;14738; GFX11-FAKE16-LABEL: v_maximumnum_v2bf16_no_ieee:14739; GFX11-FAKE16: ; %bb.0:14740; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14741; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v014742; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v114743; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v014744; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14745; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214746; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v014747; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v114748; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14749; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v514750; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14751; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v614752; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo14753; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14754; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v314755; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v114756; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v414757; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v214758; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)14759; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v514760; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v114761; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v014762; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)14763; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v714764; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v414765; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo14766; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v214767; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)14768; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v514769; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014770; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo14771; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v314772; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo14773; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114774; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)14775; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14776; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v614777; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo14778; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v714779; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)14780; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo14781; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x504010014782; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]14783;14784; GFX12-TRUE16-LABEL: v_maximumnum_v2bf16_no_ieee:14785; GFX12-TRUE16: ; %bb.0:14786; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x014787; GFX12-TRUE16-NEXT: s_wait_expcnt 0x014788; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x014789; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x014790; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x014791; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v014792; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v114793; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 014794; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v114795; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14796; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214797; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v3, v314798; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)14799; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l14800; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v014801; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v5, v514802; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14803; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo14804; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)14805; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)14806; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v1.h, v4.h, s014807; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h14808; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v214809; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14810; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo14811; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v314812; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l14813; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)14814; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)14815; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v4.h, s014816; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l14817; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14818; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo14819; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v414820; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14821; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v1.l, v3.h, s114822; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.h14823; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v3, v414824; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)14825; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)14826; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.h, v3.h, s014827; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.h14828; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, v3.h, s114829; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v2.h14830; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)14831; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14832; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, s014833; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v0.l14834; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.h, v2.h, s114835; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14836; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v414837; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)14838; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo14839; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)14840; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)14841; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s014842; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]14843;14844; GFX12-FAKE16-LABEL: v_maximumnum_v2bf16_no_ieee:14845; GFX12-FAKE16: ; %bb.0:14846; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x014847; GFX12-FAKE16-NEXT: s_wait_expcnt 0x014848; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x014849; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x014850; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x014851; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v014852; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v114853; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v014854; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)14855; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v214856; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14857; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v014858; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v114859; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)14860; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v514861; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14862; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14863; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v614864; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14865; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v2, vcc_lo14866; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14867; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v314868; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v114869; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v414870; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14871; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v214872; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)14873; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v514874; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14875; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v114876; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v014877; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)14878; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v714879; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v414880; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14881; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v1, v0, vcc_lo14882; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v214883; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14884; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)14885; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v514886; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v014887; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14888; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo14889; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v314890; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14891; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo14892; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v114893; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14894; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo14895; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v614896; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14897; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo14898; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v714899; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)14900; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo14901; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)14902; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x504010014903; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]14904 %result = call <2 x bfloat> @llvm.maximumnum.v2bf16(<2 x bfloat> %x, <2 x bfloat> %y)14905 ret <2 x bfloat> %result14906}14907 14908define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %y) #0 {14909; GFX7-LABEL: v_maximumnum_v3bf16_no_ieee:14910; GFX7: ; %bb.0:14911; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14912; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v014913; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v314914; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v114915; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v414916; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v214917; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v514918; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v514919; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v214920; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v414921; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v114922; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v314923; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v014924; GFX7-NEXT: v_max_f32_e32 v2, v2, v514925; GFX7-NEXT: v_max_f32_e32 v1, v1, v414926; GFX7-NEXT: v_max_f32_e32 v0, v0, v314927; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v214928; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v014929; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v114930; GFX7-NEXT: s_setpc_b64 s[30:31]14931;14932; GFX8-LABEL: v_maximumnum_v3bf16_no_ieee:14933; GFX8: ; %bb.0:14934; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14935; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v014936; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v414937; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v214938; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v214939; GFX8-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14940; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v714941; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc14942; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v514943; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v414944; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v714945; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc14946; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v514947; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc14948; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v414949; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc14950; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v614951; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v514952; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v114953; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc14954; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v514955; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v314956; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc14957; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v514958; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc14959; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v314960; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v114961; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v514962; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc14963; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v114964; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc14965; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v314966; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc14967; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v514968; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v314969; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v014970; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc14971; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v314972; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v214973; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc14974; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v314975; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc14976; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v214977; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v014978; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v5, v314979; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc14980; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v014981; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14982; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v214983; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc14984; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v314985; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v214986; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc14987; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v414988; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD14989; GFX8-NEXT: s_setpc_b64 s[30:31]14990;14991; GFX900-LABEL: v_maximumnum_v3bf16_no_ieee:14992; GFX900: ; %bb.0:14993; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14994; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v014995; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v414996; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v214997; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v214998; GFX900-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14999; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v715000; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc15001; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v515002; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v415003; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v715004; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc15005; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515006; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc15007; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v415008; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc15009; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v615010; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v515011; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v115012; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc15013; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v515014; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v315015; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15016; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v515017; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc15018; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v315019; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v115020; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v515021; GFX900-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc15022; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v115023; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc15024; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v315025; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15026; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v515027; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v315028; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v015029; GFX900-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc15030; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v315031; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v215032; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15033; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v315034; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc15035; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v215036; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v015037; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v5, v315038; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc15039; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v015040; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15041; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v215042; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15043; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v315044; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v215045; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15046; GFX900-NEXT: s_mov_b32 s4, 0x504010015047; GFX900-NEXT: v_perm_b32 v0, v4, v0, s415048; GFX900-NEXT: s_setpc_b64 s[30:31]15049;15050; GFX950-LABEL: v_maximumnum_v3bf16_no_ieee:15051; GFX950: ; %bb.0:15052; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15053; GFX950-NEXT: v_and_b32_e32 v4, 0xffff0000, v015054; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v415055; GFX950-NEXT: v_lshrrev_b32_e32 v4, 16, v215056; GFX950-NEXT: v_and_b32_e32 v7, 0xffff0000, v215057; GFX950-NEXT: v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15058; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v715059; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v515060; GFX950-NEXT: s_mov_b32 s0, 0x504010015061; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc15062; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v415063; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v715064; GFX950-NEXT: s_nop 115065; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc15066; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515067; GFX950-NEXT: s_nop 115068; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc15069; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v415070; GFX950-NEXT: s_nop 115071; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc15072; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v615073; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v515074; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v115075; GFX950-NEXT: s_nop 015076; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc15077; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v515078; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v315079; GFX950-NEXT: s_nop 015080; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15081; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v515082; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v115083; GFX950-NEXT: s_nop 015084; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc15085; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v315086; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v515087; GFX950-NEXT: s_nop 115088; GFX950-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc15089; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v115090; GFX950-NEXT: s_nop 115091; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc15092; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v315093; GFX950-NEXT: s_nop 115094; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15095; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v515096; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v315097; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v015098; GFX950-NEXT: s_nop 015099; GFX950-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc15100; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v315101; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v215102; GFX950-NEXT: s_nop 015103; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15104; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v315105; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v015106; GFX950-NEXT: s_nop 015107; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc15108; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v215109; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v5, v315110; GFX950-NEXT: s_nop 115111; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc15112; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v015113; GFX950-NEXT: s_nop 115114; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15115; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v215116; GFX950-NEXT: s_nop 115117; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15118; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v315119; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v215120; GFX950-NEXT: s_nop 115121; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15122; GFX950-NEXT: v_perm_b32 v0, v4, v0, s015123; GFX950-NEXT: s_setpc_b64 s[30:31]15124;15125; GFX10-LABEL: v_maximumnum_v3bf16_no_ieee:15126; GFX10: ; %bb.0:15127; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15128; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v015129; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v215130; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v015131; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v215132; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v215133; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415134; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v115135; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v315136; GFX10-NEXT: v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15137; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v815138; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15139; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415140; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15141; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v615142; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v10, vcc_lo15143; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v915144; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1015145; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v115146; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v415147; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo15148; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715149; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v015150; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v215151; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo15152; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v615153; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v315154; GFX10-NEXT: v_cndmask_b32_e32 v5, v4, v10, vcc_lo15155; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v815156; GFX10-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc_lo15157; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v1115158; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v515159; GFX10-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc_lo15160; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1015161; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo15162; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v015163; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo15164; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v415165; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo15166; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v215167; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v615168; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15169; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v915170; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo15171; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115172; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v715173; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo15174; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v815175; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc_lo15176; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v315177; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x504010015178; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15179; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v415180; GFX10-NEXT: v_cndmask_b32_e32 v1, v7, v1, vcc_lo15181; GFX10-NEXT: s_setpc_b64 s[30:31]15182;15183; GFX11-TRUE16-LABEL: v_maximumnum_v3bf16_no_ieee:15184; GFX11-TRUE16: ; %bb.0:15185; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15186; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v015187; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v215188; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, 015189; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v315190; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15191; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415192; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v515193; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)15194; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l15195; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v115196; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v715197; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo15198; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v215199; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s015200; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15201; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15202; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v715203; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v415204; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo15205; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v515206; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l15207; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)15208; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s015209; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l15210; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo15211; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v615212; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)15213; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v5.h, s115214; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h15215; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v015216; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v615217; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15218; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s015219; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15220; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s115221; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v315222; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15223; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s015224; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l15225; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s115226; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l15227; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15228; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v615229; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s215230; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.h15231; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15232; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s015233; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v0, v615234; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15235; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s115236; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.h15237; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s215238; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.h15239; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15240; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s115241; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l15242; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s215243; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15244; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v615245; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo15246; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)15247; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s115248; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]15249;15250; GFX11-FAKE16-LABEL: v_maximumnum_v3bf16_no_ieee:15251; GFX11-FAKE16: ; %bb.0:15252; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15253; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v015254; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v215255; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v015256; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v015257; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)15258; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415259; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v215260; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)15261; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715262; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v115263; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v815264; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v315265; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v215266; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)15267; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v615268; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15269; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715270; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v415271; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo15272; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v515273; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)15274; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v1015275; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo15276; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v915277; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v115278; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v615279; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v415280; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v215281; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo15282; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v515283; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)15284; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v015285; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v815286; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v315287; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo15288; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1015289; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo15290; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v015291; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)15292; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo15293; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v715294; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v515295; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo15296; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v215297; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15298; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115299; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)15300; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v615301; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v715302; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo15303; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v315304; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)15305; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x504010015306; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15307; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v215308; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo15309; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]15310;15311; GFX12-TRUE16-LABEL: v_maximumnum_v3bf16_no_ieee:15312; GFX12-TRUE16: ; %bb.0:15313; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x015314; GFX12-TRUE16-NEXT: s_wait_expcnt 0x015315; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x015316; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x015317; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x015318; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v015319; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v215320; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, 015321; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v315322; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15323; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415324; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v515325; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)15326; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l15327; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v115328; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v715329; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)15330; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo15331; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v215332; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15333; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15334; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v2.h, v6.h, s015335; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15336; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v715337; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)15338; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v415339; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)15340; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo15341; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v515342; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l15343; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15344; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)15345; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.h, s015346; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l15347; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)15348; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo15349; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v615350; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)15351; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v5.h, s115352; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.h15353; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v015354; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v615355; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15356; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15357; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v5.h, s015358; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15359; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v5.h, s115360; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v3, v315361; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15362; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15363; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s015364; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l15365; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s115366; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l15367; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15368; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v615369; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s215370; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v0.h15371; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15372; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15373; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s015374; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v0, v615375; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15376; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15377; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s115378; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.h15379; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s215380; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.h15381; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15382; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15383; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s115384; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l15385; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v4.h, s215386; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)15387; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v615388; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)15389; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo15390; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)15391; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)15392; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s115393; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]15394;15395; GFX12-FAKE16-LABEL: v_maximumnum_v3bf16_no_ieee:15396; GFX12-FAKE16: ; %bb.0:15397; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x015398; GFX12-FAKE16-NEXT: s_wait_expcnt 0x015399; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x015400; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x015401; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x015402; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v015403; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v215404; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v015405; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v015406; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)15407; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415408; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15409; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v215410; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15411; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715412; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15413; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v115414; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v815415; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15416; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v315417; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v215418; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v615419; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15420; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15421; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)15422; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715423; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v415424; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15425; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo15426; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v515427; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v1015428; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15429; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc_lo15430; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v915431; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v115432; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15433; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)15434; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v615435; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v415436; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v215437; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15438; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo15439; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v515440; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15441; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)15442; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v015443; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v815444; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v315445; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15446; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v2, v0, vcc_lo15447; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1015448; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15449; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo15450; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v015451; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15452; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo15453; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v715454; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v515455; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15456; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc_lo15457; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v215458; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15459; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15460; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115461; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15462; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v615463; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v715464; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15465; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc_lo15466; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v315467; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)15468; GFX12-FAKE16-NEXT: v_perm_b32 v0, v4, v0, 0x504010015469; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15470; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15471; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v215472; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)15473; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc_lo15474; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]15475 %result = call <3 x bfloat> @llvm.maximumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)15476 ret <3 x bfloat> %result15477}15478 15479define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %y) #0 {15480; GFX7-LABEL: v_maximumnum_v4bf16_no_ieee:15481; GFX7: ; %bb.0:15482; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15483; GFX7-NEXT: v_mul_f32_e32 v0, 1.0, v015484; GFX7-NEXT: v_mul_f32_e32 v4, 1.0, v415485; GFX7-NEXT: v_mul_f32_e32 v1, 1.0, v115486; GFX7-NEXT: v_mul_f32_e32 v5, 1.0, v515487; GFX7-NEXT: v_mul_f32_e32 v2, 1.0, v215488; GFX7-NEXT: v_mul_f32_e32 v6, 1.0, v615489; GFX7-NEXT: v_mul_f32_e32 v3, 1.0, v315490; GFX7-NEXT: v_mul_f32_e32 v7, 1.0, v715491; GFX7-NEXT: v_and_b32_e32 v7, 0xffff0000, v715492; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v315493; GFX7-NEXT: v_and_b32_e32 v6, 0xffff0000, v615494; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v215495; GFX7-NEXT: v_and_b32_e32 v5, 0xffff0000, v515496; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v115497; GFX7-NEXT: v_and_b32_e32 v4, 0xffff0000, v415498; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v015499; GFX7-NEXT: v_max_f32_e32 v3, v3, v715500; GFX7-NEXT: v_max_f32_e32 v2, v2, v615501; GFX7-NEXT: v_max_f32_e32 v1, v1, v515502; GFX7-NEXT: v_max_f32_e32 v0, v0, v415503; GFX7-NEXT: v_and_b32_e32 v0, 0xffff0000, v015504; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v115505; GFX7-NEXT: v_and_b32_e32 v2, 0xffff0000, v215506; GFX7-NEXT: v_and_b32_e32 v3, 0xffff0000, v315507; GFX7-NEXT: s_setpc_b64 s[30:31]15508;15509; GFX8-LABEL: v_maximumnum_v4bf16_no_ieee:15510; GFX8: ; %bb.0:15511; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15512; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v115513; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v4, v415514; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v315515; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v315516; GFX8-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15517; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v7, v715518; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc15519; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v515520; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v415521; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v715522; GFX8-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc15523; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515524; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc15525; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v415526; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc15527; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v615528; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v515529; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v015530; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc15531; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v215532; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v015533; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v5, v515534; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v215535; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc15536; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v8, v815537; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc15538; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v515539; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v615540; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v815541; GFX8-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc15542; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515543; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc15544; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v615545; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc15546; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v715547; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v615548; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v115549; GFX8-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc15550; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v615551; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v315552; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15553; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v6, v615554; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc15555; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v315556; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v115557; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v7, v615558; GFX8-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc15559; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v115560; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc15561; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v315562; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15563; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v615564; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v315565; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v015566; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc15567; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v315568; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v215569; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15570; GFX8-NEXT: v_cmp_u_f32_e32 vcc, v3, v315571; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc15572; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v215573; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v015574; GFX8-NEXT: v_cmp_gt_f32_e32 vcc, v6, v315575; GFX8-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc15576; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v015577; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15578; GFX8-NEXT: v_cmp_eq_u16_e32 vcc, 0, v215579; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15580; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v315581; GFX8-NEXT: v_cmp_eq_f32_e32 vcc, 0, v215582; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15583; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v515584; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15585; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v415586; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15587; GFX8-NEXT: s_setpc_b64 s[30:31]15588;15589; GFX900-LABEL: v_maximumnum_v4bf16_no_ieee:15590; GFX900: ; %bb.0:15591; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15592; GFX900-NEXT: v_and_b32_e32 v4, 0xffff0000, v115593; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v4, v415594; GFX900-NEXT: v_lshrrev_b32_e32 v4, 16, v315595; GFX900-NEXT: v_and_b32_e32 v7, 0xffff0000, v315596; GFX900-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15597; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v7, v715598; GFX900-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc15599; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v515600; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v415601; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v715602; GFX900-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc15603; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515604; GFX900-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc15605; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v415606; GFX900-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc15607; GFX900-NEXT: v_lshlrev_b32_e32 v5, 16, v615608; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v515609; GFX900-NEXT: v_and_b32_e32 v5, 0xffff0000, v015610; GFX900-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc15611; GFX900-NEXT: v_lshrrev_b32_e32 v6, 16, v215612; GFX900-NEXT: v_lshrrev_b32_e32 v7, 16, v015613; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v5, v515614; GFX900-NEXT: v_and_b32_e32 v8, 0xffff0000, v215615; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc15616; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v8, v815617; GFX900-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc15618; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v515619; GFX900-NEXT: v_lshlrev_b32_e32 v8, 16, v615620; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v815621; GFX900-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc15622; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515623; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc15624; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v615625; GFX900-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc15626; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v715627; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v615628; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v115629; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc15630; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v615631; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v315632; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15633; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v6, v615634; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc15635; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v315636; GFX900-NEXT: v_lshlrev_b32_e32 v7, 16, v115637; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v7, v615638; GFX900-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc15639; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v115640; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc15641; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v315642; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15643; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v615644; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v315645; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v015646; GFX900-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc15647; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v315648; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v215649; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15650; GFX900-NEXT: v_cmp_u_f32_e32 vcc, v3, v315651; GFX900-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc15652; GFX900-NEXT: v_lshlrev_b32_e32 v3, 16, v215653; GFX900-NEXT: v_lshlrev_b32_e32 v6, 16, v015654; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, v6, v315655; GFX900-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc15656; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v015657; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15658; GFX900-NEXT: v_cmp_eq_u16_e32 vcc, 0, v215659; GFX900-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15660; GFX900-NEXT: v_lshlrev_b32_e32 v2, 16, v315661; GFX900-NEXT: v_cmp_eq_f32_e32 vcc, 0, v215662; GFX900-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15663; GFX900-NEXT: s_mov_b32 s4, 0x504010015664; GFX900-NEXT: v_perm_b32 v0, v5, v0, s415665; GFX900-NEXT: v_perm_b32 v1, v4, v1, s415666; GFX900-NEXT: s_setpc_b64 s[30:31]15667;15668; GFX950-LABEL: v_maximumnum_v4bf16_no_ieee:15669; GFX950: ; %bb.0:15670; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15671; GFX950-NEXT: v_and_b32_e32 v4, 0xffff0000, v115672; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v4, v415673; GFX950-NEXT: v_lshrrev_b32_e32 v4, 16, v315674; GFX950-NEXT: v_and_b32_e32 v7, 0xffff0000, v315675; GFX950-NEXT: v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15676; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v7, v715677; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v515678; GFX950-NEXT: v_and_b32_e32 v8, 0xffff0000, v215679; GFX950-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc15680; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v415681; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v715682; GFX950-NEXT: v_lshrrev_b32_e32 v7, 16, v015683; GFX950-NEXT: s_mov_b32 s0, 0x504010015684; GFX950-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc15685; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515686; GFX950-NEXT: s_nop 115687; GFX950-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc15688; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v415689; GFX950-NEXT: s_nop 115690; GFX950-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc15691; GFX950-NEXT: v_lshlrev_b32_e32 v5, 16, v615692; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v515693; GFX950-NEXT: v_and_b32_e32 v5, 0xffff0000, v015694; GFX950-NEXT: s_nop 015695; GFX950-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc15696; GFX950-NEXT: v_lshrrev_b32_e32 v6, 16, v215697; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v5, v515698; GFX950-NEXT: s_nop 115699; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc15700; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v8, v815701; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v515702; GFX950-NEXT: s_nop 015703; GFX950-NEXT: v_cndmask_b32_e32 v6, v6, v5, vcc15704; GFX950-NEXT: v_lshlrev_b32_e32 v8, 16, v615705; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v815706; GFX950-NEXT: s_nop 115707; GFX950-NEXT: v_cndmask_b32_e32 v7, v6, v5, vcc15708; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v515709; GFX950-NEXT: s_nop 115710; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc15711; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v615712; GFX950-NEXT: s_nop 115713; GFX950-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc15714; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v715715; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v615716; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v115717; GFX950-NEXT: s_nop 015718; GFX950-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc15719; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v615720; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v315721; GFX950-NEXT: s_nop 015722; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15723; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v6, v615724; GFX950-NEXT: v_lshlrev_b32_e32 v7, 16, v115725; GFX950-NEXT: s_nop 015726; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc15727; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v315728; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v7, v615729; GFX950-NEXT: s_nop 115730; GFX950-NEXT: v_cndmask_b32_e32 v6, v3, v1, vcc15731; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v115732; GFX950-NEXT: s_nop 115733; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc15734; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v315735; GFX950-NEXT: s_nop 115736; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc15737; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v615738; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v315739; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v015740; GFX950-NEXT: s_nop 015741; GFX950-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc15742; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v315743; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v215744; GFX950-NEXT: v_perm_b32 v1, v4, v1, s015745; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15746; GFX950-NEXT: v_cmp_u_f32_e32 vcc, v3, v315747; GFX950-NEXT: v_lshlrev_b32_e32 v6, 16, v015748; GFX950-NEXT: s_nop 015749; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc15750; GFX950-NEXT: v_lshlrev_b32_e32 v3, 16, v215751; GFX950-NEXT: v_cmp_gt_f32_e32 vcc, v6, v315752; GFX950-NEXT: s_nop 115753; GFX950-NEXT: v_cndmask_b32_e32 v3, v2, v0, vcc15754; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v015755; GFX950-NEXT: s_nop 115756; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15757; GFX950-NEXT: v_cmp_eq_u16_e32 vcc, 0, v215758; GFX950-NEXT: s_nop 115759; GFX950-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc15760; GFX950-NEXT: v_lshlrev_b32_e32 v2, 16, v315761; GFX950-NEXT: v_cmp_eq_f32_e32 vcc, 0, v215762; GFX950-NEXT: s_nop 115763; GFX950-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc15764; GFX950-NEXT: v_perm_b32 v0, v5, v0, s015765; GFX950-NEXT: s_setpc_b64 s[30:31]15766;15767; GFX10-LABEL: v_maximumnum_v4bf16_no_ieee:15768; GFX10: ; %bb.0:15769; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15770; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v115771; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v315772; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v315773; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v215774; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v015775; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415776; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v015777; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v115778; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v015779; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v215780; GFX10-NEXT: v_cndmask_b32_sdwa v10, v1, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15781; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v615782; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v315783; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v215784; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc_lo15785; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415786; GFX10-NEXT: v_lshlrev_b32_e32 v14, 16, v515787; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v7, vcc_lo15788; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v1115789; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1015790; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v415791; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15792; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v1315793; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15794; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v1415795; GFX10-NEXT: v_cndmask_b32_e32 v8, v5, v10, vcc_lo15796; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v915797; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v4, vcc_lo15798; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v1215799; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo15800; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1015801; GFX10-NEXT: v_cndmask_b32_e32 v9, v8, v10, vcc_lo15802; GFX10-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v615803; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v715804; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v815805; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo15806; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v515807; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo15808; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v615809; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v315810; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v015811; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v4, vcc_lo15812; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v1015813; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v215814; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc_lo15815; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v115816; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v415817; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo15818; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v915819; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v615820; GFX10-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo15821; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v715822; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo15823; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v1015824; GFX10-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo15825; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115826; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo15827; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v015828; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo15829; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v315830; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15831; GFX10-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v215832; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v715833; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15834; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v915835; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v815836; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo15837; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v315838; GFX10-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo15839; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v215840; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x504010015841; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo15842; GFX10-NEXT: v_perm_b32 v1, v5, v1, 0x504010015843; GFX10-NEXT: s_setpc_b64 s[30:31]15844;15845; GFX11-TRUE16-LABEL: v_maximumnum_v4bf16_no_ieee:15846; GFX11-TRUE16: ; %bb.0:15847; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15848; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v115849; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v315850; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, 015851; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v015852; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v215853; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415854; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v515855; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l15856; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v315857; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo15858; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15859; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v915860; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v215861; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s015862; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15863; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15864; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v915865; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v515866; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo15867; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715868; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l15869; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)15870; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s015871; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l15872; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v815873; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v115874; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v615875; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo15876; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15877; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s015878; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15879; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v715880; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v7.h15881; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo15882; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v815883; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l15884; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)15885; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s015886; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l15887; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo15888; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v615889; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)15890; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v8.h, s215891; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8.h15892; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v015893; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v615894; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15895; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s015896; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h15897; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s215898; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v315899; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s415900; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)15901; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s015902; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l15903; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s215904; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l15905; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15906; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v615907; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s315908; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.h15909; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15910; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s015911; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v0, v615912; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15913; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s215914; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.h15915; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s315916; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v5.h15917; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15918; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s215919; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l15920; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v5.h, s315921; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15922; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v615923; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s115924; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo15925; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)15926; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s215927; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]15928;15929; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee:15930; GFX11-FAKE16: ; %bb.0:15931; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15932; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v115933; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v315934; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v115935; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v015936; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v115937; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v415938; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)15939; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v315940; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v715941; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v215942; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v015943; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)15944; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v415945; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo15946; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v515947; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)15948; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v1115949; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v215950; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v615951; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo15952; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v1215953; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15954; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v415955; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v315956; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v915957; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v015958; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v515959; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v215960; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)15961; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v715962; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v1415963; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo15964; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1015965; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15966; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v015967; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v815968; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v615969; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v1315970; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo15971; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)15972; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v915973; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v115974; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo15975; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v1515976; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v315977; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo15978; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v615979; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo15980; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)15981; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v815982; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v515983; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo15984; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v215985; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v715986; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo15987; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)15988; GFX11-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v1015989; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo15990; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v115991; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo15992; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v015993; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo15994; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v315995; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)15996; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo15997; GFX11-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v215998; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v715999; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v916000; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v816001; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)16002; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v316003; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo16004; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16005; GFX11-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v216006; GFX11-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x504010016007; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo16008; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)16009; GFX11-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x504010016010; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]16011;16012; GFX12-TRUE16-LABEL: v_maximumnum_v4bf16_no_ieee:16013; GFX12-TRUE16: ; %bb.0:16014; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x016015; GFX12-TRUE16-NEXT: s_wait_expcnt 0x016016; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x016017; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x016018; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x016019; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v116020; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v316021; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, 016022; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v016023; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v216024; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v416025; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v5, v516026; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l16027; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v316028; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)16029; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo16030; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)16031; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v916032; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v216033; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16034; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v3.h, v6.h, s016035; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h16036; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)16037; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v916038; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v516039; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)16040; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo16041; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v716042; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l16043; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16044; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)16045; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.h, v4.l, v6.h, s016046; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l16047; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v816048; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v116049; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v616050; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)16051; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo16052; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16053; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)16054; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v2.h, v6.h, s016055; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h16056; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v716057; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v7.h16058; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)16059; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo16060; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v816061; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v6.l16062; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16063; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)16064; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.h, s016065; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v5.l16066; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)16067; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo16068; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v616069; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)16070; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v3.l, v8.h, s216071; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v8.h16072; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v016073; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v8, v616074; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16075; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)16076; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v6.h, v8.h, s016077; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.h16078; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, v8.h, s216079; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v3, v316080; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v1.h, v7.h, s416081; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16082; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)16083; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.h, v6.h, s016084; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v1.l16085; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v2.l, s216086; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l16087; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v616088; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)16089; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v2.l, v0.h, s316090; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.h16091; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16092; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v2.h, s016093; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)16094; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v0, v616095; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16096; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v6.h, v0.h, s216097; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.h16098; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)16099; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, v0.h, s316100; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v5.h16101; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16102; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.h, v6.h, s216103; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l16104; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16105; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.h, v5.h, s316106; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v616107; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)16108; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v0.h, s116109; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)16110; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo16111; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)16112; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s216113; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]16114;16115; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16_no_ieee:16116; GFX12-FAKE16: ; %bb.0:16117; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x016118; GFX12-FAKE16-NEXT: s_wait_expcnt 0x016119; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x016120; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x016121; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x016122; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v116123; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v316124; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v116125; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v016126; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v116127; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v416128; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16129; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v316130; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)16131; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v716132; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v216133; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v016134; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v416135; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16136; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc_lo16137; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)16138; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v516139; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v1116140; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16141; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v216142; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v616143; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16144; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v7, vcc_lo16145; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v1216146; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16147; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo16148; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v416149; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16150; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v316151; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v916152; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16153; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v016154; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v516155; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v216156; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16157; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)16158; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v716159; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v1416160; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16161; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo16162; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1016163; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v016164; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)16165; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v816166; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16167; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v616168; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v1316169; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16170; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo16171; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)16172; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v916173; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v116174; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16175; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v6, vcc_lo16176; GFX12-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v1516177; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v316178; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16179; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo16180; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v616181; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16182; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc_lo16183; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v816184; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v516185; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16186; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v8, v3, v1, vcc_lo16187; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v216188; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v716189; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16190; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo16191; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)16192; GFX12-FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v1016193; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16194; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc_lo16195; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v116196; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16197; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo16198; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v016199; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16200; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo16201; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v316202; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16203; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo16204; GFX12-FAKE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v216205; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16206; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v716207; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v916208; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16209; GFX12-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v816210; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)16211; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v316212; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16213; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc_lo16214; GFX12-FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v216215; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)16216; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x504010016217; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)16218; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc_lo16219; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x504010016220; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]16221 %result = call <4 x bfloat> @llvm.maximumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)16222 ret <4 x bfloat> %result16223}16224 16225attributes #0 = { "amdgpu-ieee"="false" }16226;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:16227; GFX11: {{.*}}16228; GFX12: {{.*}}16229; GFX9: {{.*}}16230