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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare-disable-idiv-expansion < %s | FileCheck -check-prefixes=SI,SI-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti -amdgpu-codegenprepare-mul24=0 -amdgpu-codegenprepare-disable-idiv-expansion < %s | FileCheck -check-prefixes=SI,SI-GISEL %s4 5declare i32 @llvm.smin.i32(i32, i32)6declare i32 @llvm.smax.i32(i32, i32)7declare i32 @llvm.umin.i32(i32, i32)8declare i32 @llvm.umax.i32(i32, i32)9 10; Test computeKnownBits for umed3 node. We know the base address has a11; 0 sign bit only after umed3 is formed. The DS instruction offset can12; only be folded on SI with a positive base address.13define i32 @v_known_bits_umed3(i8 %a) {14; SI-LABEL: v_known_bits_umed3:15; SI: ; %bb.0:16; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17; SI-NEXT: v_and_b32_e32 v0, 0xff, v018; SI-NEXT: v_mov_b32_e32 v1, 0x8019; SI-NEXT: v_med3_u32 v0, v0, 32, v120; SI-NEXT: s_mov_b32 m0, -121; SI-NEXT: ds_read_u8 v0, v0 offset:12822; SI-NEXT: s_waitcnt lgkmcnt(0)23; SI-NEXT: s_setpc_b64 s[30:31]24 %ext.a = zext i8 %a to i3225 %max.a = call i32 @llvm.umax.i32(i32 %ext.a, i32 32)26 %umed3 = call i32 @llvm.umin.i32(i32 %max.a, i32 128)27 %cast.umed3 = inttoptr i32 %umed3 to ptr addrspace(3)28 %gep = getelementptr i8, ptr addrspace(3) %cast.umed3, i32 12829 %load = load i8, ptr addrspace(3) %gep30 %result = zext i8 %load to i3231 ret i32 %result32}33 34; The IR expansion of division is disabled. The division is legalized35; late, after the formation of smed3. We need to be able to36; computeNumSignBits on the smed3 in order to use the 24-bit-as-float37; sdiv legalization.38define i32 @v_known_signbits_smed3(i16 %a, i16 %b) {39; SI-SDAG-LABEL: v_known_signbits_smed3:40; SI-SDAG: ; %bb.0:41; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; SI-SDAG-NEXT: v_bfe_i32 v1, v1, 0, 1643; SI-SDAG-NEXT: s_movk_i32 s4, 0xffc044; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x8045; SI-SDAG-NEXT: v_med3_i32 v1, v1, s4, v246; SI-SDAG-NEXT: v_cvt_f32_i32_e32 v2, v147; SI-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 1648; SI-SDAG-NEXT: s_movk_i32 s4, 0xffe049; SI-SDAG-NEXT: v_med3_i32 v0, v0, s4, 6450; SI-SDAG-NEXT: v_cvt_f32_i32_e32 v3, v051; SI-SDAG-NEXT: v_rcp_iflag_f32_e32 v4, v252; SI-SDAG-NEXT: v_xor_b32_e32 v0, v0, v153; SI-SDAG-NEXT: v_ashrrev_i32_e32 v0, 30, v054; SI-SDAG-NEXT: v_or_b32_e32 v0, 1, v055; SI-SDAG-NEXT: v_mul_f32_e32 v1, v3, v456; SI-SDAG-NEXT: v_trunc_f32_e32 v1, v157; SI-SDAG-NEXT: v_mad_f32 v3, -v1, v2, v358; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v159; SI-SDAG-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2|60; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc61; SI-SDAG-NEXT: v_add_i32_e32 v0, vcc, v1, v062; SI-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 1663; SI-SDAG-NEXT: s_setpc_b64 s[30:31]64;65; SI-GISEL-LABEL: v_known_signbits_smed3:66; SI-GISEL: ; %bb.0:67; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; SI-GISEL-NEXT: v_bfe_i32 v1, v1, 0, 1669; SI-GISEL-NEXT: v_not_b32_e32 v2, 6370; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x8071; SI-GISEL-NEXT: v_med3_i32 v1, v1, v2, v372; SI-GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v173; SI-GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v274; SI-GISEL-NEXT: v_xor_b32_e32 v1, v1, v275; SI-GISEL-NEXT: v_cvt_f32_u32_e32 v3, v176; SI-GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v177; SI-GISEL-NEXT: v_not_b32_e32 v4, 3178; SI-GISEL-NEXT: v_rcp_iflag_f32_e32 v3, v379; SI-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 1680; SI-GISEL-NEXT: v_med3_i32 v0, v0, v4, 6481; SI-GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v082; SI-GISEL-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v383; SI-GISEL-NEXT: v_cvt_u32_f32_e32 v3, v384; SI-GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v485; SI-GISEL-NEXT: v_xor_b32_e32 v0, v0, v486; SI-GISEL-NEXT: v_mul_lo_u32 v5, v5, v387; SI-GISEL-NEXT: v_mul_hi_u32 v5, v3, v588; SI-GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v589; SI-GISEL-NEXT: v_mul_hi_u32 v3, v0, v390; SI-GISEL-NEXT: v_mul_lo_u32 v5, v3, v191; SI-GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v392; SI-GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v593; SI-GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v194; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc95; SI-GISEL-NEXT: v_sub_i32_e64 v5, s[4:5], v0, v196; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc97; SI-GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v398; SI-GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v199; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc100; SI-GISEL-NEXT: v_xor_b32_e32 v1, v4, v2101; SI-GISEL-NEXT: v_xor_b32_e32 v0, v0, v1102; SI-GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v1103; SI-GISEL-NEXT: s_setpc_b64 s[30:31]104 %ext.a = sext i16 %a to i32105 %max.a = call i32 @llvm.smax.i32(i32 %ext.a, i32 -32)106 %smed3.a = call i32 @llvm.smin.i32(i32 %max.a, i32 64)107 %ext.b = sext i16 %b to i32108 %max.b = call i32 @llvm.smax.i32(i32 %ext.b, i32 -64)109 %smed3.b = call i32 @llvm.smin.i32(i32 %max.b, i32 128)110 %mul = sdiv i32 %smed3.a, %smed3.b111 ret i32 %mul112}113