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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefix=GFX12 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250 %s5 6define amdgpu_kernel void @global_last_use_load_0(ptr addrspace(1) %in, ptr addrspace(1) %out) {7; GFX12-LABEL: global_last_use_load_0:8; GFX12: ; %bb.0: ; %entry9; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x010; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x811; GFX12-NEXT: v_mov_b32_e32 v0, 012; GFX12-NEXT: s_wait_kmcnt 0x013; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x014; GFX12-NEXT: s_wait_kmcnt 0x015; GFX12-NEXT: v_mov_b32_e32 v1, s216; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]17; GFX12-NEXT: s_endpgm18;19; GFX1250-LABEL: global_last_use_load_0:20; GFX1250: ; %bb.0: ; %entry21; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 122; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x023; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x824; GFX1250-NEXT: v_mov_b32_e32 v0, 025; GFX1250-NEXT: s_wait_kmcnt 0x026; GFX1250-NEXT: s_load_b32 s2, s[2:3], 0x027; GFX1250-NEXT: s_wait_kmcnt 0x028; GFX1250-NEXT: v_mov_b32_e32 v1, s229; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]30; GFX1250-NEXT: s_endpgm31entry:32 %val = load i32, ptr addrspace(1) %in, align 4, !amdgpu.last.use !{}33 store i32 %val, ptr addrspace(1) %out34 ret void35}36 37define amdgpu_kernel void @global_last_use_load_1(ptr addrspace(1) %in, ptr addrspace(1) %out) {38; GFX12-LABEL: global_last_use_load_1:39; GFX12: ; %bb.0: ; %entry40; GFX12-NEXT: v_mov_b32_e32 v1, v041; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x042; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x843; GFX12-NEXT: v_mov_b32_e32 v0, 044; GFX12-NEXT: s_mov_b32 s4, 0x3ff45; GFX12-NEXT: v_and_b32_e64 v1, v1, s446; GFX12-NEXT: s_mov_b32 s4, 247; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)48; GFX12-NEXT: v_lshlrev_b32_e64 v1, s4, v149; GFX12-NEXT: s_wait_kmcnt 0x050; GFX12-NEXT: global_load_b32 v1, v1, s[2:3] th:TH_LOAD_LU51; GFX12-NEXT: s_wait_loadcnt 0x052; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]53; GFX12-NEXT: s_endpgm54;55; GFX1250-LABEL: global_last_use_load_1:56; GFX1250: ; %bb.0: ; %entry57; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 158; GFX1250-NEXT: v_mov_b32_e32 v1, v059; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x060; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x861; GFX1250-NEXT: v_mov_b32_e32 v0, 062; GFX1250-NEXT: s_wait_xcnt 0x063; GFX1250-NEXT: s_mov_b32 s4, 0x3ff64; GFX1250-NEXT: v_and_b32_e64 v1, v1, s465; GFX1250-NEXT: s_wait_kmcnt 0x066; GFX1250-NEXT: global_load_b32 v1, v1, s[2:3] scale_offset th:TH_LOAD_LU67; GFX1250-NEXT: s_wait_loadcnt 0x068; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]69; GFX1250-NEXT: s_endpgm70entry:71 %tid = call i32 @llvm.amdgcn.workitem.id.x()72 %val.gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid73 %val = load i32, ptr addrspace(1) %val.gep, align 4, !amdgpu.last.use !{}74 store i32 %val, ptr addrspace(1) %out75 ret void76}77 78define amdgpu_kernel void @global_last_use_and_volatile_load(ptr addrspace(1) %in, ptr addrspace(1) %out) {79; GFX12-LABEL: global_last_use_and_volatile_load:80; GFX12: ; %bb.0: ; %entry81; GFX12-NEXT: v_mov_b32_e32 v0, 082; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x083; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x884; GFX12-NEXT: s_wait_kmcnt 0x085; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] th:TH_LOAD_BYPASS scope:SCOPE_SYS86; GFX12-NEXT: s_wait_bvhcnt 0x087; GFX12-NEXT: s_wait_samplecnt 0x088; GFX12-NEXT: s_wait_loadcnt 0x089; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]90; GFX12-NEXT: s_endpgm91;92; GFX1250-LABEL: global_last_use_and_volatile_load:93; GFX1250: ; %bb.0: ; %entry94; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 195; GFX1250-NEXT: v_mov_b32_e32 v0, 096; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x097; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x898; GFX1250-NEXT: s_wait_xcnt 0x099; GFX1250-NEXT: s_wait_kmcnt 0x0100; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] th:TH_LOAD_BYPASS scope:SCOPE_SYS101; GFX1250-NEXT: s_wait_loadcnt 0x0102; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]103; GFX1250-NEXT: s_endpgm104entry:105 %val = load volatile i32, ptr addrspace(1) %in, align 4, !amdgpu.last.use !{}106 store i32 %val, ptr addrspace(1) %out107 ret void108}109 110define amdgpu_kernel void @global_last_use_and_nontemporal_load(ptr addrspace(1) %in, ptr addrspace(1) %out) {111; GFX12-LABEL: global_last_use_and_nontemporal_load:112; GFX12: ; %bb.0: ; %entry113; GFX12-NEXT: v_mov_b32_e32 v1, v0114; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x0115; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x8116; GFX12-NEXT: v_mov_b32_e32 v0, 0117; GFX12-NEXT: s_mov_b32 s4, 0x3ff118; GFX12-NEXT: v_and_b32_e64 v1, v1, s4119; GFX12-NEXT: s_mov_b32 s4, 2120; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)121; GFX12-NEXT: v_lshlrev_b32_e64 v1, s4, v1122; GFX12-NEXT: s_wait_kmcnt 0x0123; GFX12-NEXT: global_load_b32 v1, v1, s[2:3] th:TH_LOAD_LU124; GFX12-NEXT: s_wait_loadcnt 0x0125; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]126; GFX12-NEXT: s_endpgm127;128; GFX1250-LABEL: global_last_use_and_nontemporal_load:129; GFX1250: ; %bb.0: ; %entry130; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1131; GFX1250-NEXT: v_mov_b32_e32 v1, v0132; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x0133; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8134; GFX1250-NEXT: v_mov_b32_e32 v0, 0135; GFX1250-NEXT: s_wait_xcnt 0x0136; GFX1250-NEXT: s_mov_b32 s4, 0x3ff137; GFX1250-NEXT: v_and_b32_e64 v1, v1, s4138; GFX1250-NEXT: s_wait_kmcnt 0x0139; GFX1250-NEXT: global_load_b32 v1, v1, s[2:3] scale_offset th:TH_LOAD_LU140; GFX1250-NEXT: s_wait_loadcnt 0x0141; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]142; GFX1250-NEXT: s_endpgm143entry:144 %tid = call i32 @llvm.amdgcn.workitem.id.x()145 %val.gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid146 %val = load i32, ptr addrspace(1) %val.gep, align 4, !amdgpu.last.use !{}, !nontemporal !0147 store i32 %val, ptr addrspace(1) %out148 ret void149}150!0 = !{i32 1}151declare i32 @llvm.amdgcn.workitem.id.x()152