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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefix=GFX12 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250 %s5 6define amdgpu_kernel void @private_last_use_load_0(ptr addrspace(5) %in, ptr addrspace(1) %out) {7; GFX12-LABEL: private_last_use_load_0:8; GFX12: ; %bb.0: ; %entry9; GFX12-NEXT: s_load_b32 s2, s[4:5], 0x010; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x811; GFX12-NEXT: v_mov_b32_e32 v0, 012; GFX12-NEXT: s_wait_kmcnt 0x013; GFX12-NEXT: scratch_load_b32 v1, off, s2 th:TH_LOAD_LU14; GFX12-NEXT: s_wait_loadcnt 0x015; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]16; GFX12-NEXT: s_endpgm17;18; GFX1250-LABEL: private_last_use_load_0:19; GFX1250: ; %bb.0: ; %entry20; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 121; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x022; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x823; GFX1250-NEXT: v_mov_b32_e32 v0, 024; GFX1250-NEXT: s_wait_kmcnt 0x025; GFX1250-NEXT: scratch_load_b32 v1, off, s2 th:TH_LOAD_LU26; GFX1250-NEXT: s_wait_loadcnt 0x027; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]28; GFX1250-NEXT: s_endpgm29entry:30 %val = load i32, ptr addrspace(5) %in, align 4, !amdgpu.last.use !{}31 store i32 %val, ptr addrspace(1) %out32 ret void33}34 35define amdgpu_kernel void @private_last_use_load_1(ptr addrspace(5) %in, ptr addrspace(1) %out) {36; GFX12-LABEL: private_last_use_load_1:37; GFX12: ; %bb.0: ; %entry38; GFX12-NEXT: v_mov_b32_e32 v1, v039; GFX12-NEXT: s_load_b32 s2, s[4:5], 0x040; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x841; GFX12-NEXT: v_mov_b32_e32 v0, 042; GFX12-NEXT: s_mov_b32 s3, 0x3ff43; GFX12-NEXT: v_and_b32_e64 v1, v1, s344; GFX12-NEXT: s_mov_b32 s3, 245; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)46; GFX12-NEXT: v_lshlrev_b32_e64 v1, s3, v147; GFX12-NEXT: s_wait_kmcnt 0x048; GFX12-NEXT: scratch_load_b32 v1, v1, s2 th:TH_LOAD_LU49; GFX12-NEXT: s_wait_loadcnt 0x050; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]51; GFX12-NEXT: s_endpgm52;53; GFX1250-LABEL: private_last_use_load_1:54; GFX1250: ; %bb.0: ; %entry55; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 156; GFX1250-NEXT: v_mov_b32_e32 v1, v057; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x058; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x859; GFX1250-NEXT: v_mov_b32_e32 v0, 060; GFX1250-NEXT: s_mov_b32 s3, 0x3ff61; GFX1250-NEXT: v_and_b32_e64 v1, v1, s362; GFX1250-NEXT: s_wait_kmcnt 0x063; GFX1250-NEXT: scratch_load_b32 v1, v1, s2 scale_offset th:TH_LOAD_LU64; GFX1250-NEXT: s_wait_loadcnt 0x065; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]66; GFX1250-NEXT: s_endpgm67entry:68 %tid = call i32 @llvm.amdgcn.workitem.id.x()69 %val.gep = getelementptr inbounds i32, ptr addrspace(5) %in, i32 %tid70 %val = load i32, ptr addrspace(5) %val.gep, align 4, !amdgpu.last.use !{}71 store i32 %val, ptr addrspace(1) %out72 ret void73}74 75define amdgpu_kernel void @private_last_use_and_volatile_load(ptr addrspace(5) %in, ptr addrspace(1) %out) {76; GFX12-LABEL: private_last_use_and_volatile_load:77; GFX12: ; %bb.0: ; %entry78; GFX12-NEXT: s_load_b32 s2, s[4:5], 0x079; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x880; GFX12-NEXT: v_mov_b32_e32 v0, 081; GFX12-NEXT: s_wait_kmcnt 0x082; GFX12-NEXT: scratch_load_b32 v1, off, s2 th:TH_LOAD_BYPASS scope:SCOPE_SYS83; GFX12-NEXT: s_wait_bvhcnt 0x084; GFX12-NEXT: s_wait_samplecnt 0x085; GFX12-NEXT: s_wait_loadcnt 0x086; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]87; GFX12-NEXT: s_endpgm88;89; GFX1250-LABEL: private_last_use_and_volatile_load:90; GFX1250: ; %bb.0: ; %entry91; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 192; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x093; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x894; GFX1250-NEXT: v_mov_b32_e32 v0, 095; GFX1250-NEXT: s_wait_xcnt 0x096; GFX1250-NEXT: s_wait_kmcnt 0x097; GFX1250-NEXT: scratch_load_b32 v1, off, s2 th:TH_LOAD_BYPASS scope:SCOPE_SYS98; GFX1250-NEXT: s_wait_loadcnt 0x099; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]100; GFX1250-NEXT: s_endpgm101entry:102 %val = load volatile i32, ptr addrspace(5) %in, align 4, !amdgpu.last.use !{}103 store i32 %val, ptr addrspace(1) %out104 ret void105}106 107define amdgpu_kernel void @private_last_use_and_nontemporal_load(ptr addrspace(5) %in, ptr addrspace(1) %out) {108; GFX12-LABEL: private_last_use_and_nontemporal_load:109; GFX12: ; %bb.0: ; %entry110; GFX12-NEXT: s_load_b32 s2, s[4:5], 0x0111; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x8112; GFX12-NEXT: v_mov_b32_e32 v0, 0113; GFX12-NEXT: s_wait_kmcnt 0x0114; GFX12-NEXT: scratch_load_b32 v1, off, s2 th:TH_LOAD_LU115; GFX12-NEXT: s_wait_loadcnt 0x0116; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]117; GFX12-NEXT: s_endpgm118;119; GFX1250-LABEL: private_last_use_and_nontemporal_load:120; GFX1250: ; %bb.0: ; %entry121; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1122; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x0123; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x8124; GFX1250-NEXT: v_mov_b32_e32 v0, 0125; GFX1250-NEXT: s_wait_kmcnt 0x0126; GFX1250-NEXT: scratch_load_b32 v1, off, s2 th:TH_LOAD_LU127; GFX1250-NEXT: s_wait_loadcnt 0x0128; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]129; GFX1250-NEXT: s_endpgm130entry:131 %val = load i32, ptr addrspace(5) %in, align 4, !amdgpu.last.use !{}, !nontemporal !0132 store i32 %val, ptr addrspace(1) %out133 ret void134}135 136!0 = !{i32 1}137declare i32 @llvm.amdgcn.workitem.id.x()138