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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s3 4; Effectively, check that the compile finishes; in the case5; of an infinite loop, llc toggles between merging 2 ST4s6; ( MergeConsecutiveStores() ) and breaking the resulting ST87; apart ( LegalizeStoreOps() ).8 9define amdgpu_kernel void @_Z6brokenPd(ptr %arg) {10; GCN-LABEL: _Z6brokenPd:11; GCN: ; %bb.0: ; %bb12; GCN-NEXT: s_mov_b32 flat_scratch_lo, s1313; GCN-NEXT: s_add_i32 s12, s12, s1714; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 815; GCN-NEXT: s_add_u32 s0, s0, s1716; GCN-NEXT: s_addc_u32 s1, s1, 017; GCN-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x018; GCN-NEXT: v_mov_b32_e32 v2, 019; GCN-NEXT: v_mov_b32_e32 v3, 0x7ff8000020; GCN-NEXT: s_waitcnt lgkmcnt(0)21; GCN-NEXT: v_mov_b32_e32 v0, s422; GCN-NEXT: v_mov_b32_e32 v1, s523; GCN-NEXT: s_add_u32 s4, s4, 424; GCN-NEXT: s_addc_u32 s5, s5, 025; GCN-NEXT: flat_store_dword v[0:1], v226; GCN-NEXT: v_mov_b32_e32 v0, s427; GCN-NEXT: v_mov_b32_e32 v1, s528; GCN-NEXT: flat_store_dword v[0:1], v329; GCN-NEXT: s_endpgm30bb:31 %tmp = alloca double, align 8, addrspace(5)32 %tmp1 = alloca double, align 8, addrspace(5)33 %tmp2 = load double, ptr %arg, align 834 br i1 1, label %bb6, label %bb435 36bb3: ; No predecessors!37 br label %bb438 39bb4: ; preds = %bb3, %bb40 %tmp5 = phi ptr addrspace(5) [ %tmp1, %bb3 ], [ %tmp, %bb ]41 store double %tmp2, ptr addrspace(5) %tmp5, align 842 br label %bb643 44bb6: ; preds = %bb4, %bb45 %tmp7 = phi double [ 0x7FF8123000000000, %bb4 ], [ 0x7FF8000000000000, %bb ]46 store double %tmp7, ptr %arg, align 847 ret void48}49