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1# RUN: llc -mtriple=amdgcn -mcpu=gfx803 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,VI %s2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefixes=GCN,GFX9 %s3 4# If there's a base offset, check that SILoadStoreOptimizer creates5# V_ADD_{I|U}32_e64 for that offset; _e64 uses a vreg for the carry (rather than6# $vcc, which is used in _e32); this ensures that $vcc is not inadvertently7# clobbered.8 9# GCN-LABEL: name: ds_combine_base_offset{{$}}10 11# VI: V_ADD_CO_U32_e64 %6, %0,12# VI-NEXT: DS_WRITE2_B32 killed %7, %0, %3, 0, 8,13# VI: V_ADD_CO_U32_e64 %10, %3,14# VI-NEXT: DS_READ2_B32 killed %11, 16, 24,15 16# GFX9: V_ADD_U32_e64 %6, %0,17# GFX9-NEXT: DS_WRITE2_B32_gfx9 killed %7, %0, %3, 0, 8,18# GFX9: V_ADD_U32_e64 %9, %3,19# GFX9-NEXT: DS_READ2_B32_gfx9 killed %10, 16, 24,20 21--- |22 @0 = internal unnamed_addr addrspace(3) global [256 x float] poison, align 423 24 define amdgpu_kernel void @ds_combine_base_offset() {25 bb.0:26 br label %bb227 28 bb1:29 ret void30 31 bb2:32 %tmp = getelementptr inbounds [256 x float], ptr addrspace(3) @0, i32 0, i32 033 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 834 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 1635 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 2436 br label %bb137 }38 39 define amdgpu_kernel void @ds_combine_base_offset_subreg() {40 bb.0:41 br label %bb242 43 bb1:44 ret void45 46 bb2:47 %tmp = getelementptr inbounds [256 x float], ptr addrspace(3) @0, i32 0, i32 048 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 849 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 1650 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 2451 br label %bb152 }53 54 define amdgpu_kernel void @ds_combine_subreg() {55 bb.0:56 br label %bb257 58 bb1:59 ret void60 61 bb2:62 %tmp = getelementptr inbounds [256 x float], ptr addrspace(3) @0, i32 0, i32 063 %tmp1 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 864 %tmp2 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 1665 %tmp3 = getelementptr inbounds float, ptr addrspace(3) %tmp, i32 2466 br label %bb167 }68---69name: ds_combine_base_offset70body: |71 bb.0:72 %0:vgpr_32 = IMPLICIT_DEF73 S_BRANCH %bb.274 75 bb.1:76 S_ENDPGM 077 78 bb.2:79 %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0, 0, implicit $exec80 %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %1, implicit $exec81 V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec82 DS_WRITE_B32 %0, %0, 1024, 0, implicit $m0, implicit $exec :: (store (s32) into %ir.tmp)83 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec84 DS_WRITE_B32 %0, %3, 1056, 0, implicit $m0, implicit $exec :: (store (s32) into %ir.tmp1)85 %4:vgpr_32 = DS_READ_B32 %3, 1088, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp2)86 %5:vgpr_32 = DS_READ_B32 %3, 1120, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp3)87 $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc88 S_CBRANCH_VCCNZ %bb.1, implicit $vcc89 S_BRANCH %bb.190...91 92# GCN-LABEL: name: ds_combine_base_offset_subreg{{$}}93 94# VI: V_ADD_CO_U32_e64 %6, %0.sub0,95# VI-NEXT: DS_WRITE2_B32 killed %7, %0.sub0, %3.sub0, 0, 8,96# VI: V_ADD_CO_U32_e64 %10, %3.sub0,97# VI-NEXT: DS_READ2_B32 killed %11, 16, 24,98 99# GFX9: V_ADD_U32_e64 %6, %0.sub0,100# GFX9-NEXT: DS_WRITE2_B32_gfx9 killed %7, %0.sub0, %3.sub0, 0, 8,101# GFX9: V_ADD_U32_e64 %9, %3.sub0,102# GFX9-NEXT: DS_READ2_B32_gfx9 killed %10, 16, 24,103---104name: ds_combine_base_offset_subreg105body: |106 bb.0:107 %0:vreg_64 = IMPLICIT_DEF108 S_BRANCH %bb.2109 110 bb.1:111 S_ENDPGM 0112 113 bb.2:114 %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec115 %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %1, implicit $exec116 V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec117 DS_WRITE_B32 %0.sub0, %0.sub0, 1024, 0, implicit $m0, implicit $exec :: (store (s32) into %ir.tmp)118 %3:vreg_64 = V_LSHLREV_B64_e64 0, 0, implicit $exec119 DS_WRITE_B32 %0.sub0, %3.sub0, 1056, 0, implicit $m0, implicit $exec :: (store (s32) into %ir.tmp1)120 %4:vgpr_32 = DS_READ_B32 %3.sub0, 1088, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp2)121 %5:vgpr_32 = DS_READ_B32 %3.sub0, 1120, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp3)122 $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc123 S_CBRANCH_VCCNZ %bb.1, implicit $vcc124 S_BRANCH %bb.1125...126 127# GCN-LABEL: name: ds_combine_subreg{{$}}128 129# VI: DS_WRITE2_B32 %0.sub0, %0.sub0, %3.sub0, 0, 8,130# VI: DS_READ2_B32 %3.sub0, 0, 8,131 132# GFX9: DS_WRITE2_B32_gfx9 %0.sub0, %0.sub0, %3.sub0, 0, 8,133# GFX9: DS_READ2_B32_gfx9 %3.sub0, 0, 8,134---135name: ds_combine_subreg136body: |137 bb.0:138 %0:vreg_64 = IMPLICIT_DEF139 S_BRANCH %bb.2140 141 bb.1:142 S_ENDPGM 0143 144 bb.2:145 %1:sreg_64_xexec = V_CMP_NE_U32_e64 %0.sub0, 0, implicit $exec146 %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %1, implicit $exec147 V_CMP_NE_U32_e32 1, %2, implicit-def $vcc, implicit $exec148 DS_WRITE_B32 %0.sub0, %0.sub0, 0, 0, implicit $m0, implicit $exec :: (store (s32) into %ir.tmp)149 %3:vreg_64 = V_LSHLREV_B64_e64 0, 0, implicit $exec150 DS_WRITE_B32 %0.sub0, %3.sub0, 32, 0, implicit $m0, implicit $exec :: (store (s32) into %ir.tmp1)151 %4:vgpr_32 = DS_READ_B32 %3.sub0, 0, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp2)152 %5:vgpr_32 = DS_READ_B32 %3.sub0, 32, 0, implicit $m0, implicit $exec :: (load (s32) from %ir.tmp3)153 $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc154 S_CBRANCH_VCCNZ %bb.1, implicit $vcc155 S_BRANCH %bb.1156...157