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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -O3 -mtriple=amdgcn -mcpu=fiji %s -o - | FileCheck %s3 4define i1 @basic_eq_i16_3x5(i16 %arg) {5; CHECK-LABEL: basic_eq_i16_3x5:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v09; CHECK-NEXT: v_cmp_eq_u16_e32 vcc, 0, v010; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc11; CHECK-NEXT: s_setpc_b64 s[30:31]12entry:13 %a = and i16 %arg, 3114 %sh5 = lshr i16 %arg, 515 %b = and i16 %sh5, 3116 %or = or i16 %a, %b17 %sh10 = lshr i16 %arg, 1018 %c = and i16 %sh10, 3119 %or1 = or i16 %or, %c20 %cmp = icmp eq i16 %or1, 021 ret i1 %cmp22}23 24define i1 @basic_eq_i32_3x5(i32 %arg) {25; CHECK-LABEL: basic_eq_i32_3x5:26; CHECK: ; %bb.0: ; %entry27; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)28; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v029; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v030; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc31; CHECK-NEXT: s_setpc_b64 s[30:31]32entry:33 %a = and i32 %arg, 3134 %sh5 = lshr i32 %arg, 535 %b = and i32 %sh5, 3136 %or = or i32 %a, %b37 %sh10 = lshr i32 %arg, 1038 %c = and i32 %sh10, 3139 %or1 = or i32 %or, %c40 %cmp = icmp eq i32 %or1, 041 ret i1 %cmp42}43 44define i1 @basic_eq_i64_3x5(i64 %arg) {45; CHECK-LABEL: basic_eq_i64_3x5:46; CHECK: ; %bb.0: ; %entry47; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v049; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v050; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc51; CHECK-NEXT: s_setpc_b64 s[30:31]52entry:53 %a = and i64 %arg, 3154 %sh5 = lshr i64 %arg, 555 %b = and i64 %sh5, 3156 %or = or i64 %a, %b57 %sh10 = lshr i64 %arg, 1058 %c = and i64 %sh10, 3159 %or1 = or i64 %or, %c60 %cmp = icmp eq i64 %or1, 061 ret i1 %cmp62}63 64define i1 @basic_ne_i32_3x5(i32 %arg) {65; CHECK-LABEL: basic_ne_i32_3x5:66; CHECK: ; %bb.0: ; %entry67; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v069; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v070; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc71; CHECK-NEXT: s_setpc_b64 s[30:31]72entry:73 %a = and i32 %arg, 3174 %sh5 = lshr i32 %arg, 575 %b = and i32 %sh5, 3176 %or = or i32 %a, %b77 %sh10 = lshr i32 %arg, 1078 %c = and i32 %sh10, 3179 %or1 = or i32 %or, %c80 %cmp = icmp ne i32 %or1, 081 ret i1 %cmp82}83 84define i1 @eq_i32_3x5_holes_in_mask(i32 %arg) {85; CHECK-LABEL: eq_i32_3x5_holes_in_mask:86; CHECK: ; %bb.0: ; %entry87; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)88; CHECK-NEXT: v_and_b32_e32 v0, 0x7f9f, v089; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v090; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc91; CHECK-NEXT: s_setpc_b64 s[30:31]92entry:93 %a = and i32 %arg, 3194 %sh5 = lshr i32 %arg, 795 %b = and i32 %sh5, 3196 %or = or i32 %a, %b97 %sh10 = lshr i32 %arg, 1098 %c = and i32 %sh10, 3199 %or1 = or i32 %or, %c100 %cmp = icmp ne i32 %or1, 0101 ret i1 %cmp102}103 104define i1 @eq_i32_3x5_all_shifted(i32 %arg) {105; CHECK-LABEL: eq_i32_3x5_all_shifted:106; CHECK: ; %bb.0: ; %entry107; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; CHECK-NEXT: v_and_b32_e32 v0, 0x7ffc, v0109; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0110; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc111; CHECK-NEXT: s_setpc_b64 s[30:31]112entry:113 %sh2 = lshr i32 %arg, 2114 %a = and i32 %sh2, 31115 %sh5 = lshr i32 %arg, 7116 %b = and i32 %sh5, 31117 %or = or i32 %a, %b118 %sh10 = lshr i32 %arg, 10119 %c = and i32 %sh10, 31120 %or1 = or i32 %or, %c121 %cmp = icmp ne i32 %or1, 0122 ret i1 %cmp123}124