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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck --check-prefix=EG %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefix=CI %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck --check-prefix=VI %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s8; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s9; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-TRUE16 %s10; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-FAKE16 %s11 12define amdgpu_kernel void @v_test_imin_sle_i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {13; EG-LABEL: v_test_imin_sle_i32:14; EG: ; %bb.0:15; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]16; EG-NEXT: TEX 1 @617; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[]18; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 119; EG-NEXT: CF_END20; EG-NEXT: PAD21; EG-NEXT: Fetch clause starting at 6:22; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #123; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #124; EG-NEXT: ALU clause starting at 10:25; EG-NEXT: LSHL * T0.W, T0.X, literal.x,26; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)27; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,28; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,29; EG-NEXT: ALU clause starting at 14:30; EG-NEXT: MIN_INT T0.X, T0.X, T1.X,31; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,32; EG-NEXT: LSHR * T1.X, PV.W, literal.x,33; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)34;35; CI-LABEL: v_test_imin_sle_i32:36; CI: ; %bb.0:37; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x038; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x439; CI-NEXT: v_lshlrev_b32_e32 v4, 2, v040; CI-NEXT: s_add_i32 s12, s12, s1741; CI-NEXT: s_mov_b32 flat_scratch_lo, s1342; CI-NEXT: s_waitcnt lgkmcnt(0)43; CI-NEXT: v_mov_b32_e32 v1, s344; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v445; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc46; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 847; CI-NEXT: v_mov_b32_e32 v3, s548; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v449; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc50; CI-NEXT: flat_load_dword v5, v[0:1]51; CI-NEXT: flat_load_dword v2, v[2:3]52; CI-NEXT: v_mov_b32_e32 v1, s153; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v454; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc55; CI-NEXT: s_waitcnt vmcnt(0)56; CI-NEXT: v_min_i32_e32 v2, v5, v257; CI-NEXT: flat_store_dword v[0:1], v258; CI-NEXT: s_endpgm59;60; VI-LABEL: v_test_imin_sle_i32:61; VI: ; %bb.0:62; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x063; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x1064; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v065; VI-NEXT: s_add_i32 s12, s12, s1766; VI-NEXT: s_mov_b32 flat_scratch_lo, s1367; VI-NEXT: s_waitcnt lgkmcnt(0)68; VI-NEXT: v_mov_b32_e32 v1, s369; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v470; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc71; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 872; VI-NEXT: v_mov_b32_e32 v3, s573; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v474; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc75; VI-NEXT: flat_load_dword v5, v[0:1]76; VI-NEXT: flat_load_dword v2, v[2:3]77; VI-NEXT: v_mov_b32_e32 v1, s178; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v479; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc80; VI-NEXT: s_waitcnt vmcnt(0)81; VI-NEXT: v_min_i32_e32 v2, v5, v282; VI-NEXT: flat_store_dword v[0:1], v283; VI-NEXT: s_endpgm84;85; GFX9-LABEL: v_test_imin_sle_i32:86; GFX9: ; %bb.0:87; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x088; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x1089; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v090; GFX9-NEXT: s_waitcnt lgkmcnt(0)91; GFX9-NEXT: global_load_dword v1, v0, s[2:3]92; GFX9-NEXT: global_load_dword v2, v0, s[4:5]93; GFX9-NEXT: s_waitcnt vmcnt(0)94; GFX9-NEXT: v_min_i32_e32 v1, v1, v295; GFX9-NEXT: global_store_dword v0, v1, s[0:1]96; GFX9-NEXT: s_endpgm97;98; GFX10-LABEL: v_test_imin_sle_i32:99; GFX10: ; %bb.0:100; GFX10-NEXT: s_clause 0x1101; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0102; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10103; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0104; GFX10-NEXT: s_waitcnt lgkmcnt(0)105; GFX10-NEXT: s_clause 0x1106; GFX10-NEXT: global_load_dword v1, v0, s[2:3]107; GFX10-NEXT: global_load_dword v2, v0, s[4:5]108; GFX10-NEXT: s_waitcnt vmcnt(0)109; GFX10-NEXT: v_min_i32_e32 v1, v1, v2110; GFX10-NEXT: global_store_dword v0, v1, s[0:1]111; GFX10-NEXT: s_endpgm112;113; GFX11-LABEL: v_test_imin_sle_i32:114; GFX11: ; %bb.0:115; GFX11-NEXT: s_clause 0x1116; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0117; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x10118; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0119; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)120; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0121; GFX11-NEXT: s_waitcnt lgkmcnt(0)122; GFX11-NEXT: s_clause 0x1123; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]124; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]125; GFX11-NEXT: s_waitcnt vmcnt(0)126; GFX11-NEXT: v_min_i32_e32 v1, v1, v2127; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]128; GFX11-NEXT: s_endpgm129;130; GFX1250-LABEL: v_test_imin_sle_i32:131; GFX1250: ; %bb.0:132; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1133; GFX1250-NEXT: s_clause 0x1134; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0135; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x10136; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0137; GFX1250-NEXT: s_wait_kmcnt 0x0138; GFX1250-NEXT: s_clause 0x1139; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset140; GFX1250-NEXT: global_load_b32 v2, v0, s[6:7] scale_offset141; GFX1250-NEXT: s_wait_loadcnt 0x0142; GFX1250-NEXT: v_min_i32_e32 v1, v1, v2143; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset144; GFX1250-NEXT: s_endpgm145 %tid = call i32 @llvm.amdgcn.workitem.id.x()146 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i32 %tid147 %b.gep = getelementptr inbounds i32, ptr addrspace(1) %b.ptr, i32 %tid148 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid149 %a = load i32, ptr addrspace(1) %a.gep, align 4150 %b = load i32, ptr addrspace(1) %b.gep, align 4151 %cmp = icmp sle i32 %a, %b152 %val = select i1 %cmp, i32 %a, i32 %b153 store i32 %val, ptr addrspace(1) %out.gep, align 4154 ret void155}156 157define amdgpu_kernel void @s_test_imin_sle_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {158; EG-LABEL: s_test_imin_sle_i32:159; EG: ; %bb.0:160; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]161; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1162; EG-NEXT: CF_END163; EG-NEXT: PAD164; EG-NEXT: ALU clause starting at 4:165; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,166; EG-NEXT: MIN_INT * T1.X, KC0[2].Z, KC0[2].W,167; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)168;169; CI-LABEL: s_test_imin_sle_i32:170; CI: ; %bb.0:171; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0172; CI-NEXT: s_add_i32 s12, s12, s17173; CI-NEXT: s_mov_b32 flat_scratch_lo, s13174; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8175; CI-NEXT: s_waitcnt lgkmcnt(0)176; CI-NEXT: s_min_i32 s2, s2, s3177; CI-NEXT: v_mov_b32_e32 v0, s0178; CI-NEXT: v_mov_b32_e32 v1, s1179; CI-NEXT: v_mov_b32_e32 v2, s2180; CI-NEXT: flat_store_dword v[0:1], v2181; CI-NEXT: s_endpgm182;183; VI-LABEL: s_test_imin_sle_i32:184; VI: ; %bb.0:185; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0186; VI-NEXT: s_add_i32 s12, s12, s17187; VI-NEXT: s_mov_b32 flat_scratch_lo, s13188; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8189; VI-NEXT: s_waitcnt lgkmcnt(0)190; VI-NEXT: s_min_i32 s2, s2, s3191; VI-NEXT: v_mov_b32_e32 v0, s0192; VI-NEXT: v_mov_b32_e32 v1, s1193; VI-NEXT: v_mov_b32_e32 v2, s2194; VI-NEXT: flat_store_dword v[0:1], v2195; VI-NEXT: s_endpgm196;197; GFX9-LABEL: s_test_imin_sle_i32:198; GFX9: ; %bb.0:199; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0200; GFX9-NEXT: v_mov_b32_e32 v0, 0201; GFX9-NEXT: s_waitcnt lgkmcnt(0)202; GFX9-NEXT: s_min_i32 s2, s2, s3203; GFX9-NEXT: v_mov_b32_e32 v1, s2204; GFX9-NEXT: global_store_dword v0, v1, s[0:1]205; GFX9-NEXT: s_endpgm206;207; GFX10-LABEL: s_test_imin_sle_i32:208; GFX10: ; %bb.0:209; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0210; GFX10-NEXT: v_mov_b32_e32 v0, 0211; GFX10-NEXT: s_waitcnt lgkmcnt(0)212; GFX10-NEXT: s_min_i32 s2, s2, s3213; GFX10-NEXT: v_mov_b32_e32 v1, s2214; GFX10-NEXT: global_store_dword v0, v1, s[0:1]215; GFX10-NEXT: s_endpgm216;217; GFX11-LABEL: s_test_imin_sle_i32:218; GFX11: ; %bb.0:219; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0220; GFX11-NEXT: v_mov_b32_e32 v0, 0221; GFX11-NEXT: s_waitcnt lgkmcnt(0)222; GFX11-NEXT: s_min_i32 s2, s2, s3223; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)224; GFX11-NEXT: v_mov_b32_e32 v1, s2225; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]226; GFX11-NEXT: s_endpgm227;228; GFX1250-LABEL: s_test_imin_sle_i32:229; GFX1250: ; %bb.0:230; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1231; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0232; GFX1250-NEXT: v_mov_b32_e32 v0, 0233; GFX1250-NEXT: s_wait_kmcnt 0x0234; GFX1250-NEXT: s_min_i32 s2, s2, s3235; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)236; GFX1250-NEXT: v_mov_b32_e32 v1, s2237; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]238; GFX1250-NEXT: s_endpgm239 %cmp = icmp sle i32 %a, %b240 %val = select i1 %cmp, i32 %a, i32 %b241 store i32 %val, ptr addrspace(1) %out, align 4242 ret void243}244 245define amdgpu_kernel void @s_test_imin_sle_v1i32(ptr addrspace(1) %out, <1 x i32> %a, <1 x i32> %b) #0 {246; EG-LABEL: s_test_imin_sle_v1i32:247; EG: ; %bb.0:248; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]249; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1250; EG-NEXT: CF_END251; EG-NEXT: PAD252; EG-NEXT: ALU clause starting at 4:253; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,254; EG-NEXT: MIN_INT * T1.X, KC0[2].Z, KC0[2].W,255; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)256;257; CI-LABEL: s_test_imin_sle_v1i32:258; CI: ; %bb.0:259; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0260; CI-NEXT: s_add_i32 s12, s12, s17261; CI-NEXT: s_mov_b32 flat_scratch_lo, s13262; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8263; CI-NEXT: s_waitcnt lgkmcnt(0)264; CI-NEXT: s_min_i32 s2, s2, s3265; CI-NEXT: v_mov_b32_e32 v0, s0266; CI-NEXT: v_mov_b32_e32 v1, s1267; CI-NEXT: v_mov_b32_e32 v2, s2268; CI-NEXT: flat_store_dword v[0:1], v2269; CI-NEXT: s_endpgm270;271; VI-LABEL: s_test_imin_sle_v1i32:272; VI: ; %bb.0:273; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0274; VI-NEXT: s_add_i32 s12, s12, s17275; VI-NEXT: s_mov_b32 flat_scratch_lo, s13276; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8277; VI-NEXT: s_waitcnt lgkmcnt(0)278; VI-NEXT: s_min_i32 s2, s2, s3279; VI-NEXT: v_mov_b32_e32 v0, s0280; VI-NEXT: v_mov_b32_e32 v1, s1281; VI-NEXT: v_mov_b32_e32 v2, s2282; VI-NEXT: flat_store_dword v[0:1], v2283; VI-NEXT: s_endpgm284;285; GFX9-LABEL: s_test_imin_sle_v1i32:286; GFX9: ; %bb.0:287; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0288; GFX9-NEXT: v_mov_b32_e32 v0, 0289; GFX9-NEXT: s_waitcnt lgkmcnt(0)290; GFX9-NEXT: s_min_i32 s2, s2, s3291; GFX9-NEXT: v_mov_b32_e32 v1, s2292; GFX9-NEXT: global_store_dword v0, v1, s[0:1]293; GFX9-NEXT: s_endpgm294;295; GFX10-LABEL: s_test_imin_sle_v1i32:296; GFX10: ; %bb.0:297; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0298; GFX10-NEXT: v_mov_b32_e32 v0, 0299; GFX10-NEXT: s_waitcnt lgkmcnt(0)300; GFX10-NEXT: s_min_i32 s2, s2, s3301; GFX10-NEXT: v_mov_b32_e32 v1, s2302; GFX10-NEXT: global_store_dword v0, v1, s[0:1]303; GFX10-NEXT: s_endpgm304;305; GFX11-LABEL: s_test_imin_sle_v1i32:306; GFX11: ; %bb.0:307; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0308; GFX11-NEXT: v_mov_b32_e32 v0, 0309; GFX11-NEXT: s_waitcnt lgkmcnt(0)310; GFX11-NEXT: s_min_i32 s2, s2, s3311; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)312; GFX11-NEXT: v_mov_b32_e32 v1, s2313; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]314; GFX11-NEXT: s_endpgm315;316; GFX1250-LABEL: s_test_imin_sle_v1i32:317; GFX1250: ; %bb.0:318; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1319; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0320; GFX1250-NEXT: v_mov_b32_e32 v0, 0321; GFX1250-NEXT: s_wait_kmcnt 0x0322; GFX1250-NEXT: s_min_i32 s2, s2, s3323; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)324; GFX1250-NEXT: v_mov_b32_e32 v1, s2325; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]326; GFX1250-NEXT: s_endpgm327 %cmp = icmp sle <1 x i32> %a, %b328 %val = select <1 x i1> %cmp, <1 x i32> %a, <1 x i32> %b329 store <1 x i32> %val, ptr addrspace(1) %out330 ret void331}332 333define amdgpu_kernel void @s_test_imin_sle_v4i32(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b) #0 {334; EG-LABEL: s_test_imin_sle_v4i32:335; EG: ; %bb.0:336; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]337; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1338; EG-NEXT: CF_END339; EG-NEXT: PAD340; EG-NEXT: ALU clause starting at 4:341; EG-NEXT: MIN_INT * T0.W, KC0[4].X, KC0[5].X,342; EG-NEXT: MIN_INT * T0.Z, KC0[3].W, KC0[4].W,343; EG-NEXT: MIN_INT * T0.Y, KC0[3].Z, KC0[4].Z,344; EG-NEXT: MIN_INT * T0.X, KC0[3].Y, KC0[4].Y,345; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,346; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)347;348; CI-LABEL: s_test_imin_sle_v4i32:349; CI: ; %bb.0:350; CI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x4351; CI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0352; CI-NEXT: s_add_i32 s12, s12, s17353; CI-NEXT: s_mov_b32 flat_scratch_lo, s13354; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8355; CI-NEXT: s_waitcnt lgkmcnt(0)356; CI-NEXT: s_min_i32 s3, s3, s7357; CI-NEXT: s_min_i32 s2, s2, s6358; CI-NEXT: s_min_i32 s1, s1, s5359; CI-NEXT: s_min_i32 s0, s0, s4360; CI-NEXT: v_mov_b32_e32 v4, s8361; CI-NEXT: v_mov_b32_e32 v0, s0362; CI-NEXT: v_mov_b32_e32 v1, s1363; CI-NEXT: v_mov_b32_e32 v2, s2364; CI-NEXT: v_mov_b32_e32 v3, s3365; CI-NEXT: v_mov_b32_e32 v5, s9366; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]367; CI-NEXT: s_endpgm368;369; VI-LABEL: s_test_imin_sle_v4i32:370; VI: ; %bb.0:371; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10372; VI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0373; VI-NEXT: s_add_i32 s12, s12, s17374; VI-NEXT: s_mov_b32 flat_scratch_lo, s13375; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8376; VI-NEXT: s_waitcnt lgkmcnt(0)377; VI-NEXT: s_min_i32 s3, s3, s7378; VI-NEXT: s_min_i32 s2, s2, s6379; VI-NEXT: s_min_i32 s1, s1, s5380; VI-NEXT: s_min_i32 s0, s0, s4381; VI-NEXT: v_mov_b32_e32 v4, s8382; VI-NEXT: v_mov_b32_e32 v0, s0383; VI-NEXT: v_mov_b32_e32 v1, s1384; VI-NEXT: v_mov_b32_e32 v2, s2385; VI-NEXT: v_mov_b32_e32 v3, s3386; VI-NEXT: v_mov_b32_e32 v5, s9387; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]388; VI-NEXT: s_endpgm389;390; GFX9-LABEL: s_test_imin_sle_v4i32:391; GFX9: ; %bb.0:392; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10393; GFX9-NEXT: v_mov_b32_e32 v4, 0394; GFX9-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x0395; GFX9-NEXT: s_waitcnt lgkmcnt(0)396; GFX9-NEXT: s_min_i32 s3, s3, s7397; GFX9-NEXT: s_min_i32 s2, s2, s6398; GFX9-NEXT: s_min_i32 s1, s1, s5399; GFX9-NEXT: s_min_i32 s0, s0, s4400; GFX9-NEXT: v_mov_b32_e32 v0, s0401; GFX9-NEXT: v_mov_b32_e32 v1, s1402; GFX9-NEXT: v_mov_b32_e32 v2, s2403; GFX9-NEXT: v_mov_b32_e32 v3, s3404; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]405; GFX9-NEXT: s_endpgm406;407; GFX10-LABEL: s_test_imin_sle_v4i32:408; GFX10: ; %bb.0:409; GFX10-NEXT: s_clause 0x1410; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x10411; GFX10-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0412; GFX10-NEXT: v_mov_b32_e32 v4, 0413; GFX10-NEXT: s_waitcnt lgkmcnt(0)414; GFX10-NEXT: s_min_i32 s3, s3, s7415; GFX10-NEXT: s_min_i32 s2, s2, s6416; GFX10-NEXT: s_min_i32 s0, s0, s4417; GFX10-NEXT: s_min_i32 s1, s1, s5418; GFX10-NEXT: v_mov_b32_e32 v0, s0419; GFX10-NEXT: v_mov_b32_e32 v1, s1420; GFX10-NEXT: v_mov_b32_e32 v2, s2421; GFX10-NEXT: v_mov_b32_e32 v3, s3422; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11]423; GFX10-NEXT: s_endpgm424;425; GFX11-LABEL: s_test_imin_sle_v4i32:426; GFX11: ; %bb.0:427; GFX11-NEXT: s_clause 0x1428; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x10429; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0430; GFX11-NEXT: v_mov_b32_e32 v4, 0431; GFX11-NEXT: s_waitcnt lgkmcnt(0)432; GFX11-NEXT: s_min_i32 s2, s11, s15433; GFX11-NEXT: s_min_i32 s3, s10, s14434; GFX11-NEXT: s_min_i32 s4, s8, s12435; GFX11-NEXT: s_min_i32 s5, s9, s13436; GFX11-NEXT: v_mov_b32_e32 v0, s4437; GFX11-NEXT: v_mov_b32_e32 v1, s5438; GFX11-NEXT: v_mov_b32_e32 v2, s3439; GFX11-NEXT: v_mov_b32_e32 v3, s2440; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]441; GFX11-NEXT: s_endpgm442;443; GFX1250-LABEL: s_test_imin_sle_v4i32:444; GFX1250: ; %bb.0:445; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1446; GFX1250-NEXT: s_clause 0x1447; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x10448; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0449; GFX1250-NEXT: v_mov_b32_e32 v4, 0450; GFX1250-NEXT: s_wait_kmcnt 0x0451; GFX1250-NEXT: s_min_i32 s2, s11, s15452; GFX1250-NEXT: s_min_i32 s3, s10, s14453; GFX1250-NEXT: s_min_i32 s4, s8, s12454; GFX1250-NEXT: s_min_i32 s5, s9, s13455; GFX1250-NEXT: v_mov_b32_e32 v0, s4456; GFX1250-NEXT: v_mov_b32_e32 v1, s5457; GFX1250-NEXT: v_mov_b32_e32 v2, s3458; GFX1250-NEXT: v_mov_b32_e32 v3, s2459; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[0:1]460; GFX1250-NEXT: s_endpgm461 %cmp = icmp sle <4 x i32> %a, %b462 %val = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b463 store <4 x i32> %val, ptr addrspace(1) %out464 ret void465}466 467define amdgpu_kernel void @s_test_imin_sle_i8(ptr addrspace(1) %out, [8 x i32], i8 %a, [8 x i32], i8 %b) #0 {468; EG-LABEL: s_test_imin_sle_i8:469; EG: ; %bb.0:470; EG-NEXT: ALU 0, @10, KC0[], KC1[]471; EG-NEXT: TEX 1 @6472; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]473; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X474; EG-NEXT: CF_END475; EG-NEXT: PAD476; EG-NEXT: Fetch clause starting at 6:477; EG-NEXT: VTX_READ_8 T1.X, T0.X, 72, #3478; EG-NEXT: VTX_READ_8 T0.X, T0.X, 108, #3479; EG-NEXT: ALU clause starting at 10:480; EG-NEXT: MOV * T0.X, 0.0,481; EG-NEXT: ALU clause starting at 11:482; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,483; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_212484; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,485; EG-NEXT: 8(1.121039e-44), 3(4.203895e-45)486; EG-NEXT: MIN_INT * T0.W, PV.Z, PV.W,487; EG-NEXT: AND_INT T0.W, PV.W, literal.x,488; EG-NEXT: LSHL * T1.W, T1.W, literal.y,489; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)490; EG-NEXT: LSHL T0.X, PV.W, PS,491; EG-NEXT: LSHL * T0.W, literal.x, PS,492; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)493; EG-NEXT: MOV T0.Y, 0.0,494; EG-NEXT: MOV * T0.Z, 0.0,495; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,496; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)497;498; CI-LABEL: s_test_imin_sle_i8:499; CI: ; %bb.0:500; CI-NEXT: s_load_dword s2, s[8:9], 0xa501; CI-NEXT: s_load_dword s3, s[8:9], 0x13502; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0503; CI-NEXT: s_add_i32 s12, s12, s17504; CI-NEXT: s_mov_b32 flat_scratch_lo, s13505; CI-NEXT: s_waitcnt lgkmcnt(0)506; CI-NEXT: s_sext_i32_i8 s2, s2507; CI-NEXT: s_sext_i32_i8 s3, s3508; CI-NEXT: s_min_i32 s2, s2, s3509; CI-NEXT: v_mov_b32_e32 v0, s0510; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8511; CI-NEXT: v_mov_b32_e32 v1, s1512; CI-NEXT: v_mov_b32_e32 v2, s2513; CI-NEXT: flat_store_byte v[0:1], v2514; CI-NEXT: s_endpgm515;516; VI-LABEL: s_test_imin_sle_i8:517; VI: ; %bb.0:518; VI-NEXT: s_load_dword s2, s[8:9], 0x4c519; VI-NEXT: s_load_dword s3, s[8:9], 0x28520; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0521; VI-NEXT: s_add_i32 s12, s12, s17522; VI-NEXT: s_mov_b32 flat_scratch_lo, s13523; VI-NEXT: s_waitcnt lgkmcnt(0)524; VI-NEXT: s_sext_i32_i8 s2, s2525; VI-NEXT: s_sext_i32_i8 s3, s3526; VI-NEXT: s_min_i32 s2, s3, s2527; VI-NEXT: v_mov_b32_e32 v0, s0528; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8529; VI-NEXT: v_mov_b32_e32 v1, s1530; VI-NEXT: v_mov_b32_e32 v2, s2531; VI-NEXT: flat_store_byte v[0:1], v2532; VI-NEXT: s_endpgm533;534; GFX9-LABEL: s_test_imin_sle_i8:535; GFX9: ; %bb.0:536; GFX9-NEXT: s_load_dword s2, s[8:9], 0x4c537; GFX9-NEXT: s_load_dword s3, s[8:9], 0x28538; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0539; GFX9-NEXT: v_mov_b32_e32 v0, 0540; GFX9-NEXT: s_waitcnt lgkmcnt(0)541; GFX9-NEXT: s_sext_i32_i8 s2, s2542; GFX9-NEXT: s_sext_i32_i8 s3, s3543; GFX9-NEXT: s_min_i32 s2, s3, s2544; GFX9-NEXT: v_mov_b32_e32 v1, s2545; GFX9-NEXT: global_store_byte v0, v1, s[0:1]546; GFX9-NEXT: s_endpgm547;548; GFX10-LABEL: s_test_imin_sle_i8:549; GFX10: ; %bb.0:550; GFX10-NEXT: s_clause 0x2551; GFX10-NEXT: s_load_dword s2, s[8:9], 0x4c552; GFX10-NEXT: s_load_dword s3, s[8:9], 0x28553; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0554; GFX10-NEXT: v_mov_b32_e32 v0, 0555; GFX10-NEXT: s_waitcnt lgkmcnt(0)556; GFX10-NEXT: s_sext_i32_i8 s2, s2557; GFX10-NEXT: s_sext_i32_i8 s3, s3558; GFX10-NEXT: s_min_i32 s2, s3, s2559; GFX10-NEXT: v_mov_b32_e32 v1, s2560; GFX10-NEXT: global_store_byte v0, v1, s[0:1]561; GFX10-NEXT: s_endpgm562;563; GFX11-LABEL: s_test_imin_sle_i8:564; GFX11: ; %bb.0:565; GFX11-NEXT: s_clause 0x2566; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x4c567; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x28568; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0569; GFX11-NEXT: v_mov_b32_e32 v0, 0570; GFX11-NEXT: s_waitcnt lgkmcnt(0)571; GFX11-NEXT: s_sext_i32_i8 s2, s2572; GFX11-NEXT: s_sext_i32_i8 s3, s3573; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)574; GFX11-NEXT: s_min_i32 s2, s3, s2575; GFX11-NEXT: v_mov_b32_e32 v1, s2576; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]577; GFX11-NEXT: s_endpgm578;579; GFX1250-LABEL: s_test_imin_sle_i8:580; GFX1250: ; %bb.0:581; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1582; GFX1250-NEXT: s_clause 0x2583; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x4c584; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x28585; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0586; GFX1250-NEXT: v_mov_b32_e32 v0, 0587; GFX1250-NEXT: s_wait_kmcnt 0x0588; GFX1250-NEXT: s_sext_i32_i8 s2, s2589; GFX1250-NEXT: s_sext_i32_i8 s3, s3590; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)591; GFX1250-NEXT: s_min_i32 s2, s3, s2592; GFX1250-NEXT: v_mov_b32_e32 v1, s2593; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1]594; GFX1250-NEXT: s_endpgm595 %cmp = icmp sle i8 %a, %b596 %val = select i1 %cmp, i8 %a, i8 %b597 store i8 %val, ptr addrspace(1) %out598 ret void599}600 601; FIXME: Why vector and sdwa for last element?602 603define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32], <4 x i8> %a, [8 x i32], <4 x i8> %b) #0 {604; EG-LABEL: s_test_imin_sle_v4i8:605; EG: ; %bb.0:606; EG-NEXT: ALU 0, @22, KC0[], KC1[]607; EG-NEXT: TEX 7 @6608; EG-NEXT: ALU 30, @23, KC0[CB0:0-32], KC1[]609; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1610; EG-NEXT: CF_END611; EG-NEXT: PAD612; EG-NEXT: Fetch clause starting at 6:613; EG-NEXT: VTX_READ_8 T5.X, T4.X, 74, #3614; EG-NEXT: VTX_READ_8 T6.X, T4.X, 108, #3615; EG-NEXT: VTX_READ_8 T7.X, T4.X, 72, #3616; EG-NEXT: VTX_READ_8 T8.X, T4.X, 111, #3617; EG-NEXT: VTX_READ_8 T9.X, T4.X, 75, #3618; EG-NEXT: VTX_READ_8 T10.X, T4.X, 109, #3619; EG-NEXT: VTX_READ_8 T11.X, T4.X, 73, #3620; EG-NEXT: VTX_READ_8 T4.X, T4.X, 110, #3621; EG-NEXT: ALU clause starting at 22:622; EG-NEXT: MOV * T4.X, 0.0,623; EG-NEXT: ALU clause starting at 23:624; EG-NEXT: BFE_INT T0.Z, T5.X, 0.0, literal.x,625; EG-NEXT: BFE_INT * T0.W, T4.X, 0.0, literal.x, BS:VEC_120/SCL_212626; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)627; EG-NEXT: BFE_INT T4.X, T11.X, 0.0, literal.x,628; EG-NEXT: BFE_INT T0.Y, T10.X, 0.0, literal.x, BS:VEC_120/SCL_212629; EG-NEXT: BFE_INT * T1.Z, T9.X, 0.0, literal.x, BS:VEC_201630; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)631; EG-NEXT: BFE_INT T1.W, T8.X, 0.0, literal.x,632; EG-NEXT: MIN_INT * T0.W, T0.Z, T0.W,633; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)634; EG-NEXT: MIN_INT T0.Z, T1.Z, PV.W,635; EG-NEXT: AND_INT T0.W, PS, literal.x,636; EG-NEXT: MIN_INT * T1.W, T4.X, T0.Y,637; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)638; EG-NEXT: AND_INT T4.X, PS, literal.x,639; EG-NEXT: LSHL T0.Y, PV.W, literal.y,640; EG-NEXT: BFE_INT T1.Z, T7.X, 0.0, literal.z,641; EG-NEXT: BFE_INT T0.W, T6.X, 0.0, literal.z, BS:VEC_120/SCL_212642; EG-NEXT: LSHL * T1.W, PV.Z, literal.w,643; EG-NEXT: 255(3.573311e-43), 16(2.242078e-44)644; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)645; EG-NEXT: MIN_INT T0.Z, PV.Z, PV.W,646; EG-NEXT: OR_INT T0.W, PS, PV.Y,647; EG-NEXT: LSHL * T1.W, PV.X, literal.x,648; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)649; EG-NEXT: OR_INT T0.W, PV.W, PS,650; EG-NEXT: AND_INT * T1.W, PV.Z, literal.x,651; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)652; EG-NEXT: OR_INT T4.X, PV.W, PS,653; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,654; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)655;656; CI-LABEL: s_test_imin_sle_v4i8:657; CI: ; %bb.0:658; CI-NEXT: s_load_dword s2, s[8:9], 0xa659; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0660; CI-NEXT: s_load_dword s3, s[8:9], 0x13661; CI-NEXT: s_add_i32 s12, s12, s17662; CI-NEXT: s_mov_b32 flat_scratch_lo, s13663; CI-NEXT: s_waitcnt lgkmcnt(0)664; CI-NEXT: s_ashr_i32 s4, s2, 24665; CI-NEXT: s_sext_i32_i8 s5, s2666; CI-NEXT: s_bfe_i32 s6, s2, 0x80008667; CI-NEXT: s_bfe_i32 s2, s2, 0x80010668; CI-NEXT: s_ashr_i32 s7, s3, 24669; CI-NEXT: s_sext_i32_i8 s8, s3670; CI-NEXT: s_bfe_i32 s9, s3, 0x80008671; CI-NEXT: s_bfe_i32 s3, s3, 0x80010672; CI-NEXT: s_min_i32 s2, s2, s3673; CI-NEXT: s_min_i32 s4, s4, s7674; CI-NEXT: s_and_b32 s2, s2, 0xff675; CI-NEXT: s_lshl_b32 s4, s4, 24676; CI-NEXT: s_lshl_b32 s2, s2, 16677; CI-NEXT: s_or_b32 s2, s4, s2678; CI-NEXT: s_min_i32 s3, s6, s9679; CI-NEXT: s_min_i32 s4, s5, s8680; CI-NEXT: s_lshl_b32 s3, s3, 8681; CI-NEXT: s_and_b32 s4, s4, 0xff682; CI-NEXT: s_or_b32 s3, s4, s3683; CI-NEXT: s_and_b32 s3, s3, 0xffff684; CI-NEXT: s_or_b32 s2, s3, s2685; CI-NEXT: v_mov_b32_e32 v0, s0686; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8687; CI-NEXT: v_mov_b32_e32 v1, s1688; CI-NEXT: v_mov_b32_e32 v2, s2689; CI-NEXT: flat_store_dword v[0:1], v2690; CI-NEXT: s_endpgm691;692; VI-LABEL: s_test_imin_sle_v4i8:693; VI: ; %bb.0:694; VI-NEXT: s_load_dword s2, s[8:9], 0x28695; VI-NEXT: s_load_dword s3, s[8:9], 0x4c696; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0697; VI-NEXT: s_add_i32 s12, s12, s17698; VI-NEXT: s_mov_b32 flat_scratch_lo, s13699; VI-NEXT: s_waitcnt lgkmcnt(0)700; VI-NEXT: s_ashr_i32 s4, s2, 24701; VI-NEXT: s_ashr_i32 s6, s3, 24702; VI-NEXT: s_min_i32 s4, s4, s6703; VI-NEXT: s_bfe_i32 s6, s3, 0x80010704; VI-NEXT: s_bfe_i32 s8, s2, 0x80010705; VI-NEXT: s_min_i32 s6, s8, s6706; VI-NEXT: s_sext_i32_i16 s5, s2707; VI-NEXT: s_sext_i32_i16 s7, s3708; VI-NEXT: s_lshl_b32 s4, s4, 8709; VI-NEXT: s_and_b32 s6, s6, 0xff710; VI-NEXT: s_or_b32 s4, s6, s4711; VI-NEXT: s_ashr_i32 s6, s7, 8712; VI-NEXT: s_ashr_i32 s5, s5, 8713; VI-NEXT: s_sext_i32_i8 s3, s3714; VI-NEXT: s_sext_i32_i8 s2, s2715; VI-NEXT: s_min_i32 s5, s5, s6716; VI-NEXT: s_min_i32 s2, s2, s3717; VI-NEXT: s_lshl_b32 s5, s5, 8718; VI-NEXT: s_and_b32 s2, s2, 0xff719; VI-NEXT: s_or_b32 s2, s2, s5720; VI-NEXT: s_lshl_b32 s4, s4, 16721; VI-NEXT: s_and_b32 s2, s2, 0xffff722; VI-NEXT: s_or_b32 s2, s2, s4723; VI-NEXT: v_mov_b32_e32 v0, s0724; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8725; VI-NEXT: v_mov_b32_e32 v1, s1726; VI-NEXT: v_mov_b32_e32 v2, s2727; VI-NEXT: flat_store_dword v[0:1], v2728; VI-NEXT: s_endpgm729;730; GFX9-LABEL: s_test_imin_sle_v4i8:731; GFX9: ; %bb.0:732; GFX9-NEXT: s_load_dword s2, s[8:9], 0x28733; GFX9-NEXT: s_load_dword s3, s[8:9], 0x4c734; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0735; GFX9-NEXT: v_mov_b32_e32 v0, 0736; GFX9-NEXT: s_waitcnt lgkmcnt(0)737; GFX9-NEXT: s_sext_i32_i16 s5, s2738; GFX9-NEXT: s_sext_i32_i16 s7, s3739; GFX9-NEXT: s_ashr_i32 s7, s7, 8740; GFX9-NEXT: s_ashr_i32 s5, s5, 8741; GFX9-NEXT: s_ashr_i32 s4, s2, 24742; GFX9-NEXT: s_ashr_i32 s6, s3, 24743; GFX9-NEXT: s_min_i32 s5, s5, s7744; GFX9-NEXT: s_sext_i32_i8 s7, s3745; GFX9-NEXT: s_sext_i32_i8 s8, s2746; GFX9-NEXT: s_bfe_i32 s3, s3, 0x80010747; GFX9-NEXT: s_bfe_i32 s2, s2, 0x80010748; GFX9-NEXT: s_min_i32 s7, s8, s7749; GFX9-NEXT: s_min_i32 s4, s4, s6750; GFX9-NEXT: s_min_i32 s2, s2, s3751; GFX9-NEXT: s_lshl_b32 s5, s5, 8752; GFX9-NEXT: s_and_b32 s7, s7, 0xff753; GFX9-NEXT: s_lshl_b32 s4, s4, 8754; GFX9-NEXT: s_and_b32 s2, s2, 0xff755; GFX9-NEXT: s_or_b32 s5, s7, s5756; GFX9-NEXT: s_or_b32 s2, s2, s4757; GFX9-NEXT: s_and_b32 s5, s5, 0xffff758; GFX9-NEXT: s_lshl_b32 s2, s2, 16759; GFX9-NEXT: s_or_b32 s2, s5, s2760; GFX9-NEXT: v_mov_b32_e32 v1, s2761; GFX9-NEXT: global_store_dword v0, v1, s[0:1]762; GFX9-NEXT: s_endpgm763;764; GFX10-LABEL: s_test_imin_sle_v4i8:765; GFX10: ; %bb.0:766; GFX10-NEXT: s_clause 0x2767; GFX10-NEXT: s_load_dword s2, s[8:9], 0x28768; GFX10-NEXT: s_load_dword s3, s[8:9], 0x4c769; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0770; GFX10-NEXT: v_mov_b32_e32 v0, 0771; GFX10-NEXT: s_waitcnt lgkmcnt(0)772; GFX10-NEXT: s_sext_i32_i16 s5, s2773; GFX10-NEXT: s_sext_i32_i16 s7, s3774; GFX10-NEXT: s_ashr_i32 s4, s2, 24775; GFX10-NEXT: s_ashr_i32 s6, s3, 24776; GFX10-NEXT: s_sext_i32_i8 s8, s3777; GFX10-NEXT: s_sext_i32_i8 s9, s2778; GFX10-NEXT: s_bfe_i32 s3, s3, 0x80010779; GFX10-NEXT: s_bfe_i32 s2, s2, 0x80010780; GFX10-NEXT: s_ashr_i32 s7, s7, 8781; GFX10-NEXT: s_ashr_i32 s5, s5, 8782; GFX10-NEXT: s_min_i32 s8, s9, s8783; GFX10-NEXT: s_min_i32 s4, s4, s6784; GFX10-NEXT: s_min_i32 s2, s2, s3785; GFX10-NEXT: s_min_i32 s3, s5, s7786; GFX10-NEXT: s_and_b32 s5, s8, 0xff787; GFX10-NEXT: s_lshl_b32 s4, s4, 8788; GFX10-NEXT: s_lshl_b32 s3, s3, 8789; GFX10-NEXT: s_and_b32 s2, s2, 0xff790; GFX10-NEXT: s_or_b32 s3, s5, s3791; GFX10-NEXT: s_or_b32 s2, s2, s4792; GFX10-NEXT: s_and_b32 s3, s3, 0xffff793; GFX10-NEXT: s_lshl_b32 s2, s2, 16794; GFX10-NEXT: s_or_b32 s2, s3, s2795; GFX10-NEXT: v_mov_b32_e32 v1, s2796; GFX10-NEXT: global_store_dword v0, v1, s[0:1]797; GFX10-NEXT: s_endpgm798;799; GFX11-LABEL: s_test_imin_sle_v4i8:800; GFX11: ; %bb.0:801; GFX11-NEXT: s_clause 0x2802; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x28803; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x4c804; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0805; GFX11-NEXT: v_mov_b32_e32 v0, 0806; GFX11-NEXT: s_waitcnt lgkmcnt(0)807; GFX11-NEXT: s_sext_i32_i16 s5, s2808; GFX11-NEXT: s_sext_i32_i16 s7, s3809; GFX11-NEXT: s_ashr_i32 s4, s2, 24810; GFX11-NEXT: s_ashr_i32 s6, s3, 24811; GFX11-NEXT: s_sext_i32_i8 s8, s3812; GFX11-NEXT: s_sext_i32_i8 s9, s2813; GFX11-NEXT: s_bfe_i32 s3, s3, 0x80010814; GFX11-NEXT: s_bfe_i32 s2, s2, 0x80010815; GFX11-NEXT: s_ashr_i32 s7, s7, 8816; GFX11-NEXT: s_ashr_i32 s5, s5, 8817; GFX11-NEXT: s_min_i32 s8, s9, s8818; GFX11-NEXT: s_min_i32 s4, s4, s6819; GFX11-NEXT: s_min_i32 s2, s2, s3820; GFX11-NEXT: s_min_i32 s3, s5, s7821; GFX11-NEXT: s_and_b32 s5, s8, 0xff822; GFX11-NEXT: s_lshl_b32 s4, s4, 8823; GFX11-NEXT: s_lshl_b32 s3, s3, 8824; GFX11-NEXT: s_and_b32 s2, s2, 0xff825; GFX11-NEXT: s_or_b32 s3, s5, s3826; GFX11-NEXT: s_or_b32 s2, s2, s4827; GFX11-NEXT: s_and_b32 s3, s3, 0xffff828; GFX11-NEXT: s_lshl_b32 s2, s2, 16829; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)830; GFX11-NEXT: s_or_b32 s2, s3, s2831; GFX11-NEXT: v_mov_b32_e32 v1, s2832; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]833; GFX11-NEXT: s_endpgm834;835; GFX1250-LABEL: s_test_imin_sle_v4i8:836; GFX1250: ; %bb.0:837; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1838; GFX1250-NEXT: s_clause 0x2839; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x28840; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x4c841; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x0842; GFX1250-NEXT: v_mov_b32_e32 v0, 0843; GFX1250-NEXT: s_wait_kmcnt 0x0844; GFX1250-NEXT: s_sext_i32_i16 s5, s2845; GFX1250-NEXT: s_sext_i32_i16 s7, s3846; GFX1250-NEXT: s_ashr_i32 s4, s2, 24847; GFX1250-NEXT: s_ashr_i32 s6, s3, 24848; GFX1250-NEXT: s_sext_i32_i8 s8, s3849; GFX1250-NEXT: s_sext_i32_i8 s9, s2850; GFX1250-NEXT: s_bfe_i32 s3, s3, 0x80010851; GFX1250-NEXT: s_bfe_i32 s2, s2, 0x80010852; GFX1250-NEXT: s_ashr_i32 s7, s7, 8853; GFX1250-NEXT: s_ashr_i32 s5, s5, 8854; GFX1250-NEXT: s_min_i32 s8, s9, s8855; GFX1250-NEXT: s_min_i32 s4, s4, s6856; GFX1250-NEXT: s_min_i32 s2, s2, s3857; GFX1250-NEXT: s_min_i32 s3, s5, s7858; GFX1250-NEXT: s_and_b32 s5, s8, 0xff859; GFX1250-NEXT: s_lshl_b32 s4, s4, 8860; GFX1250-NEXT: s_lshl_b32 s3, s3, 8861; GFX1250-NEXT: s_and_b32 s2, s2, 0xff862; GFX1250-NEXT: s_or_b32 s3, s5, s3863; GFX1250-NEXT: s_or_b32 s2, s2, s4864; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff865; GFX1250-NEXT: s_lshl_b32 s2, s2, 16866; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)867; GFX1250-NEXT: s_or_b32 s2, s3, s2868; GFX1250-NEXT: v_mov_b32_e32 v1, s2869; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]870; GFX1250-NEXT: s_endpgm871 %cmp = icmp sle <4 x i8> %a, %b872 %val = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b873 store <4 x i8> %val, ptr addrspace(1) %out874 ret void875}876 877define amdgpu_kernel void @s_test_imin_sle_v2i16(ptr addrspace(1) %out, <2 x i16> %a, <2 x i16> %b) #0 {878; EG-LABEL: s_test_imin_sle_v2i16:879; EG: ; %bb.0:880; EG-NEXT: ALU 0, @14, KC0[], KC1[]881; EG-NEXT: TEX 3 @6882; EG-NEXT: ALU 13, @15, KC0[CB0:0-32], KC1[]883; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 1884; EG-NEXT: CF_END885; EG-NEXT: PAD886; EG-NEXT: Fetch clause starting at 6:887; EG-NEXT: VTX_READ_16 T5.X, T4.X, 42, #3888; EG-NEXT: VTX_READ_16 T6.X, T4.X, 44, #3889; EG-NEXT: VTX_READ_16 T7.X, T4.X, 40, #3890; EG-NEXT: VTX_READ_16 T4.X, T4.X, 46, #3891; EG-NEXT: ALU clause starting at 14:892; EG-NEXT: MOV * T4.X, 0.0,893; EG-NEXT: ALU clause starting at 15:894; EG-NEXT: BFE_INT T5.X, T5.X, 0.0, literal.x,895; EG-NEXT: BFE_INT T0.Y, T4.X, 0.0, literal.x, BS:VEC_120/SCL_212896; EG-NEXT: BFE_INT * T0.Z, T7.X, 0.0, literal.x, BS:VEC_201897; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)898; EG-NEXT: BFE_INT * T0.W, T6.X, 0.0, literal.x,899; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)900; EG-NEXT: MIN_INT T0.W, T0.Z, PV.W,901; EG-NEXT: MIN_INT * T1.W, T5.X, T0.Y,902; EG-NEXT: LSHL T1.W, PS, literal.x,903; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,904; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)905; EG-NEXT: OR_INT T4.X, PV.W, PS,906; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,907; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)908;909; CI-LABEL: s_test_imin_sle_v2i16:910; CI: ; %bb.0:911; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0912; CI-NEXT: s_add_i32 s12, s12, s17913; CI-NEXT: s_mov_b32 flat_scratch_lo, s13914; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8915; CI-NEXT: s_waitcnt lgkmcnt(0)916; CI-NEXT: s_ashr_i32 s4, s2, 16917; CI-NEXT: s_sext_i32_i16 s2, s2918; CI-NEXT: s_ashr_i32 s5, s3, 16919; CI-NEXT: s_sext_i32_i16 s3, s3920; CI-NEXT: s_min_i32 s4, s4, s5921; CI-NEXT: s_min_i32 s2, s2, s3922; CI-NEXT: s_lshl_b32 s3, s4, 16923; CI-NEXT: s_and_b32 s2, s2, 0xffff924; CI-NEXT: s_or_b32 s2, s2, s3925; CI-NEXT: v_mov_b32_e32 v0, s0926; CI-NEXT: v_mov_b32_e32 v1, s1927; CI-NEXT: v_mov_b32_e32 v2, s2928; CI-NEXT: flat_store_dword v[0:1], v2929; CI-NEXT: s_endpgm930;931; VI-LABEL: s_test_imin_sle_v2i16:932; VI: ; %bb.0:933; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0934; VI-NEXT: s_add_i32 s12, s12, s17935; VI-NEXT: s_mov_b32 flat_scratch_lo, s13936; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8937; VI-NEXT: s_waitcnt lgkmcnt(0)938; VI-NEXT: s_ashr_i32 s4, s3, 16939; VI-NEXT: s_ashr_i32 s5, s2, 16940; VI-NEXT: s_sext_i32_i16 s3, s3941; VI-NEXT: s_sext_i32_i16 s2, s2942; VI-NEXT: s_min_i32 s4, s5, s4943; VI-NEXT: s_min_i32 s2, s2, s3944; VI-NEXT: s_lshl_b32 s3, s4, 16945; VI-NEXT: s_and_b32 s2, s2, 0xffff946; VI-NEXT: s_or_b32 s2, s2, s3947; VI-NEXT: v_mov_b32_e32 v0, s0948; VI-NEXT: v_mov_b32_e32 v1, s1949; VI-NEXT: v_mov_b32_e32 v2, s2950; VI-NEXT: flat_store_dword v[0:1], v2951; VI-NEXT: s_endpgm952;953; GFX9-LABEL: s_test_imin_sle_v2i16:954; GFX9: ; %bb.0:955; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0956; GFX9-NEXT: v_mov_b32_e32 v0, 0957; GFX9-NEXT: s_waitcnt lgkmcnt(0)958; GFX9-NEXT: v_mov_b32_e32 v1, s3959; GFX9-NEXT: v_pk_min_i16 v1, s2, v1960; GFX9-NEXT: global_store_dword v0, v1, s[0:1]961; GFX9-NEXT: s_endpgm962;963; GFX10-LABEL: s_test_imin_sle_v2i16:964; GFX10: ; %bb.0:965; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0966; GFX10-NEXT: v_mov_b32_e32 v0, 0967; GFX10-NEXT: s_waitcnt lgkmcnt(0)968; GFX10-NEXT: v_pk_min_i16 v1, s2, s3969; GFX10-NEXT: global_store_dword v0, v1, s[0:1]970; GFX10-NEXT: s_endpgm971;972; GFX11-LABEL: s_test_imin_sle_v2i16:973; GFX11: ; %bb.0:974; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0975; GFX11-NEXT: v_mov_b32_e32 v0, 0976; GFX11-NEXT: s_waitcnt lgkmcnt(0)977; GFX11-NEXT: v_pk_min_i16 v1, s2, s3978; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]979; GFX11-NEXT: s_endpgm980;981; GFX1250-LABEL: s_test_imin_sle_v2i16:982; GFX1250: ; %bb.0:983; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1984; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0985; GFX1250-NEXT: v_mov_b32_e32 v0, 0986; GFX1250-NEXT: s_wait_kmcnt 0x0987; GFX1250-NEXT: v_pk_min_i16 v1, s2, s3988; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]989; GFX1250-NEXT: s_endpgm990 %cmp = icmp sle <2 x i16> %a, %b991 %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b992 store <2 x i16> %val, ptr addrspace(1) %out993 ret void994}995 996define amdgpu_kernel void @s_test_imin_sle_v4i16(ptr addrspace(1) %out, <4 x i16> %a, <4 x i16> %b) #0 {997; EG-LABEL: s_test_imin_sle_v4i16:998; EG: ; %bb.0:999; EG-NEXT: ALU 1, @28, KC0[], KC1[]1000; EG-NEXT: TEX 1 @121001; EG-NEXT: ALU 9, @30, KC0[], KC1[]1002; EG-NEXT: TEX 1 @161003; EG-NEXT: ALU 10, @40, KC0[], KC1[]1004; EG-NEXT: TEX 1 @201005; EG-NEXT: ALU 10, @51, KC0[], KC1[]1006; EG-NEXT: TEX 1 @241007; EG-NEXT: ALU 11, @62, KC0[CB0:0-32], KC1[]1008; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XY, T5.X, 11009; EG-NEXT: CF_END1010; EG-NEXT: PAD1011; EG-NEXT: Fetch clause starting at 12:1012; EG-NEXT: VTX_READ_16 T6.X, T5.X, 50, #31013; EG-NEXT: VTX_READ_16 T7.X, T5.X, 58, #31014; EG-NEXT: Fetch clause starting at 16:1015; EG-NEXT: VTX_READ_16 T6.X, T5.X, 48, #31016; EG-NEXT: VTX_READ_16 T7.X, T5.X, 56, #31017; EG-NEXT: Fetch clause starting at 20:1018; EG-NEXT: VTX_READ_16 T6.X, T5.X, 46, #31019; EG-NEXT: VTX_READ_16 T7.X, T5.X, 54, #31020; EG-NEXT: Fetch clause starting at 24:1021; EG-NEXT: VTX_READ_16 T6.X, T5.X, 44, #31022; EG-NEXT: VTX_READ_16 T5.X, T5.X, 52, #31023; EG-NEXT: ALU clause starting at 28:1024; EG-NEXT: MOV * T0.Y, T3.X,1025; EG-NEXT: MOV * T5.X, 0.0,1026; EG-NEXT: ALU clause starting at 30:1027; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x,1028; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_2121029; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1030; EG-NEXT: MIN_INT * T0.W, PV.Z, PV.W,1031; EG-NEXT: LSHL T0.W, PV.W, literal.x,1032; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,1033; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)1034; EG-NEXT: OR_INT * T0.W, PS, PV.W,1035; EG-NEXT: MOV * T3.X, PV.W,1036; EG-NEXT: MOV * T0.Y, PV.X,1037; EG-NEXT: ALU clause starting at 40:1038; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x,1039; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_2121040; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1041; EG-NEXT: MIN_INT T0.W, PV.Z, PV.W,1042; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,1043; EG-NEXT: -65536(nan), 0(0.000000e+00)1044; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,1045; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1046; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,1047; EG-NEXT: MOV T3.X, PV.W,1048; EG-NEXT: MOV * T0.Y, T2.X,1049; EG-NEXT: ALU clause starting at 51:1050; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x,1051; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x, BS:VEC_120/SCL_2121052; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1053; EG-NEXT: MIN_INT T0.W, PV.Z, PV.W,1054; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,1055; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1056; EG-NEXT: LSHL * T0.W, PV.W, literal.x,1057; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1058; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,1059; EG-NEXT: MOV * T2.X, PV.W,1060; EG-NEXT: MOV * T0.Y, PV.X,1061; EG-NEXT: ALU clause starting at 62:1062; EG-NEXT: BFE_INT T0.Z, T6.X, 0.0, literal.x,1063; EG-NEXT: BFE_INT * T0.W, T5.X, 0.0, literal.x, BS:VEC_120/SCL_2121064; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1065; EG-NEXT: MIN_INT * T0.W, PV.Z, PV.W,1066; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x,1067; EG-NEXT: AND_INT T1.W, T0.Y, literal.y,1068; EG-NEXT: AND_INT * T0.W, PV.W, literal.z,1069; EG-NEXT: 2(2.802597e-45), -65536(nan)1070; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1071; EG-NEXT: OR_INT * T6.X, PV.W, PS,1072; EG-NEXT: MOV T2.X, PV.X,1073; EG-NEXT: MOV * T6.Y, T3.X,1074;1075; CI-LABEL: s_test_imin_sle_v4i16:1076; CI: ; %bb.0:1077; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x21078; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01079; CI-NEXT: s_add_i32 s12, s12, s171080; CI-NEXT: s_mov_b32 flat_scratch_lo, s131081; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81082; CI-NEXT: s_waitcnt lgkmcnt(0)1083; CI-NEXT: s_ashr_i32 s6, s0, 161084; CI-NEXT: s_ashr_i32 s7, s1, 161085; CI-NEXT: s_sext_i32_i16 s0, s01086; CI-NEXT: s_sext_i32_i16 s1, s11087; CI-NEXT: s_ashr_i32 s8, s2, 161088; CI-NEXT: s_ashr_i32 s9, s3, 161089; CI-NEXT: s_sext_i32_i16 s2, s21090; CI-NEXT: s_sext_i32_i16 s3, s31091; CI-NEXT: s_min_i32 s7, s7, s91092; CI-NEXT: s_min_i32 s1, s1, s31093; CI-NEXT: s_min_i32 s3, s6, s81094; CI-NEXT: s_min_i32 s0, s0, s21095; CI-NEXT: s_lshl_b32 s7, s7, 161096; CI-NEXT: s_and_b32 s1, s1, 0xffff1097; CI-NEXT: s_lshl_b32 s3, s3, 161098; CI-NEXT: s_and_b32 s0, s0, 0xffff1099; CI-NEXT: s_or_b32 s1, s1, s71100; CI-NEXT: s_or_b32 s0, s0, s31101; CI-NEXT: v_mov_b32_e32 v2, s41102; CI-NEXT: v_mov_b32_e32 v0, s01103; CI-NEXT: v_mov_b32_e32 v1, s11104; CI-NEXT: v_mov_b32_e32 v3, s51105; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1106; CI-NEXT: s_endpgm1107;1108; VI-LABEL: s_test_imin_sle_v4i16:1109; VI: ; %bb.0:1110; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81111; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01112; VI-NEXT: s_add_i32 s12, s12, s171113; VI-NEXT: s_mov_b32 flat_scratch_lo, s131114; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81115; VI-NEXT: s_waitcnt lgkmcnt(0)1116; VI-NEXT: s_ashr_i32 s6, s3, 161117; VI-NEXT: s_ashr_i32 s7, s1, 161118; VI-NEXT: s_sext_i32_i16 s3, s31119; VI-NEXT: s_sext_i32_i16 s1, s11120; VI-NEXT: s_min_i32 s6, s7, s61121; VI-NEXT: s_min_i32 s1, s1, s31122; VI-NEXT: s_lshl_b32 s6, s6, 161123; VI-NEXT: s_and_b32 s1, s1, 0xffff1124; VI-NEXT: s_or_b32 s1, s1, s61125; VI-NEXT: s_ashr_i32 s3, s2, 161126; VI-NEXT: s_ashr_i32 s6, s0, 161127; VI-NEXT: s_sext_i32_i16 s2, s21128; VI-NEXT: s_sext_i32_i16 s0, s01129; VI-NEXT: s_min_i32 s3, s6, s31130; VI-NEXT: s_min_i32 s0, s0, s21131; VI-NEXT: s_lshl_b32 s3, s3, 161132; VI-NEXT: s_and_b32 s0, s0, 0xffff1133; VI-NEXT: s_or_b32 s0, s0, s31134; VI-NEXT: v_mov_b32_e32 v2, s41135; VI-NEXT: v_mov_b32_e32 v0, s01136; VI-NEXT: v_mov_b32_e32 v1, s11137; VI-NEXT: v_mov_b32_e32 v3, s51138; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1139; VI-NEXT: s_endpgm1140;1141; GFX9-LABEL: s_test_imin_sle_v4i16:1142; GFX9: ; %bb.0:1143; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81144; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01145; GFX9-NEXT: v_mov_b32_e32 v2, 01146; GFX9-NEXT: s_waitcnt lgkmcnt(0)1147; GFX9-NEXT: v_mov_b32_e32 v0, s31148; GFX9-NEXT: v_mov_b32_e32 v3, s21149; GFX9-NEXT: v_pk_min_i16 v1, s1, v01150; GFX9-NEXT: v_pk_min_i16 v0, s0, v31151; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]1152; GFX9-NEXT: s_endpgm1153;1154; GFX10-LABEL: s_test_imin_sle_v4i16:1155; GFX10: ; %bb.0:1156; GFX10-NEXT: s_clause 0x11157; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81158; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01159; GFX10-NEXT: v_mov_b32_e32 v2, 01160; GFX10-NEXT: s_waitcnt lgkmcnt(0)1161; GFX10-NEXT: v_pk_min_i16 v1, s1, s31162; GFX10-NEXT: v_pk_min_i16 v0, s0, s21163; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]1164; GFX10-NEXT: s_endpgm1165;1166; GFX11-LABEL: s_test_imin_sle_v4i16:1167; GFX11: ; %bb.0:1168; GFX11-NEXT: s_clause 0x11169; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x81170; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x01171; GFX11-NEXT: v_mov_b32_e32 v2, 01172; GFX11-NEXT: s_waitcnt lgkmcnt(0)1173; GFX11-NEXT: v_pk_min_i16 v1, s1, s31174; GFX11-NEXT: v_pk_min_i16 v0, s0, s21175; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]1176; GFX11-NEXT: s_endpgm1177;1178; GFX1250-LABEL: s_test_imin_sle_v4i16:1179; GFX1250: ; %bb.0:1180; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11181; GFX1250-NEXT: s_clause 0x11182; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x81183; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x01184; GFX1250-NEXT: v_mov_b32_e32 v2, 01185; GFX1250-NEXT: s_wait_kmcnt 0x01186; GFX1250-NEXT: v_pk_min_i16 v1, s1, s31187; GFX1250-NEXT: v_pk_min_i16 v0, s0, s21188; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[6:7]1189; GFX1250-NEXT: s_endpgm1190 %cmp = icmp sle <4 x i16> %a, %b1191 %val = select <4 x i1> %cmp, <4 x i16> %a, <4 x i16> %b1192 store <4 x i16> %val, ptr addrspace(1) %out1193 ret void1194}1195 1196define amdgpu_kernel void @v_test_imin_slt_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) #0 {1197; EG-LABEL: v_test_imin_slt_i32:1198; EG: ; %bb.0:1199; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]1200; EG-NEXT: TEX 1 @61201; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[]1202; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11203; EG-NEXT: CF_END1204; EG-NEXT: PAD1205; EG-NEXT: Fetch clause starting at 6:1206; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #11207; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11208; EG-NEXT: ALU clause starting at 10:1209; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1210; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1211; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,1212; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,1213; EG-NEXT: ALU clause starting at 14:1214; EG-NEXT: MIN_INT T0.X, T0.X, T1.X,1215; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1216; EG-NEXT: LSHR * T1.X, PV.W, literal.x,1217; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1218;1219; CI-LABEL: v_test_imin_slt_i32:1220; CI: ; %bb.0:1221; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01222; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x41223; CI-NEXT: v_lshlrev_b32_e32 v4, 2, v01224; CI-NEXT: s_add_i32 s12, s12, s171225; CI-NEXT: s_mov_b32 flat_scratch_lo, s131226; CI-NEXT: s_waitcnt lgkmcnt(0)1227; CI-NEXT: v_mov_b32_e32 v1, s31228; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v41229; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1230; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81231; CI-NEXT: v_mov_b32_e32 v3, s51232; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v41233; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1234; CI-NEXT: flat_load_dword v5, v[0:1]1235; CI-NEXT: flat_load_dword v2, v[2:3]1236; CI-NEXT: v_mov_b32_e32 v1, s11237; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v41238; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1239; CI-NEXT: s_waitcnt vmcnt(0)1240; CI-NEXT: v_min_i32_e32 v2, v5, v21241; CI-NEXT: flat_store_dword v[0:1], v21242; CI-NEXT: s_endpgm1243;1244; VI-LABEL: v_test_imin_slt_i32:1245; VI: ; %bb.0:1246; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01247; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101248; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v01249; VI-NEXT: s_add_i32 s12, s12, s171250; VI-NEXT: s_mov_b32 flat_scratch_lo, s131251; VI-NEXT: s_waitcnt lgkmcnt(0)1252; VI-NEXT: v_mov_b32_e32 v1, s31253; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41254; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1255; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81256; VI-NEXT: v_mov_b32_e32 v3, s51257; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41258; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1259; VI-NEXT: flat_load_dword v5, v[0:1]1260; VI-NEXT: flat_load_dword v2, v[2:3]1261; VI-NEXT: v_mov_b32_e32 v1, s11262; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v41263; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1264; VI-NEXT: s_waitcnt vmcnt(0)1265; VI-NEXT: v_min_i32_e32 v2, v5, v21266; VI-NEXT: flat_store_dword v[0:1], v21267; VI-NEXT: s_endpgm1268;1269; GFX9-LABEL: v_test_imin_slt_i32:1270; GFX9: ; %bb.0:1271; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01272; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101273; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v01274; GFX9-NEXT: s_waitcnt lgkmcnt(0)1275; GFX9-NEXT: global_load_dword v1, v0, s[2:3]1276; GFX9-NEXT: global_load_dword v2, v0, s[4:5]1277; GFX9-NEXT: s_waitcnt vmcnt(0)1278; GFX9-NEXT: v_min_i32_e32 v1, v1, v21279; GFX9-NEXT: global_store_dword v0, v1, s[0:1]1280; GFX9-NEXT: s_endpgm1281;1282; GFX10-LABEL: v_test_imin_slt_i32:1283; GFX10: ; %bb.0:1284; GFX10-NEXT: s_clause 0x11285; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01286; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101287; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v01288; GFX10-NEXT: s_waitcnt lgkmcnt(0)1289; GFX10-NEXT: s_clause 0x11290; GFX10-NEXT: global_load_dword v1, v0, s[2:3]1291; GFX10-NEXT: global_load_dword v2, v0, s[4:5]1292; GFX10-NEXT: s_waitcnt vmcnt(0)1293; GFX10-NEXT: v_min_i32_e32 v1, v1, v21294; GFX10-NEXT: global_store_dword v0, v1, s[0:1]1295; GFX10-NEXT: s_endpgm1296;1297; GFX11-LABEL: v_test_imin_slt_i32:1298; GFX11: ; %bb.0:1299; GFX11-NEXT: s_clause 0x11300; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x01301; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x101302; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v01303; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1304; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v01305; GFX11-NEXT: s_waitcnt lgkmcnt(0)1306; GFX11-NEXT: s_clause 0x11307; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]1308; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]1309; GFX11-NEXT: s_waitcnt vmcnt(0)1310; GFX11-NEXT: v_min_i32_e32 v1, v1, v21311; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1312; GFX11-NEXT: s_endpgm1313;1314; GFX1250-LABEL: v_test_imin_slt_i32:1315; GFX1250: ; %bb.0:1316; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11317; GFX1250-NEXT: s_clause 0x11318; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x01319; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x101320; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v01321; GFX1250-NEXT: s_wait_kmcnt 0x01322; GFX1250-NEXT: s_clause 0x11323; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset1324; GFX1250-NEXT: global_load_b32 v2, v0, s[6:7] scale_offset1325; GFX1250-NEXT: s_wait_loadcnt 0x01326; GFX1250-NEXT: v_min_i32_e32 v1, v1, v21327; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset1328; GFX1250-NEXT: s_endpgm1329 %tid = call i32 @llvm.amdgcn.workitem.id.x()1330 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %aptr, i32 %tid1331 %b.gep = getelementptr inbounds i32, ptr addrspace(1) %bptr, i32 %tid1332 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid1333 %a = load i32, ptr addrspace(1) %a.gep, align 41334 %b = load i32, ptr addrspace(1) %b.gep, align 41335 %cmp = icmp slt i32 %a, %b1336 %val = select i1 %cmp, i32 %a, i32 %b1337 store i32 %val, ptr addrspace(1) %out.gep, align 41338 ret void1339}1340 1341define amdgpu_kernel void @v_test_imin_slt_i16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) #0 {1342; EG-LABEL: v_test_imin_slt_i16:1343; EG: ; %bb.0:1344; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]1345; EG-NEXT: TEX 0 @81346; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]1347; EG-NEXT: TEX 0 @101348; EG-NEXT: ALU 16, @15, KC0[CB0:0-32], KC1[]1349; EG-NEXT: MEM_RAT MSKOR T1.XW, T0.X1350; EG-NEXT: CF_END1351; EG-NEXT: PAD1352; EG-NEXT: Fetch clause starting at 8:1353; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #11354; EG-NEXT: Fetch clause starting at 10:1355; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #11356; EG-NEXT: ALU clause starting at 12:1357; EG-NEXT: LSHL * T0.W, T0.X, 1,1358; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,1359; EG-NEXT: ALU clause starting at 14:1360; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, T0.W,1361; EG-NEXT: ALU clause starting at 15:1362; EG-NEXT: BFE_INT T0.Z, T0.X, 0.0, literal.x,1363; EG-NEXT: BFE_INT T1.W, T1.X, 0.0, literal.x, BS:VEC_120/SCL_2121364; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1365; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)1366; EG-NEXT: AND_INT T2.W, PS, literal.x,1367; EG-NEXT: MIN_INT * T1.W, PV.W, PV.Z,1368; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)1369; EG-NEXT: AND_INT T1.W, PS, literal.x,1370; EG-NEXT: LSHL * T2.W, PV.W, literal.y,1371; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)1372; EG-NEXT: LSHL T1.X, PV.W, PS,1373; EG-NEXT: LSHL * T1.W, literal.x, PS,1374; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)1375; EG-NEXT: MOV T1.Y, 0.0,1376; EG-NEXT: MOV * T1.Z, 0.0,1377; EG-NEXT: LSHR * T0.X, T0.W, literal.x,1378; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1379;1380; CI-LABEL: v_test_imin_slt_i16:1381; CI: ; %bb.0:1382; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01383; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x41384; CI-NEXT: v_lshlrev_b32_e32 v4, 1, v01385; CI-NEXT: s_add_i32 s12, s12, s171386; CI-NEXT: s_mov_b32 flat_scratch_lo, s131387; CI-NEXT: s_waitcnt lgkmcnt(0)1388; CI-NEXT: v_mov_b32_e32 v1, s31389; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v41390; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1391; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81392; CI-NEXT: v_mov_b32_e32 v3, s51393; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v41394; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1395; CI-NEXT: flat_load_sshort v5, v[0:1]1396; CI-NEXT: flat_load_sshort v2, v[2:3]1397; CI-NEXT: v_mov_b32_e32 v1, s11398; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v41399; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1400; CI-NEXT: s_waitcnt vmcnt(0)1401; CI-NEXT: v_min_i32_e32 v2, v5, v21402; CI-NEXT: flat_store_short v[0:1], v21403; CI-NEXT: s_endpgm1404;1405; VI-LABEL: v_test_imin_slt_i16:1406; VI: ; %bb.0:1407; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01408; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101409; VI-NEXT: v_lshlrev_b32_e32 v4, 1, v01410; VI-NEXT: s_add_i32 s12, s12, s171411; VI-NEXT: s_mov_b32 flat_scratch_lo, s131412; VI-NEXT: s_waitcnt lgkmcnt(0)1413; VI-NEXT: v_mov_b32_e32 v1, s31414; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41415; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1416; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81417; VI-NEXT: v_mov_b32_e32 v3, s51418; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41419; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1420; VI-NEXT: flat_load_ushort v5, v[0:1]1421; VI-NEXT: flat_load_ushort v2, v[2:3]1422; VI-NEXT: v_mov_b32_e32 v1, s11423; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v41424; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1425; VI-NEXT: s_waitcnt vmcnt(0)1426; VI-NEXT: v_min_i16_e32 v2, v5, v21427; VI-NEXT: flat_store_short v[0:1], v21428; VI-NEXT: s_endpgm1429;1430; GFX9-LABEL: v_test_imin_slt_i16:1431; GFX9: ; %bb.0:1432; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01433; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101434; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v01435; GFX9-NEXT: s_waitcnt lgkmcnt(0)1436; GFX9-NEXT: global_load_ushort v1, v0, s[2:3]1437; GFX9-NEXT: global_load_ushort v2, v0, s[4:5]1438; GFX9-NEXT: s_waitcnt vmcnt(0)1439; GFX9-NEXT: v_min_i16_e32 v1, v1, v21440; GFX9-NEXT: global_store_short v0, v1, s[0:1]1441; GFX9-NEXT: s_endpgm1442;1443; GFX10-LABEL: v_test_imin_slt_i16:1444; GFX10: ; %bb.0:1445; GFX10-NEXT: s_clause 0x11446; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01447; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101448; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v01449; GFX10-NEXT: s_waitcnt lgkmcnt(0)1450; GFX10-NEXT: s_clause 0x11451; GFX10-NEXT: global_load_ushort v1, v0, s[2:3]1452; GFX10-NEXT: global_load_ushort v2, v0, s[4:5]1453; GFX10-NEXT: s_waitcnt vmcnt(0)1454; GFX10-NEXT: v_min_i16 v1, v1, v21455; GFX10-NEXT: global_store_short v0, v1, s[0:1]1456; GFX10-NEXT: s_endpgm1457;1458; GFX11-TRUE16-LABEL: v_test_imin_slt_i16:1459; GFX11-TRUE16: ; %bb.0:1460; GFX11-TRUE16-NEXT: s_clause 0x11461; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x01462; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x101463; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v01464; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1465; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 1, v01466; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)1467; GFX11-TRUE16-NEXT: s_clause 0x11468; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]1469; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5]1470; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)1471; GFX11-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v0.h1472; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]1473; GFX11-TRUE16-NEXT: s_endpgm1474;1475; GFX11-FAKE16-LABEL: v_test_imin_slt_i16:1476; GFX11-FAKE16: ; %bb.0:1477; GFX11-FAKE16-NEXT: s_clause 0x11478; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x01479; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x101480; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v01481; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1482; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 1, v01483; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)1484; GFX11-FAKE16-NEXT: s_clause 0x11485; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]1486; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5]1487; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)1488; GFX11-FAKE16-NEXT: v_min_i16 v1, v1, v21489; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]1490; GFX11-FAKE16-NEXT: s_endpgm1491;1492; GFX1250-TRUE16-LABEL: v_test_imin_slt_i16:1493; GFX1250-TRUE16: ; %bb.0:1494; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11495; GFX1250-TRUE16-NEXT: s_clause 0x11496; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x01497; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x101498; GFX1250-TRUE16-NEXT: v_and_b32_e32 v1, 0x3ff, v01499; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x01500; GFX1250-TRUE16-NEXT: s_clause 0x11501; GFX1250-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] scale_offset1502; GFX1250-TRUE16-NEXT: global_load_u16 v2, v1, s[6:7] scale_offset1503; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x01504; GFX1250-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v2.l1505; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] scale_offset1506; GFX1250-TRUE16-NEXT: s_endpgm1507;1508; GFX1250-FAKE16-LABEL: v_test_imin_slt_i16:1509; GFX1250-FAKE16: ; %bb.0:1510; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11511; GFX1250-FAKE16-NEXT: s_clause 0x11512; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x01513; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x101514; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v01515; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x01516; GFX1250-FAKE16-NEXT: s_clause 0x11517; GFX1250-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] scale_offset1518; GFX1250-FAKE16-NEXT: global_load_u16 v2, v0, s[6:7] scale_offset1519; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x01520; GFX1250-FAKE16-NEXT: v_min_i16 v1, v1, v21521; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] scale_offset1522; GFX1250-FAKE16-NEXT: s_endpgm1523 %tid = call i32 @llvm.amdgcn.workitem.id.x()1524 %a.gep = getelementptr inbounds i16, ptr addrspace(1) %aptr, i32 %tid1525 %b.gep = getelementptr inbounds i16, ptr addrspace(1) %bptr, i32 %tid1526 %out.gep = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid1527 1528 %a = load i16, ptr addrspace(1) %a.gep1529 %b = load i16, ptr addrspace(1) %b.gep1530 %cmp = icmp slt i16 %a, %b1531 %val = select i1 %cmp, i16 %a, i16 %b1532 store i16 %val, ptr addrspace(1) %out.gep1533 ret void1534}1535 1536define amdgpu_kernel void @s_test_imin_slt_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {1537; EG-LABEL: s_test_imin_slt_i32:1538; EG: ; %bb.0:1539; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]1540; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 11541; EG-NEXT: CF_END1542; EG-NEXT: PAD1543; EG-NEXT: ALU clause starting at 4:1544; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,1545; EG-NEXT: MIN_INT * T1.X, KC0[2].Z, KC0[2].W,1546; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1547;1548; CI-LABEL: s_test_imin_slt_i32:1549; CI: ; %bb.0:1550; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01551; CI-NEXT: s_add_i32 s12, s12, s171552; CI-NEXT: s_mov_b32 flat_scratch_lo, s131553; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81554; CI-NEXT: s_waitcnt lgkmcnt(0)1555; CI-NEXT: s_min_i32 s2, s2, s31556; CI-NEXT: v_mov_b32_e32 v0, s01557; CI-NEXT: v_mov_b32_e32 v1, s11558; CI-NEXT: v_mov_b32_e32 v2, s21559; CI-NEXT: flat_store_dword v[0:1], v21560; CI-NEXT: s_endpgm1561;1562; VI-LABEL: s_test_imin_slt_i32:1563; VI: ; %bb.0:1564; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01565; VI-NEXT: s_add_i32 s12, s12, s171566; VI-NEXT: s_mov_b32 flat_scratch_lo, s131567; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81568; VI-NEXT: s_waitcnt lgkmcnt(0)1569; VI-NEXT: s_min_i32 s2, s2, s31570; VI-NEXT: v_mov_b32_e32 v0, s01571; VI-NEXT: v_mov_b32_e32 v1, s11572; VI-NEXT: v_mov_b32_e32 v2, s21573; VI-NEXT: flat_store_dword v[0:1], v21574; VI-NEXT: s_endpgm1575;1576; GFX9-LABEL: s_test_imin_slt_i32:1577; GFX9: ; %bb.0:1578; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01579; GFX9-NEXT: v_mov_b32_e32 v0, 01580; GFX9-NEXT: s_waitcnt lgkmcnt(0)1581; GFX9-NEXT: s_min_i32 s2, s2, s31582; GFX9-NEXT: v_mov_b32_e32 v1, s21583; GFX9-NEXT: global_store_dword v0, v1, s[0:1]1584; GFX9-NEXT: s_endpgm1585;1586; GFX10-LABEL: s_test_imin_slt_i32:1587; GFX10: ; %bb.0:1588; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01589; GFX10-NEXT: v_mov_b32_e32 v0, 01590; GFX10-NEXT: s_waitcnt lgkmcnt(0)1591; GFX10-NEXT: s_min_i32 s2, s2, s31592; GFX10-NEXT: v_mov_b32_e32 v1, s21593; GFX10-NEXT: global_store_dword v0, v1, s[0:1]1594; GFX10-NEXT: s_endpgm1595;1596; GFX11-LABEL: s_test_imin_slt_i32:1597; GFX11: ; %bb.0:1598; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x01599; GFX11-NEXT: v_mov_b32_e32 v0, 01600; GFX11-NEXT: s_waitcnt lgkmcnt(0)1601; GFX11-NEXT: s_min_i32 s2, s2, s31602; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1603; GFX11-NEXT: v_mov_b32_e32 v1, s21604; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1605; GFX11-NEXT: s_endpgm1606;1607; GFX1250-LABEL: s_test_imin_slt_i32:1608; GFX1250: ; %bb.0:1609; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11610; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x01611; GFX1250-NEXT: v_mov_b32_e32 v0, 01612; GFX1250-NEXT: s_wait_kmcnt 0x01613; GFX1250-NEXT: s_min_i32 s2, s2, s31614; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1615; GFX1250-NEXT: v_mov_b32_e32 v1, s21616; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]1617; GFX1250-NEXT: s_endpgm1618 %cmp = icmp slt i32 %a, %b1619 %val = select i1 %cmp, i32 %a, i32 %b1620 store i32 %val, ptr addrspace(1) %out, align 41621 ret void1622}1623 1624define amdgpu_kernel void @s_test_imin_slt_v2i32(ptr addrspace(1) %out, <2 x i32> %a, <2 x i32> %b) #0 {1625; EG-LABEL: s_test_imin_slt_v2i32:1626; EG: ; %bb.0:1627; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]1628; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 11629; EG-NEXT: CF_END1630; EG-NEXT: PAD1631; EG-NEXT: ALU clause starting at 4:1632; EG-NEXT: MIN_INT * T0.Y, KC0[3].X, KC0[3].Z,1633; EG-NEXT: MIN_INT * T0.X, KC0[2].W, KC0[3].Y,1634; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1635; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1636;1637; CI-LABEL: s_test_imin_slt_v2i32:1638; CI: ; %bb.0:1639; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x21640; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01641; CI-NEXT: s_add_i32 s12, s12, s171642; CI-NEXT: s_mov_b32 flat_scratch_lo, s131643; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81644; CI-NEXT: s_waitcnt lgkmcnt(0)1645; CI-NEXT: s_min_i32 s1, s1, s31646; CI-NEXT: s_min_i32 s0, s0, s21647; CI-NEXT: v_mov_b32_e32 v2, s41648; CI-NEXT: v_mov_b32_e32 v0, s01649; CI-NEXT: v_mov_b32_e32 v1, s11650; CI-NEXT: v_mov_b32_e32 v3, s51651; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1652; CI-NEXT: s_endpgm1653;1654; VI-LABEL: s_test_imin_slt_v2i32:1655; VI: ; %bb.0:1656; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81657; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01658; VI-NEXT: s_add_i32 s12, s12, s171659; VI-NEXT: s_mov_b32 flat_scratch_lo, s131660; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81661; VI-NEXT: s_waitcnt lgkmcnt(0)1662; VI-NEXT: s_min_i32 s1, s1, s31663; VI-NEXT: s_min_i32 s0, s0, s21664; VI-NEXT: v_mov_b32_e32 v2, s41665; VI-NEXT: v_mov_b32_e32 v0, s01666; VI-NEXT: v_mov_b32_e32 v1, s11667; VI-NEXT: v_mov_b32_e32 v3, s51668; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]1669; VI-NEXT: s_endpgm1670;1671; GFX9-LABEL: s_test_imin_slt_v2i32:1672; GFX9: ; %bb.0:1673; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81674; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01675; GFX9-NEXT: v_mov_b32_e32 v2, 01676; GFX9-NEXT: s_waitcnt lgkmcnt(0)1677; GFX9-NEXT: s_min_i32 s1, s1, s31678; GFX9-NEXT: s_min_i32 s0, s0, s21679; GFX9-NEXT: v_mov_b32_e32 v0, s01680; GFX9-NEXT: v_mov_b32_e32 v1, s11681; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]1682; GFX9-NEXT: s_endpgm1683;1684; GFX10-LABEL: s_test_imin_slt_v2i32:1685; GFX10: ; %bb.0:1686; GFX10-NEXT: s_clause 0x11687; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x81688; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x01689; GFX10-NEXT: v_mov_b32_e32 v2, 01690; GFX10-NEXT: s_waitcnt lgkmcnt(0)1691; GFX10-NEXT: s_min_i32 s0, s0, s21692; GFX10-NEXT: s_min_i32 s1, s1, s31693; GFX10-NEXT: v_mov_b32_e32 v0, s01694; GFX10-NEXT: v_mov_b32_e32 v1, s11695; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]1696; GFX10-NEXT: s_endpgm1697;1698; GFX11-LABEL: s_test_imin_slt_v2i32:1699; GFX11: ; %bb.0:1700; GFX11-NEXT: s_clause 0x11701; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x81702; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x01703; GFX11-NEXT: v_mov_b32_e32 v2, 01704; GFX11-NEXT: s_waitcnt lgkmcnt(0)1705; GFX11-NEXT: s_min_i32 s0, s0, s21706; GFX11-NEXT: s_min_i32 s1, s1, s31707; GFX11-NEXT: v_mov_b32_e32 v0, s01708; GFX11-NEXT: v_mov_b32_e32 v1, s11709; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]1710; GFX11-NEXT: s_endpgm1711;1712; GFX1250-LABEL: s_test_imin_slt_v2i32:1713; GFX1250: ; %bb.0:1714; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11715; GFX1250-NEXT: s_clause 0x11716; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x81717; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x01718; GFX1250-NEXT: v_mov_b32_e32 v2, 01719; GFX1250-NEXT: s_wait_kmcnt 0x01720; GFX1250-NEXT: s_min_i32 s0, s0, s21721; GFX1250-NEXT: s_min_i32 s1, s1, s31722; GFX1250-NEXT: v_mov_b32_e32 v0, s01723; GFX1250-NEXT: v_mov_b32_e32 v1, s11724; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[6:7]1725; GFX1250-NEXT: s_endpgm1726 %cmp = icmp slt <2 x i32> %a, %b1727 %val = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b1728 store <2 x i32> %val, ptr addrspace(1) %out1729 ret void1730}1731 1732define amdgpu_kernel void @s_test_imin_slt_imm_i32(ptr addrspace(1) %out, i32 %a) #0 {1733; EG-LABEL: s_test_imin_slt_imm_i32:1734; EG: ; %bb.0:1735; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]1736; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 11737; EG-NEXT: CF_END1738; EG-NEXT: PAD1739; EG-NEXT: ALU clause starting at 4:1740; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,1741; EG-NEXT: MIN_INT * T1.X, KC0[2].Z, literal.y,1742; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)1743;1744; CI-LABEL: s_test_imin_slt_imm_i32:1745; CI: ; %bb.0:1746; CI-NEXT: s_load_dword s2, s[8:9], 0x21747; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01748; CI-NEXT: s_add_i32 s12, s12, s171749; CI-NEXT: s_mov_b32 flat_scratch_lo, s131750; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81751; CI-NEXT: s_waitcnt lgkmcnt(0)1752; CI-NEXT: s_min_i32 s2, s2, 81753; CI-NEXT: v_mov_b32_e32 v0, s01754; CI-NEXT: v_mov_b32_e32 v1, s11755; CI-NEXT: v_mov_b32_e32 v2, s21756; CI-NEXT: flat_store_dword v[0:1], v21757; CI-NEXT: s_endpgm1758;1759; VI-LABEL: s_test_imin_slt_imm_i32:1760; VI: ; %bb.0:1761; VI-NEXT: s_load_dword s2, s[8:9], 0x81762; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01763; VI-NEXT: s_add_i32 s12, s12, s171764; VI-NEXT: s_mov_b32 flat_scratch_lo, s131765; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81766; VI-NEXT: s_waitcnt lgkmcnt(0)1767; VI-NEXT: s_min_i32 s2, s2, 81768; VI-NEXT: v_mov_b32_e32 v0, s01769; VI-NEXT: v_mov_b32_e32 v1, s11770; VI-NEXT: v_mov_b32_e32 v2, s21771; VI-NEXT: flat_store_dword v[0:1], v21772; VI-NEXT: s_endpgm1773;1774; GFX9-LABEL: s_test_imin_slt_imm_i32:1775; GFX9: ; %bb.0:1776; GFX9-NEXT: s_load_dword s2, s[8:9], 0x81777; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01778; GFX9-NEXT: v_mov_b32_e32 v0, 01779; GFX9-NEXT: s_waitcnt lgkmcnt(0)1780; GFX9-NEXT: s_min_i32 s2, s2, 81781; GFX9-NEXT: v_mov_b32_e32 v1, s21782; GFX9-NEXT: global_store_dword v0, v1, s[0:1]1783; GFX9-NEXT: s_endpgm1784;1785; GFX10-LABEL: s_test_imin_slt_imm_i32:1786; GFX10: ; %bb.0:1787; GFX10-NEXT: s_clause 0x11788; GFX10-NEXT: s_load_dword s2, s[8:9], 0x81789; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01790; GFX10-NEXT: v_mov_b32_e32 v0, 01791; GFX10-NEXT: s_waitcnt lgkmcnt(0)1792; GFX10-NEXT: s_min_i32 s2, s2, 81793; GFX10-NEXT: v_mov_b32_e32 v1, s21794; GFX10-NEXT: global_store_dword v0, v1, s[0:1]1795; GFX10-NEXT: s_endpgm1796;1797; GFX11-LABEL: s_test_imin_slt_imm_i32:1798; GFX11: ; %bb.0:1799; GFX11-NEXT: s_clause 0x11800; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x81801; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x01802; GFX11-NEXT: v_mov_b32_e32 v0, 01803; GFX11-NEXT: s_waitcnt lgkmcnt(0)1804; GFX11-NEXT: s_min_i32 s2, s2, 81805; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1806; GFX11-NEXT: v_mov_b32_e32 v1, s21807; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1808; GFX11-NEXT: s_endpgm1809;1810; GFX1250-LABEL: s_test_imin_slt_imm_i32:1811; GFX1250: ; %bb.0:1812; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11813; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x01814; GFX1250-NEXT: v_mov_b32_e32 v0, 01815; GFX1250-NEXT: s_wait_kmcnt 0x01816; GFX1250-NEXT: s_min_i32 s2, s2, 81817; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1818; GFX1250-NEXT: v_mov_b32_e32 v1, s21819; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]1820; GFX1250-NEXT: s_endpgm1821 %cmp = icmp slt i32 %a, 81822 %val = select i1 %cmp, i32 %a, i32 81823 store i32 %val, ptr addrspace(1) %out, align 41824 ret void1825}1826 1827define amdgpu_kernel void @s_test_imin_sle_imm_i32(ptr addrspace(1) %out, i32 %a) #0 {1828; EG-LABEL: s_test_imin_sle_imm_i32:1829; EG: ; %bb.0:1830; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]1831; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 11832; EG-NEXT: CF_END1833; EG-NEXT: PAD1834; EG-NEXT: ALU clause starting at 4:1835; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,1836; EG-NEXT: MIN_INT * T1.X, KC0[2].Z, literal.y,1837; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)1838;1839; CI-LABEL: s_test_imin_sle_imm_i32:1840; CI: ; %bb.0:1841; CI-NEXT: s_load_dword s2, s[8:9], 0x21842; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01843; CI-NEXT: s_add_i32 s12, s12, s171844; CI-NEXT: s_mov_b32 flat_scratch_lo, s131845; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81846; CI-NEXT: s_waitcnt lgkmcnt(0)1847; CI-NEXT: s_min_i32 s2, s2, 81848; CI-NEXT: v_mov_b32_e32 v0, s01849; CI-NEXT: v_mov_b32_e32 v1, s11850; CI-NEXT: v_mov_b32_e32 v2, s21851; CI-NEXT: flat_store_dword v[0:1], v21852; CI-NEXT: s_endpgm1853;1854; VI-LABEL: s_test_imin_sle_imm_i32:1855; VI: ; %bb.0:1856; VI-NEXT: s_load_dword s2, s[8:9], 0x81857; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01858; VI-NEXT: s_add_i32 s12, s12, s171859; VI-NEXT: s_mov_b32 flat_scratch_lo, s131860; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81861; VI-NEXT: s_waitcnt lgkmcnt(0)1862; VI-NEXT: s_min_i32 s2, s2, 81863; VI-NEXT: v_mov_b32_e32 v0, s01864; VI-NEXT: v_mov_b32_e32 v1, s11865; VI-NEXT: v_mov_b32_e32 v2, s21866; VI-NEXT: flat_store_dword v[0:1], v21867; VI-NEXT: s_endpgm1868;1869; GFX9-LABEL: s_test_imin_sle_imm_i32:1870; GFX9: ; %bb.0:1871; GFX9-NEXT: s_load_dword s2, s[8:9], 0x81872; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01873; GFX9-NEXT: v_mov_b32_e32 v0, 01874; GFX9-NEXT: s_waitcnt lgkmcnt(0)1875; GFX9-NEXT: s_min_i32 s2, s2, 81876; GFX9-NEXT: v_mov_b32_e32 v1, s21877; GFX9-NEXT: global_store_dword v0, v1, s[0:1]1878; GFX9-NEXT: s_endpgm1879;1880; GFX10-LABEL: s_test_imin_sle_imm_i32:1881; GFX10: ; %bb.0:1882; GFX10-NEXT: s_clause 0x11883; GFX10-NEXT: s_load_dword s2, s[8:9], 0x81884; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x01885; GFX10-NEXT: v_mov_b32_e32 v0, 01886; GFX10-NEXT: s_waitcnt lgkmcnt(0)1887; GFX10-NEXT: s_min_i32 s2, s2, 81888; GFX10-NEXT: v_mov_b32_e32 v1, s21889; GFX10-NEXT: global_store_dword v0, v1, s[0:1]1890; GFX10-NEXT: s_endpgm1891;1892; GFX11-LABEL: s_test_imin_sle_imm_i32:1893; GFX11: ; %bb.0:1894; GFX11-NEXT: s_clause 0x11895; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x81896; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x01897; GFX11-NEXT: v_mov_b32_e32 v0, 01898; GFX11-NEXT: s_waitcnt lgkmcnt(0)1899; GFX11-NEXT: s_min_i32 s2, s2, 81900; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1901; GFX11-NEXT: v_mov_b32_e32 v1, s21902; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]1903; GFX11-NEXT: s_endpgm1904;1905; GFX1250-LABEL: s_test_imin_sle_imm_i32:1906; GFX1250: ; %bb.0:1907; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11908; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x01909; GFX1250-NEXT: v_mov_b32_e32 v0, 01910; GFX1250-NEXT: s_wait_kmcnt 0x01911; GFX1250-NEXT: s_min_i32 s2, s2, 81912; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1913; GFX1250-NEXT: v_mov_b32_e32 v1, s21914; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]1915; GFX1250-NEXT: s_endpgm1916 %cmp = icmp sle i32 %a, 81917 %val = select i1 %cmp, i32 %a, i32 81918 store i32 %val, ptr addrspace(1) %out, align 41919 ret void1920}1921 1922define amdgpu_kernel void @v_test_umin_ule_i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {1923; EG-LABEL: v_test_umin_ule_i32:1924; EG: ; %bb.0:1925; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]1926; EG-NEXT: TEX 1 @61927; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[]1928; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11929; EG-NEXT: CF_END1930; EG-NEXT: PAD1931; EG-NEXT: Fetch clause starting at 6:1932; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #11933; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11934; EG-NEXT: ALU clause starting at 10:1935; EG-NEXT: LSHL * T0.W, T0.X, literal.x,1936; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1937; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,1938; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,1939; EG-NEXT: ALU clause starting at 14:1940; EG-NEXT: MIN_UINT T0.X, T0.X, T1.X,1941; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,1942; EG-NEXT: LSHR * T1.X, PV.W, literal.x,1943; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1944;1945; CI-LABEL: v_test_umin_ule_i32:1946; CI: ; %bb.0:1947; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01948; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x41949; CI-NEXT: v_lshlrev_b32_e32 v4, 2, v01950; CI-NEXT: s_add_i32 s12, s12, s171951; CI-NEXT: s_mov_b32 flat_scratch_lo, s131952; CI-NEXT: s_waitcnt lgkmcnt(0)1953; CI-NEXT: v_mov_b32_e32 v1, s31954; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v41955; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1956; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81957; CI-NEXT: v_mov_b32_e32 v3, s51958; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v41959; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1960; CI-NEXT: flat_load_dword v5, v[0:1]1961; CI-NEXT: flat_load_dword v2, v[2:3]1962; CI-NEXT: v_mov_b32_e32 v1, s11963; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v41964; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1965; CI-NEXT: s_waitcnt vmcnt(0)1966; CI-NEXT: v_min_u32_e32 v2, v5, v21967; CI-NEXT: flat_store_dword v[0:1], v21968; CI-NEXT: s_endpgm1969;1970; VI-LABEL: v_test_umin_ule_i32:1971; VI: ; %bb.0:1972; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01973; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101974; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v01975; VI-NEXT: s_add_i32 s12, s12, s171976; VI-NEXT: s_mov_b32 flat_scratch_lo, s131977; VI-NEXT: s_waitcnt lgkmcnt(0)1978; VI-NEXT: v_mov_b32_e32 v1, s31979; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v41980; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1981; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 81982; VI-NEXT: v_mov_b32_e32 v3, s51983; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v41984; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc1985; VI-NEXT: flat_load_dword v5, v[0:1]1986; VI-NEXT: flat_load_dword v2, v[2:3]1987; VI-NEXT: v_mov_b32_e32 v1, s11988; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v41989; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc1990; VI-NEXT: s_waitcnt vmcnt(0)1991; VI-NEXT: v_min_u32_e32 v2, v5, v21992; VI-NEXT: flat_store_dword v[0:1], v21993; VI-NEXT: s_endpgm1994;1995; GFX9-LABEL: v_test_umin_ule_i32:1996; GFX9: ; %bb.0:1997; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x01998; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x101999; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v02000; GFX9-NEXT: s_waitcnt lgkmcnt(0)2001; GFX9-NEXT: global_load_dword v1, v0, s[2:3]2002; GFX9-NEXT: global_load_dword v2, v0, s[4:5]2003; GFX9-NEXT: s_waitcnt vmcnt(0)2004; GFX9-NEXT: v_min_u32_e32 v1, v1, v22005; GFX9-NEXT: global_store_dword v0, v1, s[0:1]2006; GFX9-NEXT: s_endpgm2007;2008; GFX10-LABEL: v_test_umin_ule_i32:2009; GFX10: ; %bb.0:2010; GFX10-NEXT: s_clause 0x12011; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02012; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102013; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v02014; GFX10-NEXT: s_waitcnt lgkmcnt(0)2015; GFX10-NEXT: s_clause 0x12016; GFX10-NEXT: global_load_dword v1, v0, s[2:3]2017; GFX10-NEXT: global_load_dword v2, v0, s[4:5]2018; GFX10-NEXT: s_waitcnt vmcnt(0)2019; GFX10-NEXT: v_min_u32_e32 v1, v1, v22020; GFX10-NEXT: global_store_dword v0, v1, s[0:1]2021; GFX10-NEXT: s_endpgm2022;2023; GFX11-LABEL: v_test_umin_ule_i32:2024; GFX11: ; %bb.0:2025; GFX11-NEXT: s_clause 0x12026; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x02027; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x102028; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02029; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2030; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v02031; GFX11-NEXT: s_waitcnt lgkmcnt(0)2032; GFX11-NEXT: s_clause 0x12033; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2034; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2035; GFX11-NEXT: s_waitcnt vmcnt(0)2036; GFX11-NEXT: v_min_u32_e32 v1, v1, v22037; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2038; GFX11-NEXT: s_endpgm2039;2040; GFX1250-LABEL: v_test_umin_ule_i32:2041; GFX1250: ; %bb.0:2042; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12043; GFX1250-NEXT: s_clause 0x12044; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x02045; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x102046; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v02047; GFX1250-NEXT: s_wait_kmcnt 0x02048; GFX1250-NEXT: s_clause 0x12049; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset2050; GFX1250-NEXT: global_load_b32 v2, v0, s[6:7] scale_offset2051; GFX1250-NEXT: s_wait_loadcnt 0x02052; GFX1250-NEXT: v_min_u32_e32 v1, v1, v22053; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset2054; GFX1250-NEXT: s_endpgm2055 %tid = call i32 @llvm.amdgcn.workitem.id.x()2056 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i32 %tid2057 %b.gep = getelementptr inbounds i32, ptr addrspace(1) %b.ptr, i32 %tid2058 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid2059 %a = load i32, ptr addrspace(1) %a.gep, align 42060 %b = load i32, ptr addrspace(1) %b.gep, align 42061 %cmp = icmp ule i32 %a, %b2062 %val = select i1 %cmp, i32 %a, i32 %b2063 store i32 %val, ptr addrspace(1) %out.gep, align 42064 ret void2065}2066 2067define amdgpu_kernel void @v_test_umin_ule_v3i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2068; EG-LABEL: v_test_umin_ule_v3i32:2069; EG: ; %bb.0:2070; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]2071; EG-NEXT: TEX 1 @62072; EG-NEXT: ALU 9, @14, KC0[CB0:0-32], KC1[]2073; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 02074; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 12075; EG-NEXT: CF_END2076; EG-NEXT: Fetch clause starting at 6:2077; EG-NEXT: VTX_READ_128 T1.XYZW, T1.X, 0, #12078; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #12079; EG-NEXT: ALU clause starting at 10:2080; EG-NEXT: LSHL * T0.W, T0.X, literal.x,2081; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)2082; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,2083; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,2084; EG-NEXT: ALU clause starting at 14:2085; EG-NEXT: MIN_UINT * T0.Y, T2.Y, T1.Y,2086; EG-NEXT: MIN_UINT T0.X, T2.X, T1.X,2087; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,2088; EG-NEXT: LSHR T1.X, PV.W, literal.x,2089; EG-NEXT: MIN_UINT * T2.X, T2.Z, T1.Z,2090; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2091; EG-NEXT: ADD_INT * T0.W, T0.W, literal.x,2092; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)2093; EG-NEXT: LSHR * T3.X, PV.W, literal.x,2094; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2095;2096; CI-LABEL: v_test_umin_ule_v3i32:2097; CI: ; %bb.0:2098; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02099; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x42100; CI-NEXT: v_lshlrev_b32_e32 v6, 4, v02101; CI-NEXT: s_add_i32 s12, s12, s172102; CI-NEXT: s_mov_b32 flat_scratch_lo, s132103; CI-NEXT: s_waitcnt lgkmcnt(0)2104; CI-NEXT: v_mov_b32_e32 v1, s32105; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v62106; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2107; CI-NEXT: v_mov_b32_e32 v2, s52108; CI-NEXT: v_add_i32_e32 v3, vcc, s4, v62109; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82110; CI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc2111; CI-NEXT: flat_load_dwordx3 v[0:2], v[0:1]2112; CI-NEXT: flat_load_dwordx3 v[3:5], v[3:4]2113; CI-NEXT: v_mov_b32_e32 v7, s12114; CI-NEXT: v_add_i32_e32 v6, vcc, s0, v62115; CI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc2116; CI-NEXT: s_waitcnt vmcnt(0)2117; CI-NEXT: v_min_u32_e32 v2, v2, v52118; CI-NEXT: v_min_u32_e32 v1, v1, v42119; CI-NEXT: v_min_u32_e32 v0, v0, v32120; CI-NEXT: flat_store_dwordx3 v[6:7], v[0:2]2121; CI-NEXT: s_endpgm2122;2123; VI-LABEL: v_test_umin_ule_v3i32:2124; VI: ; %bb.0:2125; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02126; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102127; VI-NEXT: v_lshlrev_b32_e32 v6, 4, v02128; VI-NEXT: s_add_i32 s12, s12, s172129; VI-NEXT: s_mov_b32 flat_scratch_lo, s132130; VI-NEXT: s_waitcnt lgkmcnt(0)2131; VI-NEXT: v_mov_b32_e32 v1, s32132; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v62133; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2134; VI-NEXT: v_mov_b32_e32 v2, s52135; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v62136; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82137; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc2138; VI-NEXT: flat_load_dwordx3 v[0:2], v[0:1]2139; VI-NEXT: flat_load_dwordx3 v[3:5], v[3:4]2140; VI-NEXT: v_mov_b32_e32 v7, s12141; VI-NEXT: v_add_u32_e32 v6, vcc, s0, v62142; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc2143; VI-NEXT: s_waitcnt vmcnt(0)2144; VI-NEXT: v_min_u32_e32 v2, v2, v52145; VI-NEXT: v_min_u32_e32 v1, v1, v42146; VI-NEXT: v_min_u32_e32 v0, v0, v32147; VI-NEXT: flat_store_dwordx3 v[6:7], v[0:2]2148; VI-NEXT: s_endpgm2149;2150; GFX9-LABEL: v_test_umin_ule_v3i32:2151; GFX9: ; %bb.0:2152; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02153; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102154; GFX9-NEXT: v_lshlrev_b32_e32 v6, 4, v02155; GFX9-NEXT: s_waitcnt lgkmcnt(0)2156; GFX9-NEXT: global_load_dwordx3 v[0:2], v6, s[2:3]2157; GFX9-NEXT: global_load_dwordx3 v[3:5], v6, s[4:5]2158; GFX9-NEXT: s_waitcnt vmcnt(0)2159; GFX9-NEXT: v_min_u32_e32 v2, v2, v52160; GFX9-NEXT: v_min_u32_e32 v1, v1, v42161; GFX9-NEXT: v_min_u32_e32 v0, v0, v32162; GFX9-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]2163; GFX9-NEXT: s_endpgm2164;2165; GFX10-LABEL: v_test_umin_ule_v3i32:2166; GFX10: ; %bb.0:2167; GFX10-NEXT: s_clause 0x12168; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02169; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102170; GFX10-NEXT: v_lshlrev_b32_e32 v6, 4, v02171; GFX10-NEXT: s_waitcnt lgkmcnt(0)2172; GFX10-NEXT: s_clause 0x12173; GFX10-NEXT: global_load_dwordx3 v[0:2], v6, s[2:3]2174; GFX10-NEXT: global_load_dwordx3 v[3:5], v6, s[4:5]2175; GFX10-NEXT: s_waitcnt vmcnt(0)2176; GFX10-NEXT: v_min_u32_e32 v2, v2, v52177; GFX10-NEXT: v_min_u32_e32 v1, v1, v42178; GFX10-NEXT: v_min_u32_e32 v0, v0, v32179; GFX10-NEXT: global_store_dwordx3 v6, v[0:2], s[0:1]2180; GFX10-NEXT: s_endpgm2181;2182; GFX11-LABEL: v_test_umin_ule_v3i32:2183; GFX11: ; %bb.0:2184; GFX11-NEXT: s_clause 0x12185; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x02186; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x102187; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02188; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2189; GFX11-NEXT: v_lshlrev_b32_e32 v6, 4, v02190; GFX11-NEXT: s_waitcnt lgkmcnt(0)2191; GFX11-NEXT: s_clause 0x12192; GFX11-NEXT: global_load_b96 v[0:2], v6, s[2:3]2193; GFX11-NEXT: global_load_b96 v[3:5], v6, s[4:5]2194; GFX11-NEXT: s_waitcnt vmcnt(0)2195; GFX11-NEXT: v_min_u32_e32 v2, v2, v52196; GFX11-NEXT: v_min_u32_e32 v1, v1, v42197; GFX11-NEXT: v_min_u32_e32 v0, v0, v32198; GFX11-NEXT: global_store_b96 v6, v[0:2], s[0:1]2199; GFX11-NEXT: s_endpgm2200;2201; GFX1250-LABEL: v_test_umin_ule_v3i32:2202; GFX1250: ; %bb.0:2203; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12204; GFX1250-NEXT: s_clause 0x12205; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x02206; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x102207; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v02208; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)2209; GFX1250-NEXT: v_lshlrev_b32_e32 v3, 4, v02210; GFX1250-NEXT: s_wait_kmcnt 0x02211; GFX1250-NEXT: s_clause 0x12212; GFX1250-NEXT: global_load_b96 v[0:2], v3, s[2:3]2213; GFX1250-NEXT: global_load_b96 v[4:6], v3, s[6:7]2214; GFX1250-NEXT: s_wait_loadcnt 0x02215; GFX1250-NEXT: v_min_u32_e32 v2, v2, v62216; GFX1250-NEXT: v_min_u32_e32 v1, v1, v52217; GFX1250-NEXT: v_min_u32_e32 v0, v0, v42218; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[0:1]2219; GFX1250-NEXT: s_endpgm2220 %tid = call i32 @llvm.amdgcn.workitem.id.x()2221 %a.gep = getelementptr inbounds <3 x i32>, ptr addrspace(1) %a.ptr, i32 %tid2222 %b.gep = getelementptr inbounds <3 x i32>, ptr addrspace(1) %b.ptr, i32 %tid2223 %out.gep = getelementptr inbounds <3 x i32>, ptr addrspace(1) %out, i32 %tid2224 2225 %a = load <3 x i32>, ptr addrspace(1) %a.gep2226 %b = load <3 x i32>, ptr addrspace(1) %b.gep2227 %cmp = icmp ule <3 x i32> %a, %b2228 %val = select <3 x i1> %cmp, <3 x i32> %a, <3 x i32> %b2229 store <3 x i32> %val, ptr addrspace(1) %out.gep2230 ret void2231}2232 2233; FIXME: Reduce unused packed component to scalar2234 2235define amdgpu_kernel void @v_test_umin_ule_v3i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2236; EG-LABEL: v_test_umin_ule_v3i16:2237; EG: ; %bb.0:2238; EG-NEXT: ALU 3, @20, KC0[CB0:0-32], KC1[]2239; EG-NEXT: TEX 1 @82240; EG-NEXT: ALU 11, @24, KC0[CB0:0-32], KC1[]2241; EG-NEXT: TEX 3 @122242; EG-NEXT: ALU 8, @36, KC0[], KC1[]2243; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T8.X, 02244; EG-NEXT: MEM_RAT MSKOR T7.XW, T0.X2245; EG-NEXT: CF_END2246; EG-NEXT: Fetch clause starting at 8:2247; EG-NEXT: VTX_READ_16 T7.X, T6.X, 4, #12248; EG-NEXT: VTX_READ_16 T8.X, T0.X, 4, #12249; EG-NEXT: Fetch clause starting at 12:2250; EG-NEXT: VTX_READ_16 T8.X, T6.X, 0, #12251; EG-NEXT: VTX_READ_16 T9.X, T0.X, 0, #12252; EG-NEXT: VTX_READ_16 T6.X, T6.X, 2, #12253; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #12254; EG-NEXT: ALU clause starting at 20:2255; EG-NEXT: LSHL * T0.W, T0.X, literal.x,2256; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2257; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,2258; EG-NEXT: ADD_INT * T6.X, KC0[2].W, PV.W,2259; EG-NEXT: ALU clause starting at 24:2260; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,2261; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x,2262; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)2263; EG-NEXT: AND_INT * T2.W, PV.W, literal.x,2264; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2265; EG-NEXT: LSHL T2.W, PV.W, literal.x,2266; EG-NEXT: MIN_UINT * T3.W, T8.X, T7.X,2267; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2268; EG-NEXT: LSHL T7.X, PS, PV.W,2269; EG-NEXT: LSHL * T7.W, literal.x, PV.W,2270; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)2271; EG-NEXT: MOV * T7.Y, 0.0,2272; EG-NEXT: ALU clause starting at 36:2273; EG-NEXT: MOV T7.Z, 0.0,2274; EG-NEXT: MIN_UINT * T2.W, T0.X, T6.X,2275; EG-NEXT: LSHR T0.X, T1.W, literal.x,2276; EG-NEXT: LSHL T1.W, PV.W, literal.y,2277; EG-NEXT: MIN_UINT * T2.W, T9.X, T8.X,2278; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)2279; EG-NEXT: OR_INT T6.X, PV.W, PS,2280; EG-NEXT: LSHR * T8.X, T0.W, literal.x,2281; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2282;2283; CI-LABEL: v_test_umin_ule_v3i16:2284; CI: ; %bb.0:2285; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02286; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x42287; CI-NEXT: v_lshlrev_b32_e32 v4, 3, v02288; CI-NEXT: s_add_i32 s12, s12, s172289; CI-NEXT: s_mov_b32 flat_scratch_lo, s132290; CI-NEXT: s_waitcnt lgkmcnt(0)2291; CI-NEXT: v_mov_b32_e32 v1, s32292; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v42293; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2294; CI-NEXT: v_mov_b32_e32 v3, s52295; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v42296; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82297; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2298; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]2299; CI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]2300; CI-NEXT: v_mov_b32_e32 v5, s12301; CI-NEXT: v_add_i32_e32 v4, vcc, s0, v42302; CI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2303; CI-NEXT: v_add_i32_e32 v6, vcc, 4, v42304; CI-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc2305; CI-NEXT: s_waitcnt vmcnt(1)2306; CI-NEXT: v_lshrrev_b32_e32 v8, 16, v02307; CI-NEXT: v_and_b32_e32 v0, 0xffff, v02308; CI-NEXT: s_waitcnt vmcnt(0)2309; CI-NEXT: v_lshrrev_b32_e32 v9, 16, v22310; CI-NEXT: v_and_b32_e32 v2, 0xffff, v22311; CI-NEXT: v_and_b32_e32 v1, 0xffff, v12312; CI-NEXT: v_and_b32_e32 v3, 0xffff, v32313; CI-NEXT: v_min_u32_e32 v0, v0, v22314; CI-NEXT: v_min_u32_e32 v2, v8, v92315; CI-NEXT: v_min_u32_e32 v1, v1, v32316; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v22317; CI-NEXT: v_or_b32_e32 v0, v0, v22318; CI-NEXT: flat_store_short v[6:7], v12319; CI-NEXT: flat_store_dword v[4:5], v02320; CI-NEXT: s_endpgm2321;2322; VI-LABEL: v_test_umin_ule_v3i16:2323; VI: ; %bb.0:2324; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02325; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102326; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v02327; VI-NEXT: s_add_i32 s12, s12, s172328; VI-NEXT: s_mov_b32 flat_scratch_lo, s132329; VI-NEXT: s_waitcnt lgkmcnt(0)2330; VI-NEXT: v_mov_b32_e32 v1, s32331; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v42332; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2333; VI-NEXT: v_mov_b32_e32 v3, s52334; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v42335; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82336; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2337; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]2338; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]2339; VI-NEXT: v_mov_b32_e32 v5, s12340; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v42341; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2342; VI-NEXT: v_add_u32_e32 v6, vcc, 4, v42343; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc2344; VI-NEXT: s_waitcnt vmcnt(0)2345; VI-NEXT: v_min_u16_e32 v8, v0, v22346; VI-NEXT: v_min_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12347; VI-NEXT: v_min_u16_e32 v1, v1, v32348; VI-NEXT: v_or_b32_e32 v0, v8, v02349; VI-NEXT: flat_store_short v[6:7], v12350; VI-NEXT: flat_store_dword v[4:5], v02351; VI-NEXT: s_endpgm2352;2353; GFX9-LABEL: v_test_umin_ule_v3i16:2354; GFX9: ; %bb.0:2355; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02356; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102357; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v02358; GFX9-NEXT: s_waitcnt lgkmcnt(0)2359; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]2360; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[4:5]2361; GFX9-NEXT: s_waitcnt vmcnt(0)2362; GFX9-NEXT: v_pk_min_u16 v1, v1, v32363; GFX9-NEXT: v_pk_min_u16 v0, v0, v22364; GFX9-NEXT: global_store_short v4, v1, s[0:1] offset:42365; GFX9-NEXT: global_store_dword v4, v0, s[0:1]2366; GFX9-NEXT: s_endpgm2367;2368; GFX10-LABEL: v_test_umin_ule_v3i16:2369; GFX10: ; %bb.0:2370; GFX10-NEXT: s_clause 0x12371; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02372; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102373; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v02374; GFX10-NEXT: s_waitcnt lgkmcnt(0)2375; GFX10-NEXT: s_clause 0x12376; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]2377; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[4:5]2378; GFX10-NEXT: s_waitcnt vmcnt(0)2379; GFX10-NEXT: v_pk_min_u16 v1, v1, v32380; GFX10-NEXT: v_pk_min_u16 v0, v0, v22381; GFX10-NEXT: global_store_short v4, v1, s[0:1] offset:42382; GFX10-NEXT: global_store_dword v4, v0, s[0:1]2383; GFX10-NEXT: s_endpgm2384;2385; GFX11-LABEL: v_test_umin_ule_v3i16:2386; GFX11: ; %bb.0:2387; GFX11-NEXT: s_clause 0x12388; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x02389; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x102390; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02391; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2392; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v02393; GFX11-NEXT: s_waitcnt lgkmcnt(0)2394; GFX11-NEXT: s_clause 0x12395; GFX11-NEXT: global_load_b64 v[0:1], v4, s[2:3]2396; GFX11-NEXT: global_load_b64 v[2:3], v4, s[4:5]2397; GFX11-NEXT: s_waitcnt vmcnt(0)2398; GFX11-NEXT: v_pk_min_u16 v1, v1, v32399; GFX11-NEXT: v_pk_min_u16 v0, v0, v22400; GFX11-NEXT: s_clause 0x12401; GFX11-NEXT: global_store_b16 v4, v1, s[0:1] offset:42402; GFX11-NEXT: global_store_b32 v4, v0, s[0:1]2403; GFX11-NEXT: s_endpgm2404;2405; GFX1250-LABEL: v_test_umin_ule_v3i16:2406; GFX1250: ; %bb.0:2407; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12408; GFX1250-NEXT: s_clause 0x12409; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x02410; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x102411; GFX1250-NEXT: v_and_b32_e32 v4, 0x3ff, v02412; GFX1250-NEXT: s_wait_kmcnt 0x02413; GFX1250-NEXT: s_clause 0x12414; GFX1250-NEXT: global_load_b64 v[0:1], v4, s[2:3] scale_offset2415; GFX1250-NEXT: global_load_b64 v[2:3], v4, s[6:7] scale_offset2416; GFX1250-NEXT: s_wait_xcnt 0x02417; GFX1250-NEXT: v_lshlrev_b32_e32 v4, 3, v42418; GFX1250-NEXT: s_wait_loadcnt 0x02419; GFX1250-NEXT: v_pk_min_u16 v1, v1, v32420; GFX1250-NEXT: v_pk_min_u16 v0, v0, v22421; GFX1250-NEXT: s_clause 0x12422; GFX1250-NEXT: global_store_b16 v4, v1, s[0:1] offset:42423; GFX1250-NEXT: global_store_b32 v4, v0, s[0:1]2424; GFX1250-NEXT: s_endpgm2425 %tid = call i32 @llvm.amdgcn.workitem.id.x()2426 %a.gep = getelementptr inbounds <3 x i16>, ptr addrspace(1) %a.ptr, i32 %tid2427 %b.gep = getelementptr inbounds <3 x i16>, ptr addrspace(1) %b.ptr, i32 %tid2428 %out.gep = getelementptr inbounds <3 x i16>, ptr addrspace(1) %out, i32 %tid2429 2430 %a = load <3 x i16>, ptr addrspace(1) %a.gep2431 %b = load <3 x i16>, ptr addrspace(1) %b.gep2432 %cmp = icmp ule <3 x i16> %a, %b2433 %val = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b2434 store <3 x i16> %val, ptr addrspace(1) %out.gep2435 ret void2436}2437 2438define amdgpu_kernel void @s_test_umin_ule_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {2439; EG-LABEL: s_test_umin_ule_i32:2440; EG: ; %bb.0:2441; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]2442; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 12443; EG-NEXT: CF_END2444; EG-NEXT: PAD2445; EG-NEXT: ALU clause starting at 4:2446; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,2447; EG-NEXT: MIN_UINT * T1.X, KC0[2].Z, KC0[2].W,2448; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2449;2450; CI-LABEL: s_test_umin_ule_i32:2451; CI: ; %bb.0:2452; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02453; CI-NEXT: s_add_i32 s12, s12, s172454; CI-NEXT: s_mov_b32 flat_scratch_lo, s132455; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82456; CI-NEXT: s_waitcnt lgkmcnt(0)2457; CI-NEXT: s_min_u32 s2, s2, s32458; CI-NEXT: v_mov_b32_e32 v0, s02459; CI-NEXT: v_mov_b32_e32 v1, s12460; CI-NEXT: v_mov_b32_e32 v2, s22461; CI-NEXT: flat_store_dword v[0:1], v22462; CI-NEXT: s_endpgm2463;2464; VI-LABEL: s_test_umin_ule_i32:2465; VI: ; %bb.0:2466; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02467; VI-NEXT: s_add_i32 s12, s12, s172468; VI-NEXT: s_mov_b32 flat_scratch_lo, s132469; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82470; VI-NEXT: s_waitcnt lgkmcnt(0)2471; VI-NEXT: s_min_u32 s2, s2, s32472; VI-NEXT: v_mov_b32_e32 v0, s02473; VI-NEXT: v_mov_b32_e32 v1, s12474; VI-NEXT: v_mov_b32_e32 v2, s22475; VI-NEXT: flat_store_dword v[0:1], v22476; VI-NEXT: s_endpgm2477;2478; GFX9-LABEL: s_test_umin_ule_i32:2479; GFX9: ; %bb.0:2480; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02481; GFX9-NEXT: v_mov_b32_e32 v0, 02482; GFX9-NEXT: s_waitcnt lgkmcnt(0)2483; GFX9-NEXT: s_min_u32 s2, s2, s32484; GFX9-NEXT: v_mov_b32_e32 v1, s22485; GFX9-NEXT: global_store_dword v0, v1, s[0:1]2486; GFX9-NEXT: s_endpgm2487;2488; GFX10-LABEL: s_test_umin_ule_i32:2489; GFX10: ; %bb.0:2490; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02491; GFX10-NEXT: v_mov_b32_e32 v0, 02492; GFX10-NEXT: s_waitcnt lgkmcnt(0)2493; GFX10-NEXT: s_min_u32 s2, s2, s32494; GFX10-NEXT: v_mov_b32_e32 v1, s22495; GFX10-NEXT: global_store_dword v0, v1, s[0:1]2496; GFX10-NEXT: s_endpgm2497;2498; GFX11-LABEL: s_test_umin_ule_i32:2499; GFX11: ; %bb.0:2500; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x02501; GFX11-NEXT: v_mov_b32_e32 v0, 02502; GFX11-NEXT: s_waitcnt lgkmcnt(0)2503; GFX11-NEXT: s_min_u32 s2, s2, s32504; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2505; GFX11-NEXT: v_mov_b32_e32 v1, s22506; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2507; GFX11-NEXT: s_endpgm2508;2509; GFX1250-LABEL: s_test_umin_ule_i32:2510; GFX1250: ; %bb.0:2511; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12512; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x02513; GFX1250-NEXT: v_mov_b32_e32 v0, 02514; GFX1250-NEXT: s_wait_kmcnt 0x02515; GFX1250-NEXT: s_min_u32 s2, s2, s32516; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2517; GFX1250-NEXT: v_mov_b32_e32 v1, s22518; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]2519; GFX1250-NEXT: s_endpgm2520 %cmp = icmp ule i32 %a, %b2521 %val = select i1 %cmp, i32 %a, i32 %b2522 store i32 %val, ptr addrspace(1) %out, align 42523 ret void2524}2525 2526define amdgpu_kernel void @v_test_umin_ult_i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2527; EG-LABEL: v_test_umin_ult_i32:2528; EG: ; %bb.0:2529; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]2530; EG-NEXT: TEX 1 @62531; EG-NEXT: ALU 3, @14, KC0[CB0:0-32], KC1[]2532; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 12533; EG-NEXT: CF_END2534; EG-NEXT: PAD2535; EG-NEXT: Fetch clause starting at 6:2536; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #12537; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #12538; EG-NEXT: ALU clause starting at 10:2539; EG-NEXT: LSHL * T0.W, T0.X, literal.x,2540; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2541; EG-NEXT: ADD_INT T0.X, KC0[2].Z, PV.W,2542; EG-NEXT: ADD_INT * T1.X, KC0[2].W, PV.W,2543; EG-NEXT: ALU clause starting at 14:2544; EG-NEXT: MIN_UINT T0.X, T0.X, T1.X,2545; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,2546; EG-NEXT: LSHR * T1.X, PV.W, literal.x,2547; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2548;2549; CI-LABEL: v_test_umin_ult_i32:2550; CI: ; %bb.0:2551; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02552; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x42553; CI-NEXT: v_lshlrev_b32_e32 v4, 2, v02554; CI-NEXT: s_add_i32 s12, s12, s172555; CI-NEXT: s_mov_b32 flat_scratch_lo, s132556; CI-NEXT: s_waitcnt lgkmcnt(0)2557; CI-NEXT: v_mov_b32_e32 v1, s32558; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v42559; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2560; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82561; CI-NEXT: v_mov_b32_e32 v3, s52562; CI-NEXT: v_add_i32_e32 v2, vcc, s4, v42563; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2564; CI-NEXT: flat_load_dword v5, v[0:1]2565; CI-NEXT: flat_load_dword v2, v[2:3]2566; CI-NEXT: v_mov_b32_e32 v1, s12567; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v42568; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2569; CI-NEXT: s_waitcnt vmcnt(0)2570; CI-NEXT: v_min_u32_e32 v2, v5, v22571; CI-NEXT: flat_store_dword v[0:1], v22572; CI-NEXT: s_endpgm2573;2574; VI-LABEL: v_test_umin_ult_i32:2575; VI: ; %bb.0:2576; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02577; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102578; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v02579; VI-NEXT: s_add_i32 s12, s12, s172580; VI-NEXT: s_mov_b32 flat_scratch_lo, s132581; VI-NEXT: s_waitcnt lgkmcnt(0)2582; VI-NEXT: v_mov_b32_e32 v1, s32583; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v42584; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2585; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82586; VI-NEXT: v_mov_b32_e32 v3, s52587; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v42588; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2589; VI-NEXT: flat_load_dword v5, v[0:1]2590; VI-NEXT: flat_load_dword v2, v[2:3]2591; VI-NEXT: v_mov_b32_e32 v1, s12592; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v42593; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2594; VI-NEXT: s_waitcnt vmcnt(0)2595; VI-NEXT: v_min_u32_e32 v2, v5, v22596; VI-NEXT: flat_store_dword v[0:1], v22597; VI-NEXT: s_endpgm2598;2599; GFX9-LABEL: v_test_umin_ult_i32:2600; GFX9: ; %bb.0:2601; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02602; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102603; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v02604; GFX9-NEXT: s_waitcnt lgkmcnt(0)2605; GFX9-NEXT: global_load_dword v1, v0, s[2:3]2606; GFX9-NEXT: global_load_dword v2, v0, s[4:5]2607; GFX9-NEXT: s_waitcnt vmcnt(0)2608; GFX9-NEXT: v_min_u32_e32 v1, v1, v22609; GFX9-NEXT: global_store_dword v0, v1, s[0:1]2610; GFX9-NEXT: s_endpgm2611;2612; GFX10-LABEL: v_test_umin_ult_i32:2613; GFX10: ; %bb.0:2614; GFX10-NEXT: s_clause 0x12615; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02616; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102617; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v02618; GFX10-NEXT: s_waitcnt lgkmcnt(0)2619; GFX10-NEXT: s_clause 0x12620; GFX10-NEXT: global_load_dword v1, v0, s[2:3]2621; GFX10-NEXT: global_load_dword v2, v0, s[4:5]2622; GFX10-NEXT: s_waitcnt vmcnt(0)2623; GFX10-NEXT: v_min_u32_e32 v1, v1, v22624; GFX10-NEXT: global_store_dword v0, v1, s[0:1]2625; GFX10-NEXT: s_endpgm2626;2627; GFX11-LABEL: v_test_umin_ult_i32:2628; GFX11: ; %bb.0:2629; GFX11-NEXT: s_clause 0x12630; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x02631; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x102632; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v02633; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2634; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v02635; GFX11-NEXT: s_waitcnt lgkmcnt(0)2636; GFX11-NEXT: s_clause 0x12637; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]2638; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]2639; GFX11-NEXT: s_waitcnt vmcnt(0)2640; GFX11-NEXT: v_min_u32_e32 v1, v1, v22641; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2642; GFX11-NEXT: s_endpgm2643;2644; GFX1250-LABEL: v_test_umin_ult_i32:2645; GFX1250: ; %bb.0:2646; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12647; GFX1250-NEXT: s_clause 0x12648; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x02649; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x102650; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v02651; GFX1250-NEXT: s_wait_kmcnt 0x02652; GFX1250-NEXT: s_clause 0x12653; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset2654; GFX1250-NEXT: global_load_b32 v2, v0, s[6:7] scale_offset2655; GFX1250-NEXT: s_wait_loadcnt 0x02656; GFX1250-NEXT: v_min_u32_e32 v1, v1, v22657; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset2658; GFX1250-NEXT: s_endpgm2659 %tid = call i32 @llvm.amdgcn.workitem.id.x()2660 %a.gep = getelementptr inbounds i32, ptr addrspace(1) %a.ptr, i32 %tid2661 %b.gep = getelementptr inbounds i32, ptr addrspace(1) %b.ptr, i32 %tid2662 %out.gep = getelementptr inbounds i32, ptr addrspace(1) %out, i32 %tid2663 %a = load i32, ptr addrspace(1) %a.gep, align 42664 %b = load i32, ptr addrspace(1) %b.gep, align 42665 %cmp = icmp ult i32 %a, %b2666 %val = select i1 %cmp, i32 %a, i32 %b2667 store i32 %val, ptr addrspace(1) %out.gep, align 42668 ret void2669}2670 2671define amdgpu_kernel void @v_test_umin_ult_i8(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {2672; EG-LABEL: v_test_umin_ult_i8:2673; EG: ; %bb.0:2674; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]2675; EG-NEXT: TEX 1 @62676; EG-NEXT: ALU 12, @12, KC0[CB0:0-32], KC1[]2677; EG-NEXT: MEM_RAT MSKOR T1.XW, T0.X2678; EG-NEXT: CF_END2679; EG-NEXT: PAD2680; EG-NEXT: Fetch clause starting at 6:2681; EG-NEXT: VTX_READ_8 T2.X, T2.X, 0, #12682; EG-NEXT: VTX_READ_8 T1.X, T1.X, 0, #12683; EG-NEXT: ALU clause starting at 10:2684; EG-NEXT: ADD_INT T1.X, KC0[2].Z, T0.X,2685; EG-NEXT: ADD_INT * T2.X, KC0[2].W, T0.X,2686; EG-NEXT: ALU clause starting at 12:2687; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.X,2688; EG-NEXT: AND_INT T1.W, PV.W, literal.x,2689; EG-NEXT: MIN_UINT * T2.W, T1.X, T2.X,2690; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2691; EG-NEXT: LSHL * T1.W, PV.W, literal.x,2692; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2693; EG-NEXT: LSHL T1.X, T2.W, PV.W,2694; EG-NEXT: LSHL * T1.W, literal.x, PV.W,2695; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)2696; EG-NEXT: MOV T1.Y, 0.0,2697; EG-NEXT: MOV * T1.Z, 0.0,2698; EG-NEXT: LSHR * T0.X, T0.W, literal.x,2699; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2700;2701; CI-LABEL: v_test_umin_ult_i8:2702; CI: ; %bb.0:2703; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02704; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x42705; CI-NEXT: s_add_i32 s12, s12, s172706; CI-NEXT: s_mov_b32 flat_scratch_lo, s132707; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82708; CI-NEXT: s_waitcnt lgkmcnt(0)2709; CI-NEXT: v_mov_b32_e32 v2, s32710; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v02711; CI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc2712; CI-NEXT: v_mov_b32_e32 v4, s52713; CI-NEXT: v_add_i32_e32 v3, vcc, s4, v02714; CI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc2715; CI-NEXT: flat_load_ubyte v2, v[1:2]2716; CI-NEXT: flat_load_ubyte v3, v[3:4]2717; CI-NEXT: v_mov_b32_e32 v1, s12718; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v02719; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2720; CI-NEXT: s_waitcnt vmcnt(0)2721; CI-NEXT: v_min_u32_e32 v2, v2, v32722; CI-NEXT: flat_store_byte v[0:1], v22723; CI-NEXT: s_endpgm2724;2725; VI-LABEL: v_test_umin_ult_i8:2726; VI: ; %bb.0:2727; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02728; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102729; VI-NEXT: s_add_i32 s12, s12, s172730; VI-NEXT: s_mov_b32 flat_scratch_lo, s132731; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82732; VI-NEXT: s_waitcnt lgkmcnt(0)2733; VI-NEXT: v_mov_b32_e32 v2, s32734; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v02735; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc2736; VI-NEXT: v_mov_b32_e32 v4, s52737; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v02738; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc2739; VI-NEXT: flat_load_ubyte v2, v[1:2]2740; VI-NEXT: flat_load_ubyte v3, v[3:4]2741; VI-NEXT: v_mov_b32_e32 v1, s12742; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v02743; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2744; VI-NEXT: s_waitcnt vmcnt(0)2745; VI-NEXT: v_min_u16_e32 v2, v2, v32746; VI-NEXT: flat_store_byte v[0:1], v22747; VI-NEXT: s_endpgm2748;2749; GFX9-LABEL: v_test_umin_ult_i8:2750; GFX9: ; %bb.0:2751; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02752; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102753; GFX9-NEXT: s_waitcnt lgkmcnt(0)2754; GFX9-NEXT: global_load_ubyte v1, v0, s[2:3]2755; GFX9-NEXT: global_load_ubyte v2, v0, s[4:5]2756; GFX9-NEXT: s_waitcnt vmcnt(0)2757; GFX9-NEXT: v_min_u16_e32 v1, v1, v22758; GFX9-NEXT: global_store_byte v0, v1, s[0:1]2759; GFX9-NEXT: s_endpgm2760;2761; GFX10-LABEL: v_test_umin_ult_i8:2762; GFX10: ; %bb.0:2763; GFX10-NEXT: s_clause 0x12764; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02765; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x102766; GFX10-NEXT: s_waitcnt lgkmcnt(0)2767; GFX10-NEXT: s_clause 0x12768; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3]2769; GFX10-NEXT: global_load_ubyte v2, v0, s[4:5]2770; GFX10-NEXT: s_waitcnt vmcnt(0)2771; GFX10-NEXT: v_min_u16 v1, v1, v22772; GFX10-NEXT: global_store_byte v0, v1, s[0:1]2773; GFX10-NEXT: s_endpgm2774;2775; GFX11-TRUE16-LABEL: v_test_umin_ult_i8:2776; GFX11-TRUE16: ; %bb.0:2777; GFX11-TRUE16-NEXT: s_clause 0x12778; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x02779; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x102780; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x3ff, v02781; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)2782; GFX11-TRUE16-NEXT: s_clause 0x12783; GFX11-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[2:3]2784; GFX11-TRUE16-NEXT: global_load_d16_hi_u8 v0, v1, s[4:5]2785; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)2786; GFX11-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v0.h2787; GFX11-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]2788; GFX11-TRUE16-NEXT: s_endpgm2789;2790; GFX11-FAKE16-LABEL: v_test_umin_ult_i8:2791; GFX11-FAKE16: ; %bb.0:2792; GFX11-FAKE16-NEXT: s_clause 0x12793; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x02794; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x102795; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v02796; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)2797; GFX11-FAKE16-NEXT: s_clause 0x12798; GFX11-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3]2799; GFX11-FAKE16-NEXT: global_load_u8 v2, v0, s[4:5]2800; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)2801; GFX11-FAKE16-NEXT: v_min_u16 v1, v1, v22802; GFX11-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]2803; GFX11-FAKE16-NEXT: s_endpgm2804;2805; GFX1250-TRUE16-LABEL: v_test_umin_ult_i8:2806; GFX1250-TRUE16: ; %bb.0:2807; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12808; GFX1250-TRUE16-NEXT: s_clause 0x12809; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x02810; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x102811; GFX1250-TRUE16-NEXT: v_and_b32_e32 v1, 0x3ff, v02812; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x02813; GFX1250-TRUE16-NEXT: s_clause 0x12814; GFX1250-TRUE16-NEXT: global_load_u8 v0, v1, s[2:3]2815; GFX1250-TRUE16-NEXT: global_load_u8 v2, v1, s[6:7]2816; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x02817; GFX1250-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v2.l2818; GFX1250-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]2819; GFX1250-TRUE16-NEXT: s_endpgm2820;2821; GFX1250-FAKE16-LABEL: v_test_umin_ult_i8:2822; GFX1250-FAKE16: ; %bb.0:2823; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12824; GFX1250-FAKE16-NEXT: s_clause 0x12825; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x02826; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x102827; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v02828; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x02829; GFX1250-FAKE16-NEXT: s_clause 0x12830; GFX1250-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3]2831; GFX1250-FAKE16-NEXT: global_load_u8 v2, v0, s[6:7]2832; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x02833; GFX1250-FAKE16-NEXT: v_min_u16 v1, v1, v22834; GFX1250-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1]2835; GFX1250-FAKE16-NEXT: s_endpgm2836 %tid = call i32 @llvm.amdgcn.workitem.id.x()2837 %a.gep = getelementptr inbounds i8, ptr addrspace(1) %a.ptr, i32 %tid2838 %b.gep = getelementptr inbounds i8, ptr addrspace(1) %b.ptr, i32 %tid2839 %out.gep = getelementptr inbounds i8, ptr addrspace(1) %out, i32 %tid2840 2841 %a = load i8, ptr addrspace(1) %a.gep, align 12842 %b = load i8, ptr addrspace(1) %b.gep, align 12843 %cmp = icmp ult i8 %a, %b2844 %val = select i1 %cmp, i8 %a, i8 %b2845 store i8 %val, ptr addrspace(1) %out.gep, align 12846 ret void2847}2848 2849define amdgpu_kernel void @s_test_umin_ult_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {2850; EG-LABEL: s_test_umin_ult_i32:2851; EG: ; %bb.0:2852; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]2853; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 12854; EG-NEXT: CF_END2855; EG-NEXT: PAD2856; EG-NEXT: ALU clause starting at 4:2857; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,2858; EG-NEXT: MIN_UINT * T1.X, KC0[2].Z, KC0[2].W,2859; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2860;2861; CI-LABEL: s_test_umin_ult_i32:2862; CI: ; %bb.0:2863; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02864; CI-NEXT: s_add_i32 s12, s12, s172865; CI-NEXT: s_mov_b32 flat_scratch_lo, s132866; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82867; CI-NEXT: s_waitcnt lgkmcnt(0)2868; CI-NEXT: s_min_u32 s2, s2, s32869; CI-NEXT: v_mov_b32_e32 v0, s02870; CI-NEXT: v_mov_b32_e32 v1, s12871; CI-NEXT: v_mov_b32_e32 v2, s22872; CI-NEXT: flat_store_dword v[0:1], v22873; CI-NEXT: s_endpgm2874;2875; VI-LABEL: s_test_umin_ult_i32:2876; VI: ; %bb.0:2877; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02878; VI-NEXT: s_add_i32 s12, s12, s172879; VI-NEXT: s_mov_b32 flat_scratch_lo, s132880; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82881; VI-NEXT: s_waitcnt lgkmcnt(0)2882; VI-NEXT: s_min_u32 s2, s2, s32883; VI-NEXT: v_mov_b32_e32 v0, s02884; VI-NEXT: v_mov_b32_e32 v1, s12885; VI-NEXT: v_mov_b32_e32 v2, s22886; VI-NEXT: flat_store_dword v[0:1], v22887; VI-NEXT: s_endpgm2888;2889; GFX9-LABEL: s_test_umin_ult_i32:2890; GFX9: ; %bb.0:2891; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02892; GFX9-NEXT: v_mov_b32_e32 v0, 02893; GFX9-NEXT: s_waitcnt lgkmcnt(0)2894; GFX9-NEXT: s_min_u32 s2, s2, s32895; GFX9-NEXT: v_mov_b32_e32 v1, s22896; GFX9-NEXT: global_store_dword v0, v1, s[0:1]2897; GFX9-NEXT: s_endpgm2898;2899; GFX10-LABEL: s_test_umin_ult_i32:2900; GFX10: ; %bb.0:2901; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x02902; GFX10-NEXT: v_mov_b32_e32 v0, 02903; GFX10-NEXT: s_waitcnt lgkmcnt(0)2904; GFX10-NEXT: s_min_u32 s2, s2, s32905; GFX10-NEXT: v_mov_b32_e32 v1, s22906; GFX10-NEXT: global_store_dword v0, v1, s[0:1]2907; GFX10-NEXT: s_endpgm2908;2909; GFX11-LABEL: s_test_umin_ult_i32:2910; GFX11: ; %bb.0:2911; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x02912; GFX11-NEXT: v_mov_b32_e32 v0, 02913; GFX11-NEXT: s_waitcnt lgkmcnt(0)2914; GFX11-NEXT: s_min_u32 s2, s2, s32915; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2916; GFX11-NEXT: v_mov_b32_e32 v1, s22917; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]2918; GFX11-NEXT: s_endpgm2919;2920; GFX1250-LABEL: s_test_umin_ult_i32:2921; GFX1250: ; %bb.0:2922; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 12923; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x02924; GFX1250-NEXT: v_mov_b32_e32 v0, 02925; GFX1250-NEXT: s_wait_kmcnt 0x02926; GFX1250-NEXT: s_min_u32 s2, s2, s32927; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2928; GFX1250-NEXT: v_mov_b32_e32 v1, s22929; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]2930; GFX1250-NEXT: s_endpgm2931 %cmp = icmp ult i32 %a, %b2932 %val = select i1 %cmp, i32 %a, i32 %b2933 store i32 %val, ptr addrspace(1) %out, align 42934 ret void2935}2936 2937define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) #0 {2938; EG-LABEL: v_test_umin_ult_i32_multi_use:2939; EG: ; %bb.0:2940; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]2941; EG-NEXT: TEX 1 @62942; EG-NEXT: ALU 16, @12, KC0[CB0:0-32], KC1[]2943; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 02944; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X2945; EG-NEXT: CF_END2946; EG-NEXT: Fetch clause starting at 6:2947; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #12948; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #12949; EG-NEXT: ALU clause starting at 10:2950; EG-NEXT: MOV T0.X, KC0[2].W,2951; EG-NEXT: MOV * T1.X, KC0[3].X,2952; EG-NEXT: ALU clause starting at 12:2953; EG-NEXT: AND_INT T0.W, KC0[2].Z, literal.x,2954; EG-NEXT: SETGT_UINT * T1.W, T1.X, T0.X,2955; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2956; EG-NEXT: AND_INT T1.W, PS, 1,2957; EG-NEXT: LSHL * T0.W, PV.W, literal.x,2958; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)2959; EG-NEXT: LSHL T2.X, PV.W, PS,2960; EG-NEXT: LSHL * T2.W, literal.x, PS,2961; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)2962; EG-NEXT: MOV T2.Y, 0.0,2963; EG-NEXT: MOV * T2.Z, 0.0,2964; EG-NEXT: LSHR T3.X, KC0[2].Z, literal.x,2965; EG-NEXT: SETGE_UINT * T0.W, T0.X, T1.X,2966; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2967; EG-NEXT: CNDE_INT T0.X, PV.W, T0.X, T1.X,2968; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,2969; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)2970;2971; CI-LABEL: v_test_umin_ult_i32_multi_use:2972; CI: ; %bb.0:2973; CI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x02974; CI-NEXT: s_add_i32 s12, s12, s172975; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 82976; CI-NEXT: s_mov_b32 flat_scratch_lo, s132977; CI-NEXT: s_waitcnt lgkmcnt(0)2978; CI-NEXT: s_load_dword s4, s[4:5], 0x02979; CI-NEXT: s_load_dword s5, s[6:7], 0x02980; CI-NEXT: v_mov_b32_e32 v0, s02981; CI-NEXT: v_mov_b32_e32 v1, s12982; CI-NEXT: v_mov_b32_e32 v2, s22983; CI-NEXT: v_mov_b32_e32 v3, s32984; CI-NEXT: s_waitcnt lgkmcnt(0)2985; CI-NEXT: s_cmp_lt_u32 s4, s52986; CI-NEXT: s_cselect_b64 s[0:1], -1, 02987; CI-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]2988; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec2989; CI-NEXT: s_cselect_b32 s0, s4, s52990; CI-NEXT: v_mov_b32_e32 v5, s02991; CI-NEXT: flat_store_dword v[0:1], v52992; CI-NEXT: flat_store_byte v[2:3], v42993; CI-NEXT: s_endpgm2994;2995; VI-LABEL: v_test_umin_ult_i32_multi_use:2996; VI: ; %bb.0:2997; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x02998; VI-NEXT: s_add_i32 s12, s12, s172999; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83000; VI-NEXT: s_mov_b32 flat_scratch_lo, s133001; VI-NEXT: s_waitcnt lgkmcnt(0)3002; VI-NEXT: s_load_dword s4, s[4:5], 0x03003; VI-NEXT: s_load_dword s5, s[6:7], 0x03004; VI-NEXT: v_mov_b32_e32 v0, s03005; VI-NEXT: v_mov_b32_e32 v1, s13006; VI-NEXT: v_mov_b32_e32 v2, s23007; VI-NEXT: v_mov_b32_e32 v3, s33008; VI-NEXT: s_waitcnt lgkmcnt(0)3009; VI-NEXT: s_cmp_lt_u32 s4, s53010; VI-NEXT: s_cselect_b64 s[0:1], -1, 03011; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]3012; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec3013; VI-NEXT: s_cselect_b32 s0, s4, s53014; VI-NEXT: v_mov_b32_e32 v5, s03015; VI-NEXT: flat_store_dword v[0:1], v53016; VI-NEXT: flat_store_byte v[2:3], v43017; VI-NEXT: s_endpgm3018;3019; GFX9-LABEL: v_test_umin_ult_i32_multi_use:3020; GFX9: ; %bb.0:3021; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x03022; GFX9-NEXT: v_mov_b32_e32 v0, 03023; GFX9-NEXT: s_waitcnt lgkmcnt(0)3024; GFX9-NEXT: s_load_dword s8, s[4:5], 0x03025; GFX9-NEXT: s_load_dword s9, s[6:7], 0x03026; GFX9-NEXT: s_waitcnt lgkmcnt(0)3027; GFX9-NEXT: s_cmp_lt_u32 s8, s93028; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 03029; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]3030; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec3031; GFX9-NEXT: s_cselect_b32 s4, s8, s93032; GFX9-NEXT: v_mov_b32_e32 v2, s43033; GFX9-NEXT: global_store_dword v0, v2, s[0:1]3034; GFX9-NEXT: global_store_byte v0, v1, s[2:3]3035; GFX9-NEXT: s_endpgm3036;3037; GFX10-LABEL: v_test_umin_ult_i32_multi_use:3038; GFX10: ; %bb.0:3039; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x03040; GFX10-NEXT: v_mov_b32_e32 v1, 03041; GFX10-NEXT: s_waitcnt lgkmcnt(0)3042; GFX10-NEXT: s_load_dword s8, s[4:5], 0x03043; GFX10-NEXT: s_load_dword s9, s[6:7], 0x03044; GFX10-NEXT: s_waitcnt lgkmcnt(0)3045; GFX10-NEXT: s_cmp_lt_u32 s8, s93046; GFX10-NEXT: s_cselect_b32 s4, -1, 03047; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s43048; GFX10-NEXT: s_and_b32 s4, s4, exec_lo3049; GFX10-NEXT: s_cselect_b32 s4, s8, s93050; GFX10-NEXT: v_mov_b32_e32 v2, s43051; GFX10-NEXT: global_store_dword v1, v2, s[0:1]3052; GFX10-NEXT: global_store_byte v1, v0, s[2:3]3053; GFX10-NEXT: s_endpgm3054;3055; GFX11-LABEL: v_test_umin_ult_i32_multi_use:3056; GFX11: ; %bb.0:3057; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x03058; GFX11-NEXT: v_mov_b32_e32 v1, 03059; GFX11-NEXT: s_waitcnt lgkmcnt(0)3060; GFX11-NEXT: s_load_b32 s4, s[4:5], 0x03061; GFX11-NEXT: s_load_b32 s5, s[6:7], 0x03062; GFX11-NEXT: s_waitcnt lgkmcnt(0)3063; GFX11-NEXT: s_cmp_lt_u32 s4, s53064; GFX11-NEXT: s_cselect_b32 s6, -1, 03065; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)3066; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s63067; GFX11-NEXT: s_and_b32 s6, s6, exec_lo3068; GFX11-NEXT: s_cselect_b32 s4, s4, s53069; GFX11-NEXT: v_mov_b32_e32 v2, s43070; GFX11-NEXT: s_clause 0x13071; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]3072; GFX11-NEXT: global_store_b8 v1, v0, s[2:3]3073; GFX11-NEXT: s_endpgm3074;3075; GFX1250-LABEL: v_test_umin_ult_i32_multi_use:3076; GFX1250: ; %bb.0:3077; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13078; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x03079; GFX1250-NEXT: v_mov_b32_e32 v1, 03080; GFX1250-NEXT: s_wait_kmcnt 0x03081; GFX1250-NEXT: s_load_b32 s0, s[12:13], 0x03082; GFX1250-NEXT: s_load_b32 s1, s[14:15], 0x03083; GFX1250-NEXT: s_wait_kmcnt 0x03084; GFX1250-NEXT: s_cmp_lt_u32 s0, s13085; GFX1250-NEXT: s_cselect_b32 s2, -1, 03086; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)3087; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, s23088; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo3089; GFX1250-NEXT: s_cselect_b32 s0, s0, s13090; GFX1250-NEXT: v_mov_b32_e32 v2, s03091; GFX1250-NEXT: s_clause 0x13092; GFX1250-NEXT: global_store_b32 v1, v2, s[8:9]3093; GFX1250-NEXT: global_store_b8 v1, v0, s[10:11]3094; GFX1250-NEXT: s_endpgm3095 %a = load i32, ptr addrspace(1) %aptr, align 43096 %b = load i32, ptr addrspace(1) %bptr, align 43097 %cmp = icmp ult i32 %a, %b3098 %val = select i1 %cmp, i32 %a, i32 %b3099 store i32 %val, ptr addrspace(1) %out0, align 43100 store i1 %cmp, ptr addrspace(1) %out13101 ret void3102}3103 3104define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0, ptr addrspace(1) %out1, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) #0 {3105; EG-LABEL: v_test_umin_ult_i16_multi_use:3106; EG: ; %bb.0:3107; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]3108; EG-NEXT: TEX 1 @63109; EG-NEXT: ALU 24, @12, KC0[CB0:0-32], KC1[]3110; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X3111; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X3112; EG-NEXT: CF_END3113; EG-NEXT: Fetch clause starting at 6:3114; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #13115; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #13116; EG-NEXT: ALU clause starting at 10:3117; EG-NEXT: MOV T0.X, KC0[2].W,3118; EG-NEXT: MOV * T1.X, KC0[3].X,3119; EG-NEXT: ALU clause starting at 12:3120; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,3121; EG-NEXT: SETGE_UINT * T1.W, T0.X, T1.X,3122; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)3123; EG-NEXT: CNDE_INT T1.W, PS, T0.X, T1.X,3124; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3125; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)3126; EG-NEXT: LSHL T2.X, PV.W, PS,3127; EG-NEXT: LSHL * T2.W, literal.x, PS,3128; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3129; EG-NEXT: MOV T2.Y, 0.0,3130; EG-NEXT: AND_INT T0.W, KC0[2].Z, literal.x,3131; EG-NEXT: SETGT_UINT * T1.W, T1.X, T0.X,3132; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)3133; EG-NEXT: AND_INT T1.W, PS, 1,3134; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3135; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)3136; EG-NEXT: LSHL T0.X, PV.W, PS,3137; EG-NEXT: LSHL * T0.W, literal.x, PS,3138; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)3139; EG-NEXT: MOV T0.Y, 0.0,3140; EG-NEXT: MOV T2.Z, 0.0,3141; EG-NEXT: MOV * T0.Z, 0.0,3142; EG-NEXT: LSHR T1.X, KC0[2].Z, literal.x,3143; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,3144; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3145;3146; CI-LABEL: v_test_umin_ult_i16_multi_use:3147; CI: ; %bb.0:3148; CI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x03149; CI-NEXT: s_add_i32 s12, s12, s173150; CI-NEXT: s_mov_b32 flat_scratch_lo, s133151; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83152; CI-NEXT: s_waitcnt lgkmcnt(0)3153; CI-NEXT: v_mov_b32_e32 v0, s43154; CI-NEXT: v_mov_b32_e32 v1, s53155; CI-NEXT: v_mov_b32_e32 v2, s63156; CI-NEXT: v_mov_b32_e32 v3, s73157; CI-NEXT: flat_load_ushort v4, v[0:1]3158; CI-NEXT: flat_load_ushort v5, v[2:3]3159; CI-NEXT: v_mov_b32_e32 v0, s03160; CI-NEXT: v_mov_b32_e32 v1, s13161; CI-NEXT: v_mov_b32_e32 v2, s23162; CI-NEXT: v_mov_b32_e32 v3, s33163; CI-NEXT: s_waitcnt vmcnt(0)3164; CI-NEXT: v_cmp_lt_u32_e32 vcc, v4, v53165; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc3166; CI-NEXT: flat_store_short v[0:1], v43167; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc3168; CI-NEXT: flat_store_byte v[2:3], v03169; CI-NEXT: s_endpgm3170;3171; VI-LABEL: v_test_umin_ult_i16_multi_use:3172; VI: ; %bb.0:3173; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x03174; VI-NEXT: s_add_i32 s12, s12, s173175; VI-NEXT: s_mov_b32 flat_scratch_lo, s133176; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83177; VI-NEXT: s_waitcnt lgkmcnt(0)3178; VI-NEXT: v_mov_b32_e32 v2, s63179; VI-NEXT: v_mov_b32_e32 v3, s73180; VI-NEXT: v_mov_b32_e32 v0, s43181; VI-NEXT: v_mov_b32_e32 v1, s53182; VI-NEXT: flat_load_ushort v4, v[2:3]3183; VI-NEXT: flat_load_ushort v5, v[0:1]3184; VI-NEXT: v_mov_b32_e32 v0, s03185; VI-NEXT: v_mov_b32_e32 v1, s13186; VI-NEXT: v_mov_b32_e32 v2, s23187; VI-NEXT: v_mov_b32_e32 v3, s33188; VI-NEXT: s_waitcnt vmcnt(1)3189; VI-NEXT: v_and_b32_e32 v6, 0xffff, v43190; VI-NEXT: s_waitcnt vmcnt(0)3191; VI-NEXT: v_and_b32_e32 v7, 0xffff, v53192; VI-NEXT: v_cmp_lt_u32_e32 vcc, v7, v63193; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc3194; VI-NEXT: flat_store_short v[0:1], v43195; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc3196; VI-NEXT: flat_store_byte v[2:3], v03197; VI-NEXT: s_endpgm3198;3199; GFX9-LABEL: v_test_umin_ult_i16_multi_use:3200; GFX9: ; %bb.0:3201; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x03202; GFX9-NEXT: v_mov_b32_e32 v0, 03203; GFX9-NEXT: s_waitcnt lgkmcnt(0)3204; GFX9-NEXT: global_load_ushort v1, v0, s[4:5]3205; GFX9-NEXT: global_load_ushort v2, v0, s[6:7]3206; GFX9-NEXT: s_waitcnt vmcnt(0)3207; GFX9-NEXT: v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:WORD_03208; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc3209; GFX9-NEXT: global_store_short v0, v1, s[0:1]3210; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc3211; GFX9-NEXT: global_store_byte v0, v1, s[2:3]3212; GFX9-NEXT: s_endpgm3213;3214; GFX10-LABEL: v_test_umin_ult_i16_multi_use:3215; GFX10: ; %bb.0:3216; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x03217; GFX10-NEXT: v_mov_b32_e32 v0, 03218; GFX10-NEXT: s_waitcnt lgkmcnt(0)3219; GFX10-NEXT: s_clause 0x13220; GFX10-NEXT: global_load_ushort v1, v0, s[4:5]3221; GFX10-NEXT: global_load_ushort v2, v0, s[6:7]3222; GFX10-NEXT: s_waitcnt vmcnt(0)3223; GFX10-NEXT: v_cmp_lt_u32_sdwa vcc_lo, v1, v2 src0_sel:WORD_0 src1_sel:WORD_03224; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo3225; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo3226; GFX10-NEXT: global_store_short v0, v1, s[0:1]3227; GFX10-NEXT: global_store_byte v0, v2, s[2:3]3228; GFX10-NEXT: s_endpgm3229;3230; GFX11-TRUE16-LABEL: v_test_umin_ult_i16_multi_use:3231; GFX11-TRUE16: ; %bb.0:3232; GFX11-TRUE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x03233; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 03234; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)3235; GFX11-TRUE16-NEXT: s_clause 0x13236; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[6:7]3237; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v0, s[4:5]3238; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)3239; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v13240; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)3241; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v23242; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3243; GFX11-TRUE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v33244; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo3245; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo3246; GFX11-TRUE16-NEXT: s_clause 0x13247; GFX11-TRUE16-NEXT: global_store_b16 v0, v1, s[0:1]3248; GFX11-TRUE16-NEXT: global_store_b8 v0, v2, s[2:3]3249; GFX11-TRUE16-NEXT: s_endpgm3250;3251; GFX11-FAKE16-LABEL: v_test_umin_ult_i16_multi_use:3252; GFX11-FAKE16: ; %bb.0:3253; GFX11-FAKE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x03254; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 03255; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)3256; GFX11-FAKE16-NEXT: s_clause 0x13257; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[6:7]3258; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5]3259; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)3260; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v13261; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)3262; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v23263; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)3264; GFX11-FAKE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v33265; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo3266; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo3267; GFX11-FAKE16-NEXT: s_clause 0x13268; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]3269; GFX11-FAKE16-NEXT: global_store_b8 v0, v2, s[2:3]3270; GFX11-FAKE16-NEXT: s_endpgm3271;3272; GFX1250-LABEL: v_test_umin_ult_i16_multi_use:3273; GFX1250: ; %bb.0:3274; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13275; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x03276; GFX1250-NEXT: v_mov_b32_e32 v0, 03277; GFX1250-NEXT: s_wait_kmcnt 0x03278; GFX1250-NEXT: s_clause 0x13279; GFX1250-NEXT: global_load_u16 v1, v0, s[14:15]3280; GFX1250-NEXT: global_load_u16 v2, v0, s[12:13]3281; GFX1250-NEXT: s_wait_loadcnt 0x13282; GFX1250-NEXT: v_and_b32_e32 v3, 0xffff, v13283; GFX1250-NEXT: s_wait_loadcnt 0x03284; GFX1250-NEXT: v_and_b32_e32 v4, 0xffff, v23285; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)3286; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v33287; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo3288; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo3289; GFX1250-NEXT: s_clause 0x13290; GFX1250-NEXT: global_store_b16 v0, v1, s[8:9]3291; GFX1250-NEXT: global_store_b8 v0, v2, s[10:11]3292; GFX1250-NEXT: s_endpgm3293 %a = load i16, ptr addrspace(1) %aptr, align 23294 %b = load i16, ptr addrspace(1) %bptr, align 23295 %cmp = icmp ult i16 %a, %b3296 %val = select i1 %cmp, i16 %a, i16 %b3297 store i16 %val, ptr addrspace(1) %out0, align 23298 store i1 %cmp, ptr addrspace(1) %out13299 ret void3300}3301 3302define amdgpu_kernel void @s_test_umin_ult_v1i32(ptr addrspace(1) %out, <1 x i32> %a, <1 x i32> %b) #0 {3303; EG-LABEL: s_test_umin_ult_v1i32:3304; EG: ; %bb.0:3305; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]3306; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 13307; EG-NEXT: CF_END3308; EG-NEXT: PAD3309; EG-NEXT: ALU clause starting at 4:3310; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,3311; EG-NEXT: MIN_UINT * T1.X, KC0[2].Z, KC0[2].W,3312; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3313;3314; CI-LABEL: s_test_umin_ult_v1i32:3315; CI: ; %bb.0:3316; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x03317; CI-NEXT: s_add_i32 s12, s12, s173318; CI-NEXT: s_mov_b32 flat_scratch_lo, s133319; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83320; CI-NEXT: s_waitcnt lgkmcnt(0)3321; CI-NEXT: s_min_u32 s2, s2, s33322; CI-NEXT: v_mov_b32_e32 v0, s03323; CI-NEXT: v_mov_b32_e32 v1, s13324; CI-NEXT: v_mov_b32_e32 v2, s23325; CI-NEXT: flat_store_dword v[0:1], v23326; CI-NEXT: s_endpgm3327;3328; VI-LABEL: s_test_umin_ult_v1i32:3329; VI: ; %bb.0:3330; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x03331; VI-NEXT: s_add_i32 s12, s12, s173332; VI-NEXT: s_mov_b32 flat_scratch_lo, s133333; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83334; VI-NEXT: s_waitcnt lgkmcnt(0)3335; VI-NEXT: s_min_u32 s2, s2, s33336; VI-NEXT: v_mov_b32_e32 v0, s03337; VI-NEXT: v_mov_b32_e32 v1, s13338; VI-NEXT: v_mov_b32_e32 v2, s23339; VI-NEXT: flat_store_dword v[0:1], v23340; VI-NEXT: s_endpgm3341;3342; GFX9-LABEL: s_test_umin_ult_v1i32:3343; GFX9: ; %bb.0:3344; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x03345; GFX9-NEXT: v_mov_b32_e32 v0, 03346; GFX9-NEXT: s_waitcnt lgkmcnt(0)3347; GFX9-NEXT: s_min_u32 s2, s2, s33348; GFX9-NEXT: v_mov_b32_e32 v1, s23349; GFX9-NEXT: global_store_dword v0, v1, s[0:1]3350; GFX9-NEXT: s_endpgm3351;3352; GFX10-LABEL: s_test_umin_ult_v1i32:3353; GFX10: ; %bb.0:3354; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x03355; GFX10-NEXT: v_mov_b32_e32 v0, 03356; GFX10-NEXT: s_waitcnt lgkmcnt(0)3357; GFX10-NEXT: s_min_u32 s2, s2, s33358; GFX10-NEXT: v_mov_b32_e32 v1, s23359; GFX10-NEXT: global_store_dword v0, v1, s[0:1]3360; GFX10-NEXT: s_endpgm3361;3362; GFX11-LABEL: s_test_umin_ult_v1i32:3363; GFX11: ; %bb.0:3364; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x03365; GFX11-NEXT: v_mov_b32_e32 v0, 03366; GFX11-NEXT: s_waitcnt lgkmcnt(0)3367; GFX11-NEXT: s_min_u32 s2, s2, s33368; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3369; GFX11-NEXT: v_mov_b32_e32 v1, s23370; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]3371; GFX11-NEXT: s_endpgm3372;3373; GFX1250-LABEL: s_test_umin_ult_v1i32:3374; GFX1250: ; %bb.0:3375; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13376; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x03377; GFX1250-NEXT: v_mov_b32_e32 v0, 03378; GFX1250-NEXT: s_wait_kmcnt 0x03379; GFX1250-NEXT: s_min_u32 s2, s2, s33380; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3381; GFX1250-NEXT: v_mov_b32_e32 v1, s23382; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]3383; GFX1250-NEXT: s_endpgm3384 %cmp = icmp ult <1 x i32> %a, %b3385 %val = select <1 x i1> %cmp, <1 x i32> %a, <1 x i32> %b3386 store <1 x i32> %val, ptr addrspace(1) %out3387 ret void3388}3389 3390define amdgpu_kernel void @s_test_umin_ult_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x i32> %b) #0 {3391; EG-LABEL: s_test_umin_ult_v8i32:3392; EG: ; %bb.0:3393; EG-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]3394; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 03395; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 13396; EG-NEXT: CF_END3397; EG-NEXT: ALU clause starting at 4:3398; EG-NEXT: MIN_UINT * T0.W, KC0[5].X, KC0[7].X,3399; EG-NEXT: MIN_UINT * T0.Z, KC0[4].W, KC0[6].W,3400; EG-NEXT: MIN_UINT * T0.Y, KC0[4].Z, KC0[6].Z,3401; EG-NEXT: MIN_UINT * T0.X, KC0[4].Y, KC0[6].Y,3402; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,3403; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3404; EG-NEXT: MIN_UINT * T2.W, KC0[6].X, KC0[8].X,3405; EG-NEXT: MIN_UINT * T2.Z, KC0[5].W, KC0[7].W,3406; EG-NEXT: MIN_UINT * T2.Y, KC0[5].Z, KC0[7].Z,3407; EG-NEXT: MIN_UINT * T2.X, KC0[5].Y, KC0[7].Y,3408; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,3409; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3410; EG-NEXT: LSHR * T3.X, PV.W, literal.x,3411; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3412;3413; CI-LABEL: s_test_umin_ult_v8i32:3414; CI: ; %bb.0:3415; CI-NEXT: s_add_i32 s12, s12, s173416; CI-NEXT: s_mov_b32 flat_scratch_lo, s133417; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83418; CI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x83419; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03420; CI-NEXT: s_waitcnt lgkmcnt(0)3421; CI-NEXT: s_min_u32 s4, s15, s233422; CI-NEXT: s_min_u32 s5, s14, s223423; CI-NEXT: s_min_u32 s6, s13, s213424; CI-NEXT: s_min_u32 s7, s12, s203425; CI-NEXT: s_min_u32 s2, s19, s273426; CI-NEXT: s_min_u32 s3, s18, s263427; CI-NEXT: s_min_u32 s8, s17, s253428; CI-NEXT: s_min_u32 s9, s16, s243429; CI-NEXT: v_mov_b32_e32 v3, s23430; CI-NEXT: s_add_u32 s2, s0, 163431; CI-NEXT: v_mov_b32_e32 v2, s33432; CI-NEXT: s_addc_u32 s3, s1, 03433; CI-NEXT: v_mov_b32_e32 v5, s33434; CI-NEXT: v_mov_b32_e32 v0, s93435; CI-NEXT: v_mov_b32_e32 v1, s83436; CI-NEXT: v_mov_b32_e32 v4, s23437; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3438; CI-NEXT: v_mov_b32_e32 v5, s13439; CI-NEXT: v_mov_b32_e32 v0, s73440; CI-NEXT: v_mov_b32_e32 v1, s63441; CI-NEXT: v_mov_b32_e32 v2, s53442; CI-NEXT: v_mov_b32_e32 v3, s43443; CI-NEXT: v_mov_b32_e32 v4, s03444; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3445; CI-NEXT: s_endpgm3446;3447; VI-LABEL: s_test_umin_ult_v8i32:3448; VI: ; %bb.0:3449; VI-NEXT: s_add_i32 s12, s12, s173450; VI-NEXT: s_mov_b32 flat_scratch_lo, s133451; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83452; VI-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x203453; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03454; VI-NEXT: s_waitcnt lgkmcnt(0)3455; VI-NEXT: s_min_u32 s4, s15, s233456; VI-NEXT: s_min_u32 s5, s14, s223457; VI-NEXT: s_min_u32 s6, s13, s213458; VI-NEXT: s_min_u32 s7, s12, s203459; VI-NEXT: s_min_u32 s2, s19, s273460; VI-NEXT: s_min_u32 s3, s18, s263461; VI-NEXT: s_min_u32 s8, s17, s253462; VI-NEXT: s_min_u32 s9, s16, s243463; VI-NEXT: v_mov_b32_e32 v3, s23464; VI-NEXT: s_add_u32 s2, s0, 163465; VI-NEXT: v_mov_b32_e32 v2, s33466; VI-NEXT: s_addc_u32 s3, s1, 03467; VI-NEXT: v_mov_b32_e32 v5, s33468; VI-NEXT: v_mov_b32_e32 v0, s93469; VI-NEXT: v_mov_b32_e32 v1, s83470; VI-NEXT: v_mov_b32_e32 v4, s23471; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3472; VI-NEXT: v_mov_b32_e32 v5, s13473; VI-NEXT: v_mov_b32_e32 v0, s73474; VI-NEXT: v_mov_b32_e32 v1, s63475; VI-NEXT: v_mov_b32_e32 v2, s53476; VI-NEXT: v_mov_b32_e32 v3, s43477; VI-NEXT: v_mov_b32_e32 v4, s03478; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3479; VI-NEXT: s_endpgm3480;3481; GFX9-LABEL: s_test_umin_ult_v8i32:3482; GFX9: ; %bb.0:3483; GFX9-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x203484; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03485; GFX9-NEXT: v_mov_b32_e32 v4, 03486; GFX9-NEXT: s_waitcnt lgkmcnt(0)3487; GFX9-NEXT: s_min_u32 s6, s19, s273488; GFX9-NEXT: s_min_u32 s7, s18, s263489; GFX9-NEXT: s_min_u32 s8, s17, s253490; GFX9-NEXT: s_min_u32 s9, s16, s243491; GFX9-NEXT: s_min_u32 s2, s15, s233492; GFX9-NEXT: s_min_u32 s3, s14, s223493; GFX9-NEXT: s_min_u32 s4, s13, s213494; GFX9-NEXT: s_min_u32 s5, s12, s203495; GFX9-NEXT: v_mov_b32_e32 v0, s93496; GFX9-NEXT: v_mov_b32_e32 v1, s83497; GFX9-NEXT: v_mov_b32_e32 v2, s73498; GFX9-NEXT: v_mov_b32_e32 v3, s63499; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:163500; GFX9-NEXT: s_nop 03501; GFX9-NEXT: v_mov_b32_e32 v0, s53502; GFX9-NEXT: v_mov_b32_e32 v1, s43503; GFX9-NEXT: v_mov_b32_e32 v2, s33504; GFX9-NEXT: v_mov_b32_e32 v3, s23505; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]3506; GFX9-NEXT: s_endpgm3507;3508; GFX10-LABEL: s_test_umin_ult_v8i32:3509; GFX10: ; %bb.0:3510; GFX10-NEXT: s_clause 0x13511; GFX10-NEXT: s_load_dwordx16 s[12:27], s[8:9], 0x203512; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03513; GFX10-NEXT: v_mov_b32_e32 v8, 03514; GFX10-NEXT: s_waitcnt lgkmcnt(0)3515; GFX10-NEXT: s_min_u32 s6, s19, s273516; GFX10-NEXT: s_min_u32 s7, s18, s263517; GFX10-NEXT: s_min_u32 s8, s16, s243518; GFX10-NEXT: s_min_u32 s9, s17, s253519; GFX10-NEXT: s_min_u32 s2, s15, s233520; GFX10-NEXT: s_min_u32 s3, s14, s223521; GFX10-NEXT: s_min_u32 s4, s13, s213522; GFX10-NEXT: s_min_u32 s5, s12, s203523; GFX10-NEXT: v_mov_b32_e32 v0, s83524; GFX10-NEXT: v_mov_b32_e32 v1, s93525; GFX10-NEXT: v_mov_b32_e32 v2, s73526; GFX10-NEXT: v_mov_b32_e32 v3, s63527; GFX10-NEXT: v_mov_b32_e32 v4, s53528; GFX10-NEXT: v_mov_b32_e32 v5, s43529; GFX10-NEXT: v_mov_b32_e32 v6, s33530; GFX10-NEXT: v_mov_b32_e32 v7, s23531; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:163532; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]3533; GFX10-NEXT: s_endpgm3534;3535; GFX11-LABEL: s_test_umin_ult_v8i32:3536; GFX11: ; %bb.0:3537; GFX11-NEXT: s_clause 0x13538; GFX11-NEXT: s_load_b512 s[8:23], s[4:5], 0x203539; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x03540; GFX11-NEXT: v_mov_b32_e32 v8, 03541; GFX11-NEXT: s_waitcnt lgkmcnt(0)3542; GFX11-NEXT: s_min_u32 s4, s9, s173543; GFX11-NEXT: s_min_u32 s5, s8, s163544; GFX11-NEXT: s_min_u32 s6, s15, s233545; GFX11-NEXT: s_min_u32 s7, s14, s223546; GFX11-NEXT: s_min_u32 s8, s12, s203547; GFX11-NEXT: s_min_u32 s9, s13, s213548; GFX11-NEXT: s_min_u32 s2, s11, s193549; GFX11-NEXT: s_min_u32 s3, s10, s183550; GFX11-NEXT: v_mov_b32_e32 v0, s83551; GFX11-NEXT: v_mov_b32_e32 v1, s93552; GFX11-NEXT: v_mov_b32_e32 v2, s73553; GFX11-NEXT: v_mov_b32_e32 v3, s63554; GFX11-NEXT: v_mov_b32_e32 v4, s53555; GFX11-NEXT: v_mov_b32_e32 v5, s43556; GFX11-NEXT: v_mov_b32_e32 v6, s33557; GFX11-NEXT: v_mov_b32_e32 v7, s23558; GFX11-NEXT: s_clause 0x13559; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:163560; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1]3561; GFX11-NEXT: s_endpgm3562;3563; GFX1250-LABEL: s_test_umin_ult_v8i32:3564; GFX1250: ; %bb.0:3565; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13566; GFX1250-NEXT: s_clause 0x13567; GFX1250-NEXT: s_load_b512 s[8:23], s[4:5], 0x203568; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x03569; GFX1250-NEXT: v_mov_b32_e32 v8, 03570; GFX1250-NEXT: s_wait_kmcnt 0x03571; GFX1250-NEXT: s_min_u32 s4, s9, s173572; GFX1250-NEXT: s_min_u32 s5, s8, s163573; GFX1250-NEXT: s_min_u32 s6, s15, s233574; GFX1250-NEXT: s_min_u32 s7, s14, s223575; GFX1250-NEXT: s_min_u32 s8, s12, s203576; GFX1250-NEXT: s_min_u32 s9, s13, s213577; GFX1250-NEXT: s_min_u32 s2, s11, s193578; GFX1250-NEXT: s_min_u32 s3, s10, s183579; GFX1250-NEXT: v_mov_b32_e32 v0, s83580; GFX1250-NEXT: v_mov_b32_e32 v1, s93581; GFX1250-NEXT: v_mov_b32_e32 v2, s73582; GFX1250-NEXT: v_mov_b32_e32 v3, s63583; GFX1250-NEXT: v_mov_b32_e32 v4, s53584; GFX1250-NEXT: v_mov_b32_e32 v5, s43585; GFX1250-NEXT: v_mov_b32_e32 v6, s33586; GFX1250-NEXT: v_mov_b32_e32 v7, s23587; GFX1250-NEXT: s_clause 0x13588; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:163589; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[0:1]3590; GFX1250-NEXT: s_endpgm3591 %cmp = icmp ult <8 x i32> %a, %b3592 %val = select <8 x i1> %cmp, <8 x i32> %a, <8 x i32> %b3593 store <8 x i32> %val, ptr addrspace(1) %out3594 ret void3595}3596 3597define amdgpu_kernel void @s_test_umin_ult_v8i16(ptr addrspace(1) %out, <8 x i16> %a, <8 x i16> %b) #0 {3598; EG-LABEL: s_test_umin_ult_v8i16:3599; EG: ; %bb.0:3600; EG-NEXT: ALU 1, @52, KC0[], KC1[]3601; EG-NEXT: TEX 1 @203602; EG-NEXT: ALU 9, @54, KC0[], KC1[]3603; EG-NEXT: TEX 1 @243604; EG-NEXT: ALU 8, @64, KC0[], KC1[]3605; EG-NEXT: TEX 1 @283606; EG-NEXT: ALU 10, @73, KC0[], KC1[]3607; EG-NEXT: TEX 1 @323608; EG-NEXT: ALU 8, @84, KC0[], KC1[]3609; EG-NEXT: TEX 1 @363610; EG-NEXT: ALU 10, @93, KC0[], KC1[]3611; EG-NEXT: TEX 1 @403612; EG-NEXT: ALU 8, @104, KC0[], KC1[]3613; EG-NEXT: TEX 1 @443614; EG-NEXT: ALU 10, @113, KC0[], KC1[]3615; EG-NEXT: TEX 1 @483616; EG-NEXT: ALU 10, @124, KC0[CB0:0-32], KC1[]3617; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 13618; EG-NEXT: CF_END3619; EG-NEXT: PAD3620; EG-NEXT: Fetch clause starting at 20:3621; EG-NEXT: VTX_READ_16 T8.X, T7.X, 66, #33622; EG-NEXT: VTX_READ_16 T9.X, T7.X, 82, #33623; EG-NEXT: Fetch clause starting at 24:3624; EG-NEXT: VTX_READ_16 T8.X, T7.X, 64, #33625; EG-NEXT: VTX_READ_16 T9.X, T7.X, 80, #33626; EG-NEXT: Fetch clause starting at 28:3627; EG-NEXT: VTX_READ_16 T8.X, T7.X, 62, #33628; EG-NEXT: VTX_READ_16 T9.X, T7.X, 78, #33629; EG-NEXT: Fetch clause starting at 32:3630; EG-NEXT: VTX_READ_16 T8.X, T7.X, 60, #33631; EG-NEXT: VTX_READ_16 T9.X, T7.X, 76, #33632; EG-NEXT: Fetch clause starting at 36:3633; EG-NEXT: VTX_READ_16 T8.X, T7.X, 58, #33634; EG-NEXT: VTX_READ_16 T9.X, T7.X, 74, #33635; EG-NEXT: Fetch clause starting at 40:3636; EG-NEXT: VTX_READ_16 T8.X, T7.X, 56, #33637; EG-NEXT: VTX_READ_16 T9.X, T7.X, 72, #33638; EG-NEXT: Fetch clause starting at 44:3639; EG-NEXT: VTX_READ_16 T8.X, T7.X, 54, #33640; EG-NEXT: VTX_READ_16 T9.X, T7.X, 70, #33641; EG-NEXT: Fetch clause starting at 48:3642; EG-NEXT: VTX_READ_16 T8.X, T7.X, 52, #33643; EG-NEXT: VTX_READ_16 T7.X, T7.X, 68, #33644; EG-NEXT: ALU clause starting at 52:3645; EG-NEXT: MOV * T0.Y, T3.X,3646; EG-NEXT: MOV * T7.X, 0.0,3647; EG-NEXT: ALU clause starting at 54:3648; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3649; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3650; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3651; EG-NEXT: MIN_UINT * T0.W, PV.W, PS,3652; EG-NEXT: LSHL T0.W, PV.W, literal.x,3653; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,3654; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)3655; EG-NEXT: OR_INT * T0.W, PS, PV.W,3656; EG-NEXT: MOV * T3.X, PV.W,3657; EG-NEXT: MOV * T0.Y, PV.X,3658; EG-NEXT: ALU clause starting at 64:3659; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3660; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3661; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3662; EG-NEXT: AND_INT T2.W, T0.Y, literal.x,3663; EG-NEXT: MIN_UINT * T0.W, PV.W, PS,3664; EG-NEXT: -65536(nan), 0(0.000000e+00)3665; EG-NEXT: OR_INT * T0.W, PV.W, PS,3666; EG-NEXT: MOV T3.X, PV.W,3667; EG-NEXT: MOV * T0.Y, T2.X,3668; EG-NEXT: ALU clause starting at 73:3669; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3670; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3671; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3672; EG-NEXT: MIN_UINT T0.W, PV.W, PS,3673; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,3674; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3675; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3676; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3677; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3678; EG-NEXT: MOV * T2.X, PV.W,3679; EG-NEXT: MOV * T0.Y, PV.X,3680; EG-NEXT: ALU clause starting at 84:3681; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3682; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3683; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3684; EG-NEXT: AND_INT T2.W, T0.Y, literal.x,3685; EG-NEXT: MIN_UINT * T0.W, PV.W, PS,3686; EG-NEXT: -65536(nan), 0(0.000000e+00)3687; EG-NEXT: OR_INT * T7.Z, PV.W, PS,3688; EG-NEXT: MOV T2.X, PV.Z,3689; EG-NEXT: MOV * T0.Y, T5.X,3690; EG-NEXT: ALU clause starting at 93:3691; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3692; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3693; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3694; EG-NEXT: MIN_UINT T0.W, PV.W, PS,3695; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,3696; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3697; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3698; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3699; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3700; EG-NEXT: MOV * T5.X, PV.W,3701; EG-NEXT: MOV * T0.Y, PV.X,3702; EG-NEXT: ALU clause starting at 104:3703; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3704; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3705; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3706; EG-NEXT: AND_INT T2.W, T0.Y, literal.x,3707; EG-NEXT: MIN_UINT * T0.W, PV.W, PS,3708; EG-NEXT: -65536(nan), 0(0.000000e+00)3709; EG-NEXT: OR_INT * T0.W, PV.W, PS,3710; EG-NEXT: MOV T5.X, PV.W,3711; EG-NEXT: MOV * T0.Y, T4.X,3712; EG-NEXT: ALU clause starting at 113:3713; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3714; EG-NEXT: AND_INT * T1.W, T9.X, literal.x,3715; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3716; EG-NEXT: MIN_UINT T0.W, PV.W, PS,3717; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,3718; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3719; EG-NEXT: LSHL * T0.W, PV.W, literal.x,3720; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3721; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,3722; EG-NEXT: MOV * T4.X, PV.W,3723; EG-NEXT: MOV * T0.Y, PV.X,3724; EG-NEXT: ALU clause starting at 124:3725; EG-NEXT: AND_INT T0.W, T8.X, literal.x,3726; EG-NEXT: AND_INT * T1.W, T7.X, literal.x,3727; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)3728; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x,3729; EG-NEXT: AND_INT T2.W, T0.Y, literal.y,3730; EG-NEXT: MIN_UINT * T0.W, PV.W, PS,3731; EG-NEXT: 2(2.802597e-45), -65536(nan)3732; EG-NEXT: OR_INT * T7.X, PV.W, PS,3733; EG-NEXT: MOV T4.X, PV.X,3734; EG-NEXT: MOV * T7.W, T3.X,3735; EG-NEXT: MOV * T7.Y, T5.X,3736;3737; CI-LABEL: s_test_umin_ult_v8i16:3738; CI: ; %bb.0:3739; CI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x43740; CI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x03741; CI-NEXT: s_add_i32 s12, s12, s173742; CI-NEXT: s_mov_b32 flat_scratch_lo, s133743; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83744; CI-NEXT: s_waitcnt lgkmcnt(0)3745; CI-NEXT: s_lshr_b32 s10, s0, 163746; CI-NEXT: s_and_b32 s0, s0, 0xffff3747; CI-NEXT: s_lshr_b32 s11, s1, 163748; CI-NEXT: s_and_b32 s1, s1, 0xffff3749; CI-NEXT: s_lshr_b32 s12, s2, 163750; CI-NEXT: s_and_b32 s2, s2, 0xffff3751; CI-NEXT: s_lshr_b32 s13, s3, 163752; CI-NEXT: s_and_b32 s3, s3, 0xffff3753; CI-NEXT: s_lshr_b32 s14, s4, 163754; CI-NEXT: s_and_b32 s4, s4, 0xffff3755; CI-NEXT: s_lshr_b32 s15, s5, 163756; CI-NEXT: s_and_b32 s5, s5, 0xffff3757; CI-NEXT: s_lshr_b32 s16, s6, 163758; CI-NEXT: s_and_b32 s6, s6, 0xffff3759; CI-NEXT: s_lshr_b32 s17, s7, 163760; CI-NEXT: s_and_b32 s7, s7, 0xffff3761; CI-NEXT: s_min_u32 s3, s3, s73762; CI-NEXT: s_min_u32 s7, s13, s173763; CI-NEXT: s_min_u32 s2, s2, s63764; CI-NEXT: s_min_u32 s6, s12, s163765; CI-NEXT: s_min_u32 s1, s1, s53766; CI-NEXT: s_min_u32 s5, s11, s153767; CI-NEXT: s_min_u32 s0, s0, s43768; CI-NEXT: s_min_u32 s4, s10, s143769; CI-NEXT: s_lshl_b32 s7, s7, 163770; CI-NEXT: s_lshl_b32 s6, s6, 163771; CI-NEXT: s_lshl_b32 s5, s5, 163772; CI-NEXT: s_lshl_b32 s4, s4, 163773; CI-NEXT: s_or_b32 s3, s3, s73774; CI-NEXT: s_or_b32 s2, s2, s63775; CI-NEXT: s_or_b32 s1, s1, s53776; CI-NEXT: s_or_b32 s0, s0, s43777; CI-NEXT: v_mov_b32_e32 v4, s83778; CI-NEXT: v_mov_b32_e32 v0, s03779; CI-NEXT: v_mov_b32_e32 v1, s13780; CI-NEXT: v_mov_b32_e32 v2, s23781; CI-NEXT: v_mov_b32_e32 v3, s33782; CI-NEXT: v_mov_b32_e32 v5, s93783; CI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3784; CI-NEXT: s_endpgm3785;3786; VI-LABEL: s_test_umin_ult_v8i16:3787; VI: ; %bb.0:3788; VI-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x103789; VI-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x03790; VI-NEXT: s_add_i32 s12, s12, s173791; VI-NEXT: s_mov_b32 flat_scratch_lo, s133792; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83793; VI-NEXT: s_waitcnt lgkmcnt(0)3794; VI-NEXT: s_and_b32 s10, s7, 0xffff3795; VI-NEXT: s_and_b32 s11, s3, 0xffff3796; VI-NEXT: s_lshr_b32 s7, s7, 163797; VI-NEXT: s_lshr_b32 s3, s3, 163798; VI-NEXT: s_min_u32 s3, s3, s73799; VI-NEXT: s_min_u32 s10, s11, s103800; VI-NEXT: s_lshl_b32 s3, s3, 163801; VI-NEXT: s_or_b32 s3, s10, s33802; VI-NEXT: s_and_b32 s7, s6, 0xffff3803; VI-NEXT: s_and_b32 s10, s2, 0xffff3804; VI-NEXT: s_lshr_b32 s6, s6, 163805; VI-NEXT: s_lshr_b32 s2, s2, 163806; VI-NEXT: s_min_u32 s2, s2, s63807; VI-NEXT: s_min_u32 s7, s10, s73808; VI-NEXT: s_lshl_b32 s2, s2, 163809; VI-NEXT: s_or_b32 s2, s7, s23810; VI-NEXT: s_and_b32 s6, s5, 0xffff3811; VI-NEXT: s_and_b32 s7, s1, 0xffff3812; VI-NEXT: s_lshr_b32 s5, s5, 163813; VI-NEXT: s_lshr_b32 s1, s1, 163814; VI-NEXT: s_min_u32 s1, s1, s53815; VI-NEXT: s_min_u32 s6, s7, s63816; VI-NEXT: s_lshl_b32 s1, s1, 163817; VI-NEXT: s_or_b32 s1, s6, s13818; VI-NEXT: s_and_b32 s5, s4, 0xffff3819; VI-NEXT: s_and_b32 s6, s0, 0xffff3820; VI-NEXT: s_lshr_b32 s4, s4, 163821; VI-NEXT: s_lshr_b32 s0, s0, 163822; VI-NEXT: s_min_u32 s0, s0, s43823; VI-NEXT: s_min_u32 s5, s6, s53824; VI-NEXT: s_lshl_b32 s0, s0, 163825; VI-NEXT: s_or_b32 s0, s5, s03826; VI-NEXT: v_mov_b32_e32 v4, s83827; VI-NEXT: v_mov_b32_e32 v0, s03828; VI-NEXT: v_mov_b32_e32 v1, s13829; VI-NEXT: v_mov_b32_e32 v2, s23830; VI-NEXT: v_mov_b32_e32 v3, s33831; VI-NEXT: v_mov_b32_e32 v5, s93832; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]3833; VI-NEXT: s_endpgm3834;3835; GFX9-LABEL: s_test_umin_ult_v8i16:3836; GFX9: ; %bb.0:3837; GFX9-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x103838; GFX9-NEXT: v_mov_b32_e32 v4, 03839; GFX9-NEXT: s_load_dwordx2 s[8:9], s[8:9], 0x03840; GFX9-NEXT: s_waitcnt lgkmcnt(0)3841; GFX9-NEXT: v_mov_b32_e32 v0, s73842; GFX9-NEXT: v_mov_b32_e32 v1, s63843; GFX9-NEXT: v_pk_min_u16 v3, s3, v03844; GFX9-NEXT: v_mov_b32_e32 v0, s53845; GFX9-NEXT: v_pk_min_u16 v2, s2, v13846; GFX9-NEXT: v_pk_min_u16 v1, s1, v03847; GFX9-NEXT: v_mov_b32_e32 v0, s43848; GFX9-NEXT: v_pk_min_u16 v0, s0, v03849; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]3850; GFX9-NEXT: s_endpgm3851;3852; GFX10-LABEL: s_test_umin_ult_v8i16:3853; GFX10: ; %bb.0:3854; GFX10-NEXT: s_clause 0x13855; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x103856; GFX10-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x03857; GFX10-NEXT: v_mov_b32_e32 v4, 03858; GFX10-NEXT: s_waitcnt lgkmcnt(0)3859; GFX10-NEXT: v_pk_min_u16 v3, s3, s73860; GFX10-NEXT: v_pk_min_u16 v2, s2, s63861; GFX10-NEXT: v_pk_min_u16 v1, s1, s53862; GFX10-NEXT: v_pk_min_u16 v0, s0, s43863; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11]3864; GFX10-NEXT: s_endpgm3865;3866; GFX11-LABEL: s_test_umin_ult_v8i16:3867; GFX11: ; %bb.0:3868; GFX11-NEXT: s_clause 0x13869; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x103870; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x03871; GFX11-NEXT: v_mov_b32_e32 v4, 03872; GFX11-NEXT: s_waitcnt lgkmcnt(0)3873; GFX11-NEXT: v_pk_min_u16 v3, s11, s153874; GFX11-NEXT: v_pk_min_u16 v2, s10, s143875; GFX11-NEXT: v_pk_min_u16 v1, s9, s133876; GFX11-NEXT: v_pk_min_u16 v0, s8, s123877; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]3878; GFX11-NEXT: s_endpgm3879;3880; GFX1250-LABEL: s_test_umin_ult_v8i16:3881; GFX1250: ; %bb.0:3882; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 13883; GFX1250-NEXT: s_clause 0x13884; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x103885; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x03886; GFX1250-NEXT: v_mov_b32_e32 v4, 03887; GFX1250-NEXT: s_wait_kmcnt 0x03888; GFX1250-NEXT: v_pk_min_u16 v3, s11, s153889; GFX1250-NEXT: v_pk_min_u16 v2, s10, s143890; GFX1250-NEXT: v_pk_min_u16 v1, s9, s133891; GFX1250-NEXT: v_pk_min_u16 v0, s8, s123892; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[0:1]3893; GFX1250-NEXT: s_endpgm3894 %cmp = icmp ult <8 x i16> %a, %b3895 %val = select <8 x i1> %cmp, <8 x i16> %a, <8 x i16> %b3896 store <8 x i16> %val, ptr addrspace(1) %out3897 ret void3898}3899 3900; Make sure redundant and removed3901 3902define amdgpu_kernel void @simplify_demanded_bits_test_umin_ult_i16(ptr addrspace(1) %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) #0 {3903; EG-LABEL: simplify_demanded_bits_test_umin_ult_i16:3904; EG: ; %bb.0:3905; EG-NEXT: ALU 0, @10, KC0[], KC1[]3906; EG-NEXT: TEX 1 @63907; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]3908; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 13909; EG-NEXT: CF_END3910; EG-NEXT: PAD3911; EG-NEXT: Fetch clause starting at 6:3912; EG-NEXT: VTX_READ_16 T1.X, T0.X, 72, #33913; EG-NEXT: VTX_READ_16 T0.X, T0.X, 108, #33914; EG-NEXT: ALU clause starting at 10:3915; EG-NEXT: MOV * T0.X, 0.0,3916; EG-NEXT: ALU clause starting at 11:3917; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,3918; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_2123919; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)3920; EG-NEXT: MIN_UINT T0.X, PV.Z, PV.W,3921; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,3922; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)3923;3924; CI-LABEL: simplify_demanded_bits_test_umin_ult_i16:3925; CI: ; %bb.0:3926; CI-NEXT: s_load_dword s2, s[8:9], 0xa3927; CI-NEXT: s_load_dword s3, s[8:9], 0x133928; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03929; CI-NEXT: s_add_i32 s12, s12, s173930; CI-NEXT: s_mov_b32 flat_scratch_lo, s133931; CI-NEXT: s_waitcnt lgkmcnt(0)3932; CI-NEXT: s_and_b32 s2, s2, 0xffff3933; CI-NEXT: s_and_b32 s3, s3, 0xffff3934; CI-NEXT: s_min_u32 s2, s2, s33935; CI-NEXT: v_mov_b32_e32 v0, s03936; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83937; CI-NEXT: v_mov_b32_e32 v1, s13938; CI-NEXT: v_mov_b32_e32 v2, s23939; CI-NEXT: flat_store_dword v[0:1], v23940; CI-NEXT: s_endpgm3941;3942; VI-LABEL: simplify_demanded_bits_test_umin_ult_i16:3943; VI: ; %bb.0:3944; VI-NEXT: s_load_dword s2, s[8:9], 0x283945; VI-NEXT: s_load_dword s3, s[8:9], 0x4c3946; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03947; VI-NEXT: s_add_i32 s12, s12, s173948; VI-NEXT: s_mov_b32 flat_scratch_lo, s133949; VI-NEXT: s_waitcnt lgkmcnt(0)3950; VI-NEXT: s_and_b32 s2, s2, 0xffff3951; VI-NEXT: s_and_b32 s3, s3, 0xffff3952; VI-NEXT: s_min_u32 s2, s2, s33953; VI-NEXT: v_mov_b32_e32 v0, s03954; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 83955; VI-NEXT: v_mov_b32_e32 v1, s13956; VI-NEXT: v_mov_b32_e32 v2, s23957; VI-NEXT: flat_store_dword v[0:1], v23958; VI-NEXT: s_endpgm3959;3960; GFX9-LABEL: simplify_demanded_bits_test_umin_ult_i16:3961; GFX9: ; %bb.0:3962; GFX9-NEXT: s_load_dword s2, s[8:9], 0x283963; GFX9-NEXT: s_load_dword s3, s[8:9], 0x4c3964; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03965; GFX9-NEXT: v_mov_b32_e32 v0, 03966; GFX9-NEXT: s_waitcnt lgkmcnt(0)3967; GFX9-NEXT: s_and_b32 s2, s2, 0xffff3968; GFX9-NEXT: s_and_b32 s3, s3, 0xffff3969; GFX9-NEXT: s_min_u32 s2, s2, s33970; GFX9-NEXT: v_mov_b32_e32 v1, s23971; GFX9-NEXT: global_store_dword v0, v1, s[0:1]3972; GFX9-NEXT: s_endpgm3973;3974; GFX10-LABEL: simplify_demanded_bits_test_umin_ult_i16:3975; GFX10: ; %bb.0:3976; GFX10-NEXT: s_clause 0x23977; GFX10-NEXT: s_load_dword s2, s[8:9], 0x283978; GFX10-NEXT: s_load_dword s3, s[8:9], 0x4c3979; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x03980; GFX10-NEXT: v_mov_b32_e32 v0, 03981; GFX10-NEXT: s_waitcnt lgkmcnt(0)3982; GFX10-NEXT: s_and_b32 s2, s2, 0xffff3983; GFX10-NEXT: s_and_b32 s3, s3, 0xffff3984; GFX10-NEXT: s_min_u32 s2, s2, s33985; GFX10-NEXT: v_mov_b32_e32 v1, s23986; GFX10-NEXT: global_store_dword v0, v1, s[0:1]3987; GFX10-NEXT: s_endpgm3988;3989; GFX11-LABEL: simplify_demanded_bits_test_umin_ult_i16:3990; GFX11: ; %bb.0:3991; GFX11-NEXT: s_clause 0x23992; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x283993; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x4c3994; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x03995; GFX11-NEXT: v_mov_b32_e32 v0, 03996; GFX11-NEXT: s_waitcnt lgkmcnt(0)3997; GFX11-NEXT: s_and_b32 s2, s2, 0xffff3998; GFX11-NEXT: s_and_b32 s3, s3, 0xffff3999; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4000; GFX11-NEXT: s_min_u32 s2, s2, s34001; GFX11-NEXT: v_mov_b32_e32 v1, s24002; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]4003; GFX11-NEXT: s_endpgm4004;4005; GFX1250-LABEL: simplify_demanded_bits_test_umin_ult_i16:4006; GFX1250: ; %bb.0:4007; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14008; GFX1250-NEXT: s_clause 0x24009; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x284010; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x4c4011; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x04012; GFX1250-NEXT: v_mov_b32_e32 v0, 04013; GFX1250-NEXT: s_wait_kmcnt 0x04014; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff4015; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff4016; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4017; GFX1250-NEXT: s_min_u32 s2, s2, s34018; GFX1250-NEXT: v_mov_b32_e32 v1, s24019; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]4020; GFX1250-NEXT: s_endpgm4021 %a.ext = zext i16 %a to i324022 %b.ext = zext i16 %b to i324023 %cmp = icmp ult i32 %a.ext, %b.ext4024 %val = select i1 %cmp, i32 %a.ext, i32 %b.ext4025 %mask = and i32 %val, 655354026 store i32 %mask, ptr addrspace(1) %out4027 ret void4028}4029 4030; Make sure redundant sign_extend_inreg removed.4031 4032define amdgpu_kernel void @simplify_demanded_bits_test_min_slt_i16(ptr addrspace(1) %out, [8 x i32], i16 signext %a, [8 x i32], i16 signext %b) #0 {4033; EG-LABEL: simplify_demanded_bits_test_min_slt_i16:4034; EG: ; %bb.0:4035; EG-NEXT: ALU 0, @10, KC0[], KC1[]4036; EG-NEXT: TEX 1 @64037; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]4038; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 14039; EG-NEXT: CF_END4040; EG-NEXT: PAD4041; EG-NEXT: Fetch clause starting at 6:4042; EG-NEXT: VTX_READ_16 T1.X, T0.X, 72, #34043; EG-NEXT: VTX_READ_16 T0.X, T0.X, 108, #34044; EG-NEXT: ALU clause starting at 10:4045; EG-NEXT: MOV * T0.X, 0.0,4046; EG-NEXT: ALU clause starting at 11:4047; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,4048; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_2124049; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4050; EG-NEXT: MIN_INT T0.X, PV.Z, PV.W,4051; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4052; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4053;4054; CI-LABEL: simplify_demanded_bits_test_min_slt_i16:4055; CI: ; %bb.0:4056; CI-NEXT: s_load_dword s2, s[8:9], 0xa4057; CI-NEXT: s_load_dword s3, s[8:9], 0x134058; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04059; CI-NEXT: s_add_i32 s12, s12, s174060; CI-NEXT: s_mov_b32 flat_scratch_lo, s134061; CI-NEXT: s_waitcnt lgkmcnt(0)4062; CI-NEXT: s_sext_i32_i16 s2, s24063; CI-NEXT: s_sext_i32_i16 s3, s34064; CI-NEXT: s_min_i32 s2, s2, s34065; CI-NEXT: v_mov_b32_e32 v0, s04066; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84067; CI-NEXT: v_mov_b32_e32 v1, s14068; CI-NEXT: v_mov_b32_e32 v2, s24069; CI-NEXT: flat_store_dword v[0:1], v24070; CI-NEXT: s_endpgm4071;4072; VI-LABEL: simplify_demanded_bits_test_min_slt_i16:4073; VI: ; %bb.0:4074; VI-NEXT: s_load_dword s2, s[8:9], 0x284075; VI-NEXT: s_load_dword s3, s[8:9], 0x4c4076; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04077; VI-NEXT: s_add_i32 s12, s12, s174078; VI-NEXT: s_mov_b32 flat_scratch_lo, s134079; VI-NEXT: s_waitcnt lgkmcnt(0)4080; VI-NEXT: s_sext_i32_i16 s2, s24081; VI-NEXT: s_sext_i32_i16 s3, s34082; VI-NEXT: s_min_i32 s2, s2, s34083; VI-NEXT: v_mov_b32_e32 v0, s04084; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84085; VI-NEXT: v_mov_b32_e32 v1, s14086; VI-NEXT: v_mov_b32_e32 v2, s24087; VI-NEXT: flat_store_dword v[0:1], v24088; VI-NEXT: s_endpgm4089;4090; GFX9-LABEL: simplify_demanded_bits_test_min_slt_i16:4091; GFX9: ; %bb.0:4092; GFX9-NEXT: s_load_dword s2, s[8:9], 0x284093; GFX9-NEXT: s_load_dword s3, s[8:9], 0x4c4094; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04095; GFX9-NEXT: v_mov_b32_e32 v0, 04096; GFX9-NEXT: s_waitcnt lgkmcnt(0)4097; GFX9-NEXT: s_sext_i32_i16 s2, s24098; GFX9-NEXT: s_sext_i32_i16 s3, s34099; GFX9-NEXT: s_min_i32 s2, s2, s34100; GFX9-NEXT: v_mov_b32_e32 v1, s24101; GFX9-NEXT: global_store_dword v0, v1, s[0:1]4102; GFX9-NEXT: s_endpgm4103;4104; GFX10-LABEL: simplify_demanded_bits_test_min_slt_i16:4105; GFX10: ; %bb.0:4106; GFX10-NEXT: s_clause 0x24107; GFX10-NEXT: s_load_dword s2, s[8:9], 0x284108; GFX10-NEXT: s_load_dword s3, s[8:9], 0x4c4109; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04110; GFX10-NEXT: v_mov_b32_e32 v0, 04111; GFX10-NEXT: s_waitcnt lgkmcnt(0)4112; GFX10-NEXT: s_sext_i32_i16 s2, s24113; GFX10-NEXT: s_sext_i32_i16 s3, s34114; GFX10-NEXT: s_min_i32 s2, s2, s34115; GFX10-NEXT: v_mov_b32_e32 v1, s24116; GFX10-NEXT: global_store_dword v0, v1, s[0:1]4117; GFX10-NEXT: s_endpgm4118;4119; GFX11-LABEL: simplify_demanded_bits_test_min_slt_i16:4120; GFX11: ; %bb.0:4121; GFX11-NEXT: s_clause 0x24122; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x284123; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x4c4124; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x04125; GFX11-NEXT: v_mov_b32_e32 v0, 04126; GFX11-NEXT: s_waitcnt lgkmcnt(0)4127; GFX11-NEXT: s_sext_i32_i16 s2, s24128; GFX11-NEXT: s_sext_i32_i16 s3, s34129; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4130; GFX11-NEXT: s_min_i32 s2, s2, s34131; GFX11-NEXT: v_mov_b32_e32 v1, s24132; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]4133; GFX11-NEXT: s_endpgm4134;4135; GFX1250-LABEL: simplify_demanded_bits_test_min_slt_i16:4136; GFX1250: ; %bb.0:4137; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14138; GFX1250-NEXT: s_clause 0x24139; GFX1250-NEXT: s_load_b32 s2, s[4:5], 0x284140; GFX1250-NEXT: s_load_b32 s3, s[4:5], 0x4c4141; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x04142; GFX1250-NEXT: v_mov_b32_e32 v0, 04143; GFX1250-NEXT: s_wait_kmcnt 0x04144; GFX1250-NEXT: s_sext_i32_i16 s2, s24145; GFX1250-NEXT: s_sext_i32_i16 s3, s34146; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4147; GFX1250-NEXT: s_min_i32 s2, s2, s34148; GFX1250-NEXT: v_mov_b32_e32 v1, s24149; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]4150; GFX1250-NEXT: s_endpgm4151 %a.ext = sext i16 %a to i324152 %b.ext = sext i16 %b to i324153 %cmp = icmp slt i32 %a.ext, %b.ext4154 %val = select i1 %cmp, i32 %a.ext, i32 %b.ext4155 %shl = shl i32 %val, 164156 %sextinreg = ashr i32 %shl, 164157 store i32 %sextinreg, ptr addrspace(1) %out4158 ret void4159}4160 4161define amdgpu_kernel void @s_test_imin_sle_i16(ptr addrspace(1) %out, i16 %a, i16 %b) #0 {4162; EG-LABEL: s_test_imin_sle_i16:4163; EG: ; %bb.0:4164; EG-NEXT: ALU 0, @10, KC0[], KC1[]4165; EG-NEXT: TEX 1 @64166; EG-NEXT: ALU 14, @11, KC0[CB0:0-32], KC1[]4167; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X4168; EG-NEXT: CF_END4169; EG-NEXT: PAD4170; EG-NEXT: Fetch clause starting at 6:4171; EG-NEXT: VTX_READ_16 T1.X, T0.X, 40, #34172; EG-NEXT: VTX_READ_16 T0.X, T0.X, 42, #34173; EG-NEXT: ALU clause starting at 10:4174; EG-NEXT: MOV * T0.X, 0.0,4175; EG-NEXT: ALU clause starting at 11:4176; EG-NEXT: BFE_INT T0.Z, T1.X, 0.0, literal.x,4177; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_2124178; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,4179; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45)4180; EG-NEXT: MIN_INT * T0.W, PV.Z, PV.W,4181; EG-NEXT: AND_INT T0.W, PV.W, literal.x,4182; EG-NEXT: LSHL * T1.W, T1.W, literal.y,4183; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)4184; EG-NEXT: LSHL T0.X, PV.W, PS,4185; EG-NEXT: LSHL * T0.W, literal.x, PS,4186; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)4187; EG-NEXT: MOV T0.Y, 0.0,4188; EG-NEXT: MOV * T0.Z, 0.0,4189; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4190; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4191;4192; CI-LABEL: s_test_imin_sle_i16:4193; CI: ; %bb.0:4194; CI-NEXT: s_load_dword s2, s[8:9], 0x24195; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04196; CI-NEXT: s_add_i32 s12, s12, s174197; CI-NEXT: s_mov_b32 flat_scratch_lo, s134198; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84199; CI-NEXT: s_waitcnt lgkmcnt(0)4200; CI-NEXT: s_sext_i32_i16 s3, s24201; CI-NEXT: s_ashr_i32 s2, s2, 164202; CI-NEXT: s_min_i32 s2, s3, s24203; CI-NEXT: v_mov_b32_e32 v0, s04204; CI-NEXT: v_mov_b32_e32 v1, s14205; CI-NEXT: v_mov_b32_e32 v2, s24206; CI-NEXT: flat_store_short v[0:1], v24207; CI-NEXT: s_endpgm4208;4209; VI-LABEL: s_test_imin_sle_i16:4210; VI: ; %bb.0:4211; VI-NEXT: s_load_dword s2, s[8:9], 0x84212; VI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04213; VI-NEXT: s_add_i32 s12, s12, s174214; VI-NEXT: s_mov_b32 flat_scratch_lo, s134215; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84216; VI-NEXT: s_waitcnt lgkmcnt(0)4217; VI-NEXT: s_ashr_i32 s3, s2, 164218; VI-NEXT: s_sext_i32_i16 s2, s24219; VI-NEXT: s_min_i32 s2, s2, s34220; VI-NEXT: v_mov_b32_e32 v0, s04221; VI-NEXT: v_mov_b32_e32 v1, s14222; VI-NEXT: v_mov_b32_e32 v2, s24223; VI-NEXT: flat_store_short v[0:1], v24224; VI-NEXT: s_endpgm4225;4226; GFX9-LABEL: s_test_imin_sle_i16:4227; GFX9: ; %bb.0:4228; GFX9-NEXT: s_load_dword s2, s[8:9], 0x84229; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04230; GFX9-NEXT: v_mov_b32_e32 v0, 04231; GFX9-NEXT: s_waitcnt lgkmcnt(0)4232; GFX9-NEXT: s_ashr_i32 s3, s2, 164233; GFX9-NEXT: s_sext_i32_i16 s2, s24234; GFX9-NEXT: s_min_i32 s2, s2, s34235; GFX9-NEXT: v_mov_b32_e32 v1, s24236; GFX9-NEXT: global_store_short v0, v1, s[0:1]4237; GFX9-NEXT: s_endpgm4238;4239; GFX10-LABEL: s_test_imin_sle_i16:4240; GFX10: ; %bb.0:4241; GFX10-NEXT: s_clause 0x14242; GFX10-NEXT: s_load_dword s2, s[8:9], 0x84243; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x04244; GFX10-NEXT: v_mov_b32_e32 v0, 04245; GFX10-NEXT: s_waitcnt lgkmcnt(0)4246; GFX10-NEXT: s_ashr_i32 s3, s2, 164247; GFX10-NEXT: s_sext_i32_i16 s2, s24248; GFX10-NEXT: s_min_i32 s2, s2, s34249; GFX10-NEXT: v_mov_b32_e32 v1, s24250; GFX10-NEXT: global_store_short v0, v1, s[0:1]4251; GFX10-NEXT: s_endpgm4252;4253; GFX11-LABEL: s_test_imin_sle_i16:4254; GFX11: ; %bb.0:4255; GFX11-NEXT: s_clause 0x14256; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x84257; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x04258; GFX11-NEXT: v_mov_b32_e32 v0, 04259; GFX11-NEXT: s_waitcnt lgkmcnt(0)4260; GFX11-NEXT: s_ashr_i32 s3, s2, 164261; GFX11-NEXT: s_sext_i32_i16 s2, s24262; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4263; GFX11-NEXT: s_min_i32 s2, s2, s34264; GFX11-NEXT: v_mov_b32_e32 v1, s24265; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]4266; GFX11-NEXT: s_endpgm4267;4268; GFX1250-LABEL: s_test_imin_sle_i16:4269; GFX1250: ; %bb.0:4270; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14271; GFX1250-NEXT: s_load_b96 s[0:2], s[4:5], 0x04272; GFX1250-NEXT: v_mov_b32_e32 v0, 04273; GFX1250-NEXT: s_wait_kmcnt 0x04274; GFX1250-NEXT: s_ashr_i32 s3, s2, 164275; GFX1250-NEXT: s_sext_i32_i16 s2, s24276; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)4277; GFX1250-NEXT: s_min_i32 s2, s2, s34278; GFX1250-NEXT: v_mov_b32_e32 v1, s24279; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1]4280; GFX1250-NEXT: s_endpgm4281 %cmp = icmp sle i16 %a, %b4282 %val = select i1 %cmp, i16 %a, i16 %b4283 store i16 %val, ptr addrspace(1) %out4284 ret void4285}4286 4287; 64 bit4288 4289define amdgpu_kernel void @test_umin_ult_i64(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {4290; EG-LABEL: test_umin_ult_i64:4291; EG: ; %bb.0:4292; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]4293; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14294; EG-NEXT: CF_END4295; EG-NEXT: PAD4296; EG-NEXT: ALU clause starting at 4:4297; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,4298; EG-NEXT: SETGT_UINT * T0.W, KC0[3].Z, KC0[3].X,4299; EG-NEXT: SETGT_UINT * T1.W, KC0[3].Y, KC0[2].W,4300; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,4301; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,4302; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,4303; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4304; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4305;4306; CI-LABEL: test_umin_ult_i64:4307; CI: ; %bb.0:4308; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04309; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x44310; CI-NEXT: s_add_i32 s12, s12, s174311; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84312; CI-NEXT: s_mov_b32 flat_scratch_lo, s134313; CI-NEXT: s_waitcnt lgkmcnt(0)4314; CI-NEXT: v_mov_b32_e32 v0, s04315; CI-NEXT: v_mov_b32_e32 v1, s44316; CI-NEXT: v_mov_b32_e32 v2, s54317; CI-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[1:2]4318; CI-NEXT: v_mov_b32_e32 v1, s14319; CI-NEXT: s_and_b64 s[0:1], vcc, exec4320; CI-NEXT: s_cselect_b32 s0, s3, s54321; CI-NEXT: s_cselect_b32 s1, s2, s44322; CI-NEXT: v_mov_b32_e32 v2, s14323; CI-NEXT: v_mov_b32_e32 v3, s04324; CI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4325; CI-NEXT: s_endpgm4326;4327; VI-LABEL: test_umin_ult_i64:4328; VI: ; %bb.0:4329; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04330; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104331; VI-NEXT: s_add_i32 s12, s12, s174332; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84333; VI-NEXT: s_mov_b32 flat_scratch_lo, s134334; VI-NEXT: s_waitcnt lgkmcnt(0)4335; VI-NEXT: v_mov_b32_e32 v0, s04336; VI-NEXT: v_mov_b32_e32 v1, s44337; VI-NEXT: v_mov_b32_e32 v2, s54338; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[1:2]4339; VI-NEXT: v_mov_b32_e32 v1, s14340; VI-NEXT: s_and_b64 s[0:1], vcc, exec4341; VI-NEXT: s_cselect_b32 s0, s3, s54342; VI-NEXT: s_cselect_b32 s1, s2, s44343; VI-NEXT: v_mov_b32_e32 v2, s14344; VI-NEXT: v_mov_b32_e32 v3, s04345; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4346; VI-NEXT: s_endpgm4347;4348; GFX9-LABEL: test_umin_ult_i64:4349; GFX9: ; %bb.0:4350; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104351; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04352; GFX9-NEXT: v_mov_b32_e32 v2, 04353; GFX9-NEXT: s_waitcnt lgkmcnt(0)4354; GFX9-NEXT: v_mov_b32_e32 v0, s44355; GFX9-NEXT: v_mov_b32_e32 v1, s54356; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]4357; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec4358; GFX9-NEXT: s_cselect_b32 s3, s3, s54359; GFX9-NEXT: s_cselect_b32 s2, s2, s44360; GFX9-NEXT: v_mov_b32_e32 v0, s24361; GFX9-NEXT: v_mov_b32_e32 v1, s34362; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4363; GFX9-NEXT: s_endpgm4364;4365; GFX10-LABEL: test_umin_ult_i64:4366; GFX10: ; %bb.0:4367; GFX10-NEXT: s_clause 0x14368; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04369; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104370; GFX10-NEXT: v_mov_b32_e32 v2, 04371; GFX10-NEXT: s_waitcnt lgkmcnt(0)4372; GFX10-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[4:5]4373; GFX10-NEXT: s_and_b32 s6, s6, exec_lo4374; GFX10-NEXT: s_cselect_b32 s2, s2, s44375; GFX10-NEXT: s_cselect_b32 s3, s3, s54376; GFX10-NEXT: v_mov_b32_e32 v0, s24377; GFX10-NEXT: v_mov_b32_e32 v1, s34378; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4379; GFX10-NEXT: s_endpgm4380;4381; GFX11-LABEL: test_umin_ult_i64:4382; GFX11: ; %bb.0:4383; GFX11-NEXT: s_clause 0x14384; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x04385; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x104386; GFX11-NEXT: v_mov_b32_e32 v2, 04387; GFX11-NEXT: s_waitcnt lgkmcnt(0)4388; GFX11-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[4:5]4389; GFX11-NEXT: s_and_b32 s6, s6, exec_lo4390; GFX11-NEXT: s_cselect_b32 s2, s2, s44391; GFX11-NEXT: s_cselect_b32 s3, s3, s54392; GFX11-NEXT: v_mov_b32_e32 v0, s24393; GFX11-NEXT: v_mov_b32_e32 v1, s34394; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]4395; GFX11-NEXT: s_endpgm4396;4397; GFX1250-LABEL: test_umin_ult_i64:4398; GFX1250: ; %bb.0:4399; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14400; GFX1250-NEXT: s_clause 0x14401; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x04402; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x104403; GFX1250-NEXT: v_mov_b32_e32 v2, 04404; GFX1250-NEXT: s_wait_kmcnt 0x04405; GFX1250-NEXT: v_min_u64 v[0:1], s[2:3], s[6:7]4406; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]4407; GFX1250-NEXT: s_endpgm4408 %tmp = icmp ult i64 %a, %b4409 %val = select i1 %tmp, i64 %a, i64 %b4410 store i64 %val, ptr addrspace(1) %out, align 84411 ret void4412}4413 4414define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {4415; EG-LABEL: test_umin_ule_i64:4416; EG: ; %bb.0:4417; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]4418; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14419; EG-NEXT: CF_END4420; EG-NEXT: PAD4421; EG-NEXT: ALU clause starting at 4:4422; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,4423; EG-NEXT: SETGT_UINT * T0.W, KC0[3].Z, KC0[3].X,4424; EG-NEXT: SETGT_UINT * T1.W, KC0[3].Y, KC0[2].W,4425; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,4426; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,4427; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,4428; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4429; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4430;4431; CI-LABEL: test_umin_ule_i64:4432; CI: ; %bb.0:4433; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04434; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x44435; CI-NEXT: s_add_i32 s12, s12, s174436; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84437; CI-NEXT: s_mov_b32 flat_scratch_lo, s134438; CI-NEXT: s_waitcnt lgkmcnt(0)4439; CI-NEXT: v_mov_b32_e32 v0, s04440; CI-NEXT: v_mov_b32_e32 v1, s44441; CI-NEXT: v_mov_b32_e32 v2, s54442; CI-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[1:2]4443; CI-NEXT: v_mov_b32_e32 v1, s14444; CI-NEXT: s_and_b64 s[0:1], vcc, exec4445; CI-NEXT: s_cselect_b32 s0, s3, s54446; CI-NEXT: s_cselect_b32 s1, s2, s44447; CI-NEXT: v_mov_b32_e32 v2, s14448; CI-NEXT: v_mov_b32_e32 v3, s04449; CI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4450; CI-NEXT: s_endpgm4451;4452; VI-LABEL: test_umin_ule_i64:4453; VI: ; %bb.0:4454; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04455; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104456; VI-NEXT: s_add_i32 s12, s12, s174457; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84458; VI-NEXT: s_mov_b32 flat_scratch_lo, s134459; VI-NEXT: s_waitcnt lgkmcnt(0)4460; VI-NEXT: v_mov_b32_e32 v0, s04461; VI-NEXT: v_mov_b32_e32 v1, s44462; VI-NEXT: v_mov_b32_e32 v2, s54463; VI-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[1:2]4464; VI-NEXT: v_mov_b32_e32 v1, s14465; VI-NEXT: s_and_b64 s[0:1], vcc, exec4466; VI-NEXT: s_cselect_b32 s0, s3, s54467; VI-NEXT: s_cselect_b32 s1, s2, s44468; VI-NEXT: v_mov_b32_e32 v2, s14469; VI-NEXT: v_mov_b32_e32 v3, s04470; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4471; VI-NEXT: s_endpgm4472;4473; GFX9-LABEL: test_umin_ule_i64:4474; GFX9: ; %bb.0:4475; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104476; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04477; GFX9-NEXT: v_mov_b32_e32 v2, 04478; GFX9-NEXT: s_waitcnt lgkmcnt(0)4479; GFX9-NEXT: v_mov_b32_e32 v0, s44480; GFX9-NEXT: v_mov_b32_e32 v1, s54481; GFX9-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[0:1]4482; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec4483; GFX9-NEXT: s_cselect_b32 s3, s3, s54484; GFX9-NEXT: s_cselect_b32 s2, s2, s44485; GFX9-NEXT: v_mov_b32_e32 v0, s24486; GFX9-NEXT: v_mov_b32_e32 v1, s34487; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4488; GFX9-NEXT: s_endpgm4489;4490; GFX10-LABEL: test_umin_ule_i64:4491; GFX10: ; %bb.0:4492; GFX10-NEXT: s_clause 0x14493; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04494; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104495; GFX10-NEXT: v_mov_b32_e32 v2, 04496; GFX10-NEXT: s_waitcnt lgkmcnt(0)4497; GFX10-NEXT: v_cmp_le_u64_e64 s6, s[2:3], s[4:5]4498; GFX10-NEXT: s_and_b32 s6, s6, exec_lo4499; GFX10-NEXT: s_cselect_b32 s2, s2, s44500; GFX10-NEXT: s_cselect_b32 s3, s3, s54501; GFX10-NEXT: v_mov_b32_e32 v0, s24502; GFX10-NEXT: v_mov_b32_e32 v1, s34503; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4504; GFX10-NEXT: s_endpgm4505;4506; GFX11-LABEL: test_umin_ule_i64:4507; GFX11: ; %bb.0:4508; GFX11-NEXT: s_clause 0x14509; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x04510; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x104511; GFX11-NEXT: v_mov_b32_e32 v2, 04512; GFX11-NEXT: s_waitcnt lgkmcnt(0)4513; GFX11-NEXT: v_cmp_le_u64_e64 s6, s[2:3], s[4:5]4514; GFX11-NEXT: s_and_b32 s6, s6, exec_lo4515; GFX11-NEXT: s_cselect_b32 s2, s2, s44516; GFX11-NEXT: s_cselect_b32 s3, s3, s54517; GFX11-NEXT: v_mov_b32_e32 v0, s24518; GFX11-NEXT: v_mov_b32_e32 v1, s34519; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]4520; GFX11-NEXT: s_endpgm4521;4522; GFX1250-LABEL: test_umin_ule_i64:4523; GFX1250: ; %bb.0:4524; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14525; GFX1250-NEXT: s_clause 0x14526; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x04527; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x104528; GFX1250-NEXT: v_mov_b32_e32 v2, 04529; GFX1250-NEXT: s_wait_kmcnt 0x04530; GFX1250-NEXT: v_min_u64 v[0:1], s[2:3], s[6:7]4531; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]4532; GFX1250-NEXT: s_endpgm4533 %tmp = icmp ule i64 %a, %b4534 %val = select i1 %tmp, i64 %a, i64 %b4535 store i64 %val, ptr addrspace(1) %out, align 84536 ret void4537}4538 4539define amdgpu_kernel void @test_imin_slt_i64(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {4540; EG-LABEL: test_imin_slt_i64:4541; EG: ; %bb.0:4542; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]4543; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14544; EG-NEXT: CF_END4545; EG-NEXT: PAD4546; EG-NEXT: ALU clause starting at 4:4547; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,4548; EG-NEXT: SETGT_INT * T0.W, KC0[3].Z, KC0[3].X,4549; EG-NEXT: SETGT_UINT * T1.W, KC0[3].Y, KC0[2].W,4550; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,4551; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,4552; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,4553; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4554; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4555;4556; CI-LABEL: test_imin_slt_i64:4557; CI: ; %bb.0:4558; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04559; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x44560; CI-NEXT: s_add_i32 s12, s12, s174561; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84562; CI-NEXT: s_mov_b32 flat_scratch_lo, s134563; CI-NEXT: s_waitcnt lgkmcnt(0)4564; CI-NEXT: v_mov_b32_e32 v0, s04565; CI-NEXT: v_mov_b32_e32 v1, s44566; CI-NEXT: v_mov_b32_e32 v2, s54567; CI-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[1:2]4568; CI-NEXT: v_mov_b32_e32 v1, s14569; CI-NEXT: s_and_b64 s[0:1], vcc, exec4570; CI-NEXT: s_cselect_b32 s0, s3, s54571; CI-NEXT: s_cselect_b32 s1, s2, s44572; CI-NEXT: v_mov_b32_e32 v2, s14573; CI-NEXT: v_mov_b32_e32 v3, s04574; CI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4575; CI-NEXT: s_endpgm4576;4577; VI-LABEL: test_imin_slt_i64:4578; VI: ; %bb.0:4579; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04580; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104581; VI-NEXT: s_add_i32 s12, s12, s174582; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84583; VI-NEXT: s_mov_b32 flat_scratch_lo, s134584; VI-NEXT: s_waitcnt lgkmcnt(0)4585; VI-NEXT: v_mov_b32_e32 v0, s04586; VI-NEXT: v_mov_b32_e32 v1, s44587; VI-NEXT: v_mov_b32_e32 v2, s54588; VI-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[1:2]4589; VI-NEXT: v_mov_b32_e32 v1, s14590; VI-NEXT: s_and_b64 s[0:1], vcc, exec4591; VI-NEXT: s_cselect_b32 s0, s3, s54592; VI-NEXT: s_cselect_b32 s1, s2, s44593; VI-NEXT: v_mov_b32_e32 v2, s14594; VI-NEXT: v_mov_b32_e32 v3, s04595; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4596; VI-NEXT: s_endpgm4597;4598; GFX9-LABEL: test_imin_slt_i64:4599; GFX9: ; %bb.0:4600; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104601; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04602; GFX9-NEXT: v_mov_b32_e32 v2, 04603; GFX9-NEXT: s_waitcnt lgkmcnt(0)4604; GFX9-NEXT: v_mov_b32_e32 v0, s44605; GFX9-NEXT: v_mov_b32_e32 v1, s54606; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]4607; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec4608; GFX9-NEXT: s_cselect_b32 s3, s3, s54609; GFX9-NEXT: s_cselect_b32 s2, s2, s44610; GFX9-NEXT: v_mov_b32_e32 v0, s24611; GFX9-NEXT: v_mov_b32_e32 v1, s34612; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4613; GFX9-NEXT: s_endpgm4614;4615; GFX10-LABEL: test_imin_slt_i64:4616; GFX10: ; %bb.0:4617; GFX10-NEXT: s_clause 0x14618; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04619; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104620; GFX10-NEXT: v_mov_b32_e32 v2, 04621; GFX10-NEXT: s_waitcnt lgkmcnt(0)4622; GFX10-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[4:5]4623; GFX10-NEXT: s_and_b32 s6, s6, exec_lo4624; GFX10-NEXT: s_cselect_b32 s2, s2, s44625; GFX10-NEXT: s_cselect_b32 s3, s3, s54626; GFX10-NEXT: v_mov_b32_e32 v0, s24627; GFX10-NEXT: v_mov_b32_e32 v1, s34628; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4629; GFX10-NEXT: s_endpgm4630;4631; GFX11-LABEL: test_imin_slt_i64:4632; GFX11: ; %bb.0:4633; GFX11-NEXT: s_clause 0x14634; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x04635; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x104636; GFX11-NEXT: v_mov_b32_e32 v2, 04637; GFX11-NEXT: s_waitcnt lgkmcnt(0)4638; GFX11-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[4:5]4639; GFX11-NEXT: s_and_b32 s6, s6, exec_lo4640; GFX11-NEXT: s_cselect_b32 s2, s2, s44641; GFX11-NEXT: s_cselect_b32 s3, s3, s54642; GFX11-NEXT: v_mov_b32_e32 v0, s24643; GFX11-NEXT: v_mov_b32_e32 v1, s34644; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]4645; GFX11-NEXT: s_endpgm4646;4647; GFX1250-LABEL: test_imin_slt_i64:4648; GFX1250: ; %bb.0:4649; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14650; GFX1250-NEXT: s_clause 0x14651; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x04652; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x104653; GFX1250-NEXT: v_mov_b32_e32 v2, 04654; GFX1250-NEXT: s_wait_kmcnt 0x04655; GFX1250-NEXT: v_min_i64 v[0:1], s[2:3], s[6:7]4656; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]4657; GFX1250-NEXT: s_endpgm4658 %tmp = icmp slt i64 %a, %b4659 %val = select i1 %tmp, i64 %a, i64 %b4660 store i64 %val, ptr addrspace(1) %out, align 84661 ret void4662}4663 4664define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {4665; EG-LABEL: test_imin_sle_i64:4666; EG: ; %bb.0:4667; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]4668; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 14669; EG-NEXT: CF_END4670; EG-NEXT: PAD4671; EG-NEXT: ALU clause starting at 4:4672; EG-NEXT: SETE_INT T0.Z, KC0[3].X, KC0[3].Z,4673; EG-NEXT: SETGT_INT * T0.W, KC0[3].Z, KC0[3].X,4674; EG-NEXT: SETGT_UINT * T1.W, KC0[3].Y, KC0[2].W,4675; EG-NEXT: CNDE_INT * T0.W, T0.Z, T0.W, PV.W,4676; EG-NEXT: CNDE_INT * T0.Y, PV.W, KC0[3].Z, KC0[3].X,4677; EG-NEXT: CNDE_INT * T0.X, T0.W, KC0[3].Y, KC0[2].W,4678; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,4679; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4680;4681; CI-LABEL: test_imin_sle_i64:4682; CI: ; %bb.0:4683; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04684; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x44685; CI-NEXT: s_add_i32 s12, s12, s174686; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84687; CI-NEXT: s_mov_b32 flat_scratch_lo, s134688; CI-NEXT: s_waitcnt lgkmcnt(0)4689; CI-NEXT: v_mov_b32_e32 v0, s04690; CI-NEXT: v_mov_b32_e32 v1, s44691; CI-NEXT: v_mov_b32_e32 v2, s54692; CI-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[1:2]4693; CI-NEXT: v_mov_b32_e32 v1, s14694; CI-NEXT: s_and_b64 s[0:1], vcc, exec4695; CI-NEXT: s_cselect_b32 s0, s3, s54696; CI-NEXT: s_cselect_b32 s1, s2, s44697; CI-NEXT: v_mov_b32_e32 v2, s14698; CI-NEXT: v_mov_b32_e32 v3, s04699; CI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4700; CI-NEXT: s_endpgm4701;4702; VI-LABEL: test_imin_sle_i64:4703; VI: ; %bb.0:4704; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04705; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104706; VI-NEXT: s_add_i32 s12, s12, s174707; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84708; VI-NEXT: s_mov_b32 flat_scratch_lo, s134709; VI-NEXT: s_waitcnt lgkmcnt(0)4710; VI-NEXT: v_mov_b32_e32 v0, s04711; VI-NEXT: v_mov_b32_e32 v1, s44712; VI-NEXT: v_mov_b32_e32 v2, s54713; VI-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[1:2]4714; VI-NEXT: v_mov_b32_e32 v1, s14715; VI-NEXT: s_and_b64 s[0:1], vcc, exec4716; VI-NEXT: s_cselect_b32 s0, s3, s54717; VI-NEXT: s_cselect_b32 s1, s2, s44718; VI-NEXT: v_mov_b32_e32 v2, s14719; VI-NEXT: v_mov_b32_e32 v3, s04720; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]4721; VI-NEXT: s_endpgm4722;4723; GFX9-LABEL: test_imin_sle_i64:4724; GFX9: ; %bb.0:4725; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104726; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04727; GFX9-NEXT: v_mov_b32_e32 v2, 04728; GFX9-NEXT: s_waitcnt lgkmcnt(0)4729; GFX9-NEXT: v_mov_b32_e32 v0, s44730; GFX9-NEXT: v_mov_b32_e32 v1, s54731; GFX9-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[0:1]4732; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec4733; GFX9-NEXT: s_cselect_b32 s3, s3, s54734; GFX9-NEXT: s_cselect_b32 s2, s2, s44735; GFX9-NEXT: v_mov_b32_e32 v0, s24736; GFX9-NEXT: v_mov_b32_e32 v1, s34737; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4738; GFX9-NEXT: s_endpgm4739;4740; GFX10-LABEL: test_imin_sle_i64:4741; GFX10: ; %bb.0:4742; GFX10-NEXT: s_clause 0x14743; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04744; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104745; GFX10-NEXT: v_mov_b32_e32 v2, 04746; GFX10-NEXT: s_waitcnt lgkmcnt(0)4747; GFX10-NEXT: v_cmp_le_i64_e64 s6, s[2:3], s[4:5]4748; GFX10-NEXT: s_and_b32 s6, s6, exec_lo4749; GFX10-NEXT: s_cselect_b32 s2, s2, s44750; GFX10-NEXT: s_cselect_b32 s3, s3, s54751; GFX10-NEXT: v_mov_b32_e32 v0, s24752; GFX10-NEXT: v_mov_b32_e32 v1, s34753; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]4754; GFX10-NEXT: s_endpgm4755;4756; GFX11-LABEL: test_imin_sle_i64:4757; GFX11: ; %bb.0:4758; GFX11-NEXT: s_clause 0x14759; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x04760; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x104761; GFX11-NEXT: v_mov_b32_e32 v2, 04762; GFX11-NEXT: s_waitcnt lgkmcnt(0)4763; GFX11-NEXT: v_cmp_le_i64_e64 s6, s[2:3], s[4:5]4764; GFX11-NEXT: s_and_b32 s6, s6, exec_lo4765; GFX11-NEXT: s_cselect_b32 s2, s2, s44766; GFX11-NEXT: s_cselect_b32 s3, s3, s54767; GFX11-NEXT: v_mov_b32_e32 v0, s24768; GFX11-NEXT: v_mov_b32_e32 v1, s34769; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]4770; GFX11-NEXT: s_endpgm4771;4772; GFX1250-LABEL: test_imin_sle_i64:4773; GFX1250: ; %bb.0:4774; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14775; GFX1250-NEXT: s_clause 0x14776; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x04777; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x104778; GFX1250-NEXT: v_mov_b32_e32 v2, 04779; GFX1250-NEXT: s_wait_kmcnt 0x04780; GFX1250-NEXT: v_min_i64 v[0:1], s[2:3], s[6:7]4781; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1]4782; GFX1250-NEXT: s_endpgm4783 %tmp = icmp sle i64 %a, %b4784 %val = select i1 %tmp, i64 %a, i64 %b4785 store i64 %val, ptr addrspace(1) %out, align 84786 ret void4787}4788 4789define amdgpu_kernel void @v_test_imin_sle_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {4790; EG-LABEL: v_test_imin_sle_v2i16:4791; EG: ; %bb.0:4792; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[]4793; EG-NEXT: TEX 0 @84794; EG-NEXT: ALU 0, @15, KC0[CB0:0-32], KC1[]4795; EG-NEXT: TEX 0 @104796; EG-NEXT: ALU 16, @16, KC0[CB0:0-32], KC1[]4797; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 14798; EG-NEXT: CF_END4799; EG-NEXT: PAD4800; EG-NEXT: Fetch clause starting at 8:4801; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #14802; EG-NEXT: Fetch clause starting at 10:4803; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #14804; EG-NEXT: ALU clause starting at 12:4805; EG-NEXT: LSHL * T0.W, T0.X, literal.x,4806; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4807; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,4808; EG-NEXT: ALU clause starting at 15:4809; EG-NEXT: ADD_INT * T7.X, KC0[2].W, T0.W,4810; EG-NEXT: ALU clause starting at 16:4811; EG-NEXT: LSHR T1.W, T0.X, literal.x,4812; EG-NEXT: LSHR * T2.W, T7.X, literal.x,4813; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4814; EG-NEXT: BFE_INT T8.X, PS, 0.0, literal.x,4815; EG-NEXT: BFE_INT T0.Y, PV.W, 0.0, literal.x,4816; EG-NEXT: BFE_INT T0.Z, T7.X, 0.0, literal.x,4817; EG-NEXT: BFE_INT * T1.W, T0.X, 0.0, literal.x, BS:VEC_120/SCL_2124818; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4819; EG-NEXT: MIN_INT T1.W, PV.W, PV.Z,4820; EG-NEXT: MIN_INT * T2.W, PV.Y, PV.X,4821; EG-NEXT: LSHL T2.W, PS, literal.x,4822; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,4823; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)4824; EG-NEXT: OR_INT T0.X, PS, PV.W,4825; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,4826; EG-NEXT: LSHR * T7.X, PV.W, literal.x,4827; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4828;4829; CI-LABEL: v_test_imin_sle_v2i16:4830; CI: ; %bb.0:4831; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04832; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x44833; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v04834; CI-NEXT: s_add_i32 s12, s12, s174835; CI-NEXT: s_mov_b32 flat_scratch_lo, s134836; CI-NEXT: s_waitcnt lgkmcnt(0)4837; CI-NEXT: v_mov_b32_e32 v1, s34838; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v24839; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84840; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4841; CI-NEXT: v_mov_b32_e32 v3, s54842; CI-NEXT: flat_load_dword v4, v[0:1]4843; CI-NEXT: v_add_i32_e32 v0, vcc, s4, v24844; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc4845; CI-NEXT: flat_load_dword v3, v[0:1]4846; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v24847; CI-NEXT: v_mov_b32_e32 v1, s14848; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4849; CI-NEXT: s_waitcnt vmcnt(1)4850; CI-NEXT: v_bfe_i32 v2, v4, 0, 164851; CI-NEXT: v_ashrrev_i32_e32 v4, 16, v44852; CI-NEXT: s_waitcnt vmcnt(0)4853; CI-NEXT: v_bfe_i32 v5, v3, 0, 164854; CI-NEXT: v_ashrrev_i32_e32 v3, 16, v34855; CI-NEXT: v_min_i32_e32 v3, v4, v34856; CI-NEXT: v_min_i32_e32 v2, v2, v54857; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v34858; CI-NEXT: v_and_b32_e32 v2, 0xffff, v24859; CI-NEXT: v_or_b32_e32 v2, v2, v34860; CI-NEXT: flat_store_dword v[0:1], v24861; CI-NEXT: s_endpgm4862;4863; VI-LABEL: v_test_imin_sle_v2i16:4864; VI: ; %bb.0:4865; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04866; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104867; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v04868; VI-NEXT: s_add_i32 s12, s12, s174869; VI-NEXT: s_mov_b32 flat_scratch_lo, s134870; VI-NEXT: s_waitcnt lgkmcnt(0)4871; VI-NEXT: v_mov_b32_e32 v1, s34872; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v44873; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4874; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 84875; VI-NEXT: v_mov_b32_e32 v3, s54876; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v44877; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4878; VI-NEXT: flat_load_dword v5, v[0:1]4879; VI-NEXT: flat_load_dword v2, v[2:3]4880; VI-NEXT: v_mov_b32_e32 v1, s14881; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v44882; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4883; VI-NEXT: s_waitcnt vmcnt(0)4884; VI-NEXT: v_min_i16_e32 v3, v5, v24885; VI-NEXT: v_min_i16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_14886; VI-NEXT: v_or_b32_e32 v2, v3, v24887; VI-NEXT: flat_store_dword v[0:1], v24888; VI-NEXT: s_endpgm4889;4890; GFX9-LABEL: v_test_imin_sle_v2i16:4891; GFX9: ; %bb.0:4892; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04893; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104894; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v04895; GFX9-NEXT: s_waitcnt lgkmcnt(0)4896; GFX9-NEXT: global_load_dword v1, v0, s[2:3]4897; GFX9-NEXT: global_load_dword v2, v0, s[4:5]4898; GFX9-NEXT: s_waitcnt vmcnt(0)4899; GFX9-NEXT: v_pk_min_i16 v1, v1, v24900; GFX9-NEXT: global_store_dword v0, v1, s[0:1]4901; GFX9-NEXT: s_endpgm4902;4903; GFX10-LABEL: v_test_imin_sle_v2i16:4904; GFX10: ; %bb.0:4905; GFX10-NEXT: s_clause 0x14906; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x04907; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x104908; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v04909; GFX10-NEXT: s_waitcnt lgkmcnt(0)4910; GFX10-NEXT: s_clause 0x14911; GFX10-NEXT: global_load_dword v1, v0, s[2:3]4912; GFX10-NEXT: global_load_dword v2, v0, s[4:5]4913; GFX10-NEXT: s_waitcnt vmcnt(0)4914; GFX10-NEXT: v_pk_min_i16 v1, v1, v24915; GFX10-NEXT: global_store_dword v0, v1, s[0:1]4916; GFX10-NEXT: s_endpgm4917;4918; GFX11-LABEL: v_test_imin_sle_v2i16:4919; GFX11: ; %bb.0:4920; GFX11-NEXT: s_clause 0x14921; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x04922; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x104923; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v04924; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4925; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v04926; GFX11-NEXT: s_waitcnt lgkmcnt(0)4927; GFX11-NEXT: s_clause 0x14928; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]4929; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]4930; GFX11-NEXT: s_waitcnt vmcnt(0)4931; GFX11-NEXT: v_pk_min_i16 v1, v1, v24932; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]4933; GFX11-NEXT: s_endpgm4934;4935; GFX1250-LABEL: v_test_imin_sle_v2i16:4936; GFX1250: ; %bb.0:4937; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 14938; GFX1250-NEXT: s_clause 0x14939; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x04940; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x104941; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v04942; GFX1250-NEXT: s_wait_kmcnt 0x04943; GFX1250-NEXT: s_clause 0x14944; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset4945; GFX1250-NEXT: global_load_b32 v2, v0, s[6:7] scale_offset4946; GFX1250-NEXT: s_wait_loadcnt 0x04947; GFX1250-NEXT: v_pk_min_i16 v1, v1, v24948; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset4949; GFX1250-NEXT: s_endpgm4950 %tid = call i32 @llvm.amdgcn.workitem.id.x()4951 %a.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %a.ptr, i32 %tid4952 %b.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %b.ptr, i32 %tid4953 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid4954 %a = load <2 x i16>, ptr addrspace(1) %a.gep4955 %b = load <2 x i16>, ptr addrspace(1) %b.gep4956 %cmp = icmp sle <2 x i16> %a, %b4957 %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b4958 store <2 x i16> %val, ptr addrspace(1) %out.gep4959 ret void4960}4961 4962; FIXME: i16 min4963 4964define amdgpu_kernel void @v_test_imin_ule_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 {4965; EG-LABEL: v_test_imin_ule_v2i16:4966; EG: ; %bb.0:4967; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[]4968; EG-NEXT: TEX 0 @84969; EG-NEXT: ALU 0, @15, KC0[CB0:0-32], KC1[]4970; EG-NEXT: TEX 0 @104971; EG-NEXT: ALU 13, @16, KC0[CB0:0-32], KC1[]4972; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 14973; EG-NEXT: CF_END4974; EG-NEXT: PAD4975; EG-NEXT: Fetch clause starting at 8:4976; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #14977; EG-NEXT: Fetch clause starting at 10:4978; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #14979; EG-NEXT: ALU clause starting at 12:4980; EG-NEXT: LSHL * T0.W, T0.X, literal.x,4981; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)4982; EG-NEXT: ADD_INT * T0.X, KC0[2].W, PV.W,4983; EG-NEXT: ALU clause starting at 15:4984; EG-NEXT: ADD_INT * T7.X, KC0[2].Z, T0.W,4985; EG-NEXT: ALU clause starting at 16:4986; EG-NEXT: LSHR T1.W, T0.X, literal.x,4987; EG-NEXT: LSHR * T2.W, T7.X, literal.x,4988; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4989; EG-NEXT: AND_INT T0.Z, T0.X, literal.x,4990; EG-NEXT: AND_INT T3.W, T7.X, literal.x, BS:VEC_120/SCL_2124991; EG-NEXT: MIN_UINT * T1.W, PS, PV.W,4992; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)4993; EG-NEXT: LSHL T1.W, PS, literal.x,4994; EG-NEXT: MIN_UINT * T2.W, PV.W, PV.Z,4995; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)4996; EG-NEXT: OR_INT T0.X, PS, PV.W,4997; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,4998; EG-NEXT: LSHR * T7.X, PV.W, literal.x,4999; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)5000;5001; CI-LABEL: v_test_imin_ule_v2i16:5002; CI: ; %bb.0:5003; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x05004; CI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x45005; CI-NEXT: v_lshlrev_b32_e32 v2, 2, v05006; CI-NEXT: s_add_i32 s12, s12, s175007; CI-NEXT: s_mov_b32 flat_scratch_lo, s135008; CI-NEXT: s_waitcnt lgkmcnt(0)5009; CI-NEXT: v_mov_b32_e32 v1, s35010; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v25011; CI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 85012; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5013; CI-NEXT: v_mov_b32_e32 v3, s55014; CI-NEXT: flat_load_dword v4, v[0:1]5015; CI-NEXT: v_add_i32_e32 v0, vcc, s4, v25016; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc5017; CI-NEXT: flat_load_dword v3, v[0:1]5018; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v25019; CI-NEXT: v_mov_b32_e32 v1, s15020; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5021; CI-NEXT: s_waitcnt vmcnt(1)5022; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v45023; CI-NEXT: v_and_b32_e32 v4, 0xffff, v45024; CI-NEXT: s_waitcnt vmcnt(0)5025; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v35026; CI-NEXT: v_and_b32_e32 v3, 0xffff, v35027; CI-NEXT: v_min_u32_e32 v2, v2, v55028; CI-NEXT: v_min_u32_e32 v3, v4, v35029; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v25030; CI-NEXT: v_or_b32_e32 v2, v3, v25031; CI-NEXT: flat_store_dword v[0:1], v25032; CI-NEXT: s_endpgm5033;5034; VI-LABEL: v_test_imin_ule_v2i16:5035; VI: ; %bb.0:5036; VI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x05037; VI-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x105038; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v05039; VI-NEXT: s_add_i32 s12, s12, s175040; VI-NEXT: s_mov_b32 flat_scratch_lo, s135041; VI-NEXT: s_waitcnt lgkmcnt(0)5042; VI-NEXT: v_mov_b32_e32 v1, s35043; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v45044; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5045; VI-NEXT: s_lshr_b32 flat_scratch_hi, s12, 85046; VI-NEXT: v_mov_b32_e32 v3, s55047; VI-NEXT: v_add_u32_e32 v2, vcc, s4, v45048; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5049; VI-NEXT: flat_load_dword v5, v[0:1]5050; VI-NEXT: flat_load_dword v2, v[2:3]5051; VI-NEXT: v_mov_b32_e32 v1, s15052; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v45053; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5054; VI-NEXT: s_waitcnt vmcnt(0)5055; VI-NEXT: v_min_u16_e32 v3, v5, v25056; VI-NEXT: v_min_u16_sdwa v2, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_15057; VI-NEXT: v_or_b32_e32 v2, v3, v25058; VI-NEXT: flat_store_dword v[0:1], v25059; VI-NEXT: s_endpgm5060;5061; GFX9-LABEL: v_test_imin_ule_v2i16:5062; GFX9: ; %bb.0:5063; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x05064; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x105065; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v05066; GFX9-NEXT: s_waitcnt lgkmcnt(0)5067; GFX9-NEXT: global_load_dword v1, v0, s[2:3]5068; GFX9-NEXT: global_load_dword v2, v0, s[4:5]5069; GFX9-NEXT: s_waitcnt vmcnt(0)5070; GFX9-NEXT: v_pk_min_u16 v1, v1, v25071; GFX9-NEXT: global_store_dword v0, v1, s[0:1]5072; GFX9-NEXT: s_endpgm5073;5074; GFX10-LABEL: v_test_imin_ule_v2i16:5075; GFX10: ; %bb.0:5076; GFX10-NEXT: s_clause 0x15077; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x05078; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x105079; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v05080; GFX10-NEXT: s_waitcnt lgkmcnt(0)5081; GFX10-NEXT: s_clause 0x15082; GFX10-NEXT: global_load_dword v1, v0, s[2:3]5083; GFX10-NEXT: global_load_dword v2, v0, s[4:5]5084; GFX10-NEXT: s_waitcnt vmcnt(0)5085; GFX10-NEXT: v_pk_min_u16 v1, v1, v25086; GFX10-NEXT: global_store_dword v0, v1, s[0:1]5087; GFX10-NEXT: s_endpgm5088;5089; GFX11-LABEL: v_test_imin_ule_v2i16:5090; GFX11: ; %bb.0:5091; GFX11-NEXT: s_clause 0x15092; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x05093; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x105094; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v05095; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)5096; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v05097; GFX11-NEXT: s_waitcnt lgkmcnt(0)5098; GFX11-NEXT: s_clause 0x15099; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]5100; GFX11-NEXT: global_load_b32 v2, v0, s[4:5]5101; GFX11-NEXT: s_waitcnt vmcnt(0)5102; GFX11-NEXT: v_pk_min_u16 v1, v1, v25103; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]5104; GFX11-NEXT: s_endpgm5105;5106; GFX1250-LABEL: v_test_imin_ule_v2i16:5107; GFX1250: ; %bb.0:5108; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 15109; GFX1250-NEXT: s_clause 0x15110; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x05111; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x105112; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v05113; GFX1250-NEXT: s_wait_kmcnt 0x05114; GFX1250-NEXT: s_clause 0x15115; GFX1250-NEXT: global_load_b32 v1, v0, s[2:3] scale_offset5116; GFX1250-NEXT: global_load_b32 v2, v0, s[6:7] scale_offset5117; GFX1250-NEXT: s_wait_loadcnt 0x05118; GFX1250-NEXT: v_pk_min_u16 v1, v1, v25119; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] scale_offset5120; GFX1250-NEXT: s_endpgm5121 %tid = call i32 @llvm.amdgcn.workitem.id.x()5122 %a.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %a.ptr, i32 %tid5123 %b.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %b.ptr, i32 %tid5124 %out.gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid5125 %a = load <2 x i16>, ptr addrspace(1) %a.gep5126 %b = load <2 x i16>, ptr addrspace(1) %b.gep5127 %cmp = icmp ule <2 x i16> %a, %b5128 %val = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b5129 store <2 x i16> %val, ptr addrspace(1) %out.gep5130 ret void5131}5132 5133declare i32 @llvm.amdgcn.workitem.id.x() #15134 5135attributes #0 = { nounwind }5136attributes #1 = { nounwind readnone }5137