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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s5; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9,GFX950 %s6; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s7; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s8; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s9; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s10; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s11 12define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) {13; GFX7-LABEL: v_minimumnum_bf16:14; GFX7:       ; %bb.0:15; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)16; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v017; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v118; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v119; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v020; GFX7-NEXT:    v_min_f32_e32 v0, v0, v121; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v022; GFX7-NEXT:    s_setpc_b64 s[30:31]23;24; GFX8-LABEL: v_minimumnum_bf16:25; GFX8:       ; %bb.0:26; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v028; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v2, v229; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v130; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc31; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v2, v232; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc33; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v134; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v035; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v236; GFX8-NEXT:    s_movk_i32 s4, 0x800037; GFX8-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc38; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v039; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc40; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v141; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc42; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v243; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v144; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc45; GFX8-NEXT:    s_setpc_b64 s[30:31]46;47; GFX900-LABEL: v_minimumnum_bf16:48; GFX900:       ; %bb.0:49; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v051; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v2, v252; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v153; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc54; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v355; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc56; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v057; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v158; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v2, v359; GFX900-NEXT:    s_movk_i32 s4, 0x800060; GFX900-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc61; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v062; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc63; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v164; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc65; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v266; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v167; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc68; GFX900-NEXT:    s_setpc_b64 s[30:31]69;70; GFX950-LABEL: v_minimumnum_bf16:71; GFX950:       ; %bb.0:72; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)73; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v074; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v2, v275; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v176; GFX950-NEXT:    s_movk_i32 s0, 0x800077; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc78; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v379; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v080; GFX950-NEXT:    s_nop 081; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc82; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v183; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v2, v384; GFX950-NEXT:    s_nop 185; GFX950-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc86; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v087; GFX950-NEXT:    s_nop 188; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc89; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v190; GFX950-NEXT:    s_nop 191; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc92; GFX950-NEXT:    v_lshlrev_b32_e32 v1, 16, v293; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v194; GFX950-NEXT:    s_nop 195; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc96; GFX950-NEXT:    s_setpc_b64 s[30:31]97;98; GFX10-LABEL: v_minimumnum_bf16:99; GFX10:       ; %bb.0:100; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)101; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v0102; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v1103; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2104; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo105; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3106; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v0107; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo108; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v1109; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3110; GFX10-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo111; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0112; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v2113; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo114; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1115; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo116; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3117; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo118; GFX10-NEXT:    s_setpc_b64 s[30:31]119;120; GFX11-TRUE16-LABEL: v_minimumnum_bf16:121; GFX11-TRUE16:       ; %bb.0:122; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0124; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l125; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l126; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)127; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2128; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l129; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l130; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo131; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)132; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2133; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.h134; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo135; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)136; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v1, v2137; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo138; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h139; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v1.h, s0140; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)141; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo142; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l143; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2144; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)145; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo146; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]147;148; GFX11-FAKE16-LABEL: v_minimumnum_bf16:149; GFX11-FAKE16:       ; %bb.0:150; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0152; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)153; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2154; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo155; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1156; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0157; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)158; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3159; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo160; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1161; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)162; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3163; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo164; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v2165; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0166; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo167; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1168; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)169; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo170; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3171; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo172; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]173;174; GFX12-TRUE16-LABEL: v_minimumnum_bf16:175; GFX12-TRUE16:       ; %bb.0:176; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0177; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0178; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0179; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0180; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0181; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0182; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l183; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l184; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)185; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2186; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l187; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l188; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)189; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo190; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2191; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)192; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.h193; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)194; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo195; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v1, v2196; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)197; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo198; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h199; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)200; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)201; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v1.h, s0202; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)203; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo204; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l205; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)206; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2207; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)208; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo209; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]210;211; GFX12-FAKE16-LABEL: v_minimumnum_bf16:212; GFX12-FAKE16:       ; %bb.0:213; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0214; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0215; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0216; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0217; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0218; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0219; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)220; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2221; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)222; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo223; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1224; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v0225; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)226; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3227; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)228; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo229; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v1230; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)231; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v3232; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)233; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo234; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v2235; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0236; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)237; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo238; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1239; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)240; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)241; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo242; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3243; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)244; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo245; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]246  %result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)247  ret bfloat %result248}249 250define bfloat @v_minimumnum_bf16_nnan(bfloat %x, bfloat %y) {251; GFX7-LABEL: v_minimumnum_bf16_nnan:252; GFX7:       ; %bb.0:253; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)254; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v0255; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v1256; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1257; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0258; GFX7-NEXT:    v_min_f32_e32 v0, v0, v1259; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0260; GFX7-NEXT:    s_setpc_b64 s[30:31]261;262; GFX8-LABEL: v_minimumnum_bf16_nnan:263; GFX8:       ; %bb.0:264; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)265; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v1266; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v0267; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v2268; GFX8-NEXT:    s_movk_i32 s4, 0x8000269; GFX8-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc270; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0271; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc272; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1273; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc274; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v2275; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1276; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc277; GFX8-NEXT:    s_setpc_b64 s[30:31]278;279; GFX900-LABEL: v_minimumnum_bf16_nnan:280; GFX900:       ; %bb.0:281; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)282; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v1283; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v0284; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v2285; GFX900-NEXT:    s_movk_i32 s4, 0x8000286; GFX900-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc287; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0288; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc289; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1290; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc291; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v2292; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1293; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc294; GFX900-NEXT:    s_setpc_b64 s[30:31]295;296; GFX950-LABEL: v_minimumnum_bf16_nnan:297; GFX950:       ; %bb.0:298; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)299; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v1300; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v0301; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v2302; GFX950-NEXT:    s_movk_i32 s0, 0x8000303; GFX950-NEXT:    s_nop 0304; GFX950-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc305; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v0306; GFX950-NEXT:    s_nop 1307; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc308; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1309; GFX950-NEXT:    s_nop 1310; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc311; GFX950-NEXT:    v_lshlrev_b32_e32 v1, 16, v2312; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1313; GFX950-NEXT:    s_nop 1314; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc315; GFX950-NEXT:    s_setpc_b64 s[30:31]316;317; GFX10-LABEL: v_minimumnum_bf16_nnan:318; GFX10:       ; %bb.0:319; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)320; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v1321; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v0322; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2323; GFX10-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo324; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0325; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v2326; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo327; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1328; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo329; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3330; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo331; GFX10-NEXT:    s_setpc_b64 s[30:31]332;333; GFX11-TRUE16-LABEL: v_minimumnum_bf16_nnan:334; GFX11-TRUE16:       ; %bb.0:335; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)336; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0337; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l338; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l339; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v0.l340; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)341; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l342; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2343; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo344; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l345; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)346; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, s0347; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo348; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2349; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)350; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo351; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]352;353; GFX11-FAKE16-LABEL: v_minimumnum_bf16_nnan:354; GFX11-FAKE16:       ; %bb.0:355; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)356; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1357; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0358; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)359; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2360; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo361; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0362; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2363; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1364; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)365; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo366; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3367; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)368; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo369; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]370;371; GFX12-TRUE16-LABEL: v_minimumnum_bf16_nnan:372; GFX12-TRUE16:       ; %bb.0:373; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0374; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0375; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0376; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0377; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0378; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0379; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l380; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v0.l381; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v0.l382; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)383; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v2.l384; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2385; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)386; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v1.l, v0.l, vcc_lo387; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l388; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)389; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)390; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, s0391; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)392; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo393; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2394; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)395; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)396; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v0.l, vcc_lo397; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]398;399; GFX12-FAKE16-LABEL: v_minimumnum_bf16_nnan:400; GFX12-FAKE16:       ; %bb.0:401; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0402; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0403; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0404; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0405; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0406; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1407; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0408; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)409; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2410; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)411; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo412; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0413; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)414; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v2, v0 :: v_dual_lshlrev_b32 v3, 16, v2415; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1416; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)417; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)418; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo419; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3420; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)421; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)422; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo423; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]424  %result = call nnan bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)425  ret bfloat %result426}427 428 429define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) {430; GFX7-LABEL: v_minimumnum_v2bf16:431; GFX7:       ; %bb.0:432; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)433; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v0434; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v2435; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v1436; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v3437; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3438; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1439; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2440; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0441; GFX7-NEXT:    v_min_f32_e32 v1, v1, v3442; GFX7-NEXT:    v_min_f32_e32 v0, v0, v2443; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0444; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1445; GFX7-NEXT:    s_setpc_b64 s[30:31]446;447; GFX8-LABEL: v_minimumnum_v2bf16:448; GFX8:       ; %bb.0:449; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)450; GFX8-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0451; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2452; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v1453; GFX8-NEXT:    v_and_b32_e32 v5, 0xffff0000, v1454; GFX8-NEXT:    v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD455; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v5456; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc457; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v3458; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v2459; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v5460; GFX8-NEXT:    s_movk_i32 s4, 0x8000461; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc462; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v3463; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc464; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2465; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc466; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v4467; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3468; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v0469; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc470; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3471; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v1472; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc473; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3474; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc475; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v1476; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v0477; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v3478; GFX8-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc479; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0480; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc481; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1482; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc483; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v3484; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1485; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2486; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc487; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD488; GFX8-NEXT:    s_setpc_b64 s[30:31]489;490; GFX900-LABEL: v_minimumnum_v2bf16:491; GFX900:       ; %bb.0:492; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)493; GFX900-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0494; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2495; GFX900-NEXT:    v_lshrrev_b32_e32 v2, 16, v1496; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v1497; GFX900-NEXT:    v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD498; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v5499; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc500; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v3501; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v2502; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v5503; GFX900-NEXT:    s_movk_i32 s4, 0x8000504; GFX900-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc505; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v3506; GFX900-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc507; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2508; GFX900-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc509; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v4510; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3511; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v0512; GFX900-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc513; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3514; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v1515; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc516; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3517; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc518; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v1519; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v0520; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v3521; GFX900-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc522; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0523; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc524; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1525; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc526; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v3527; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1528; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc529; GFX900-NEXT:    s_mov_b32 s4, 0x5040100530; GFX900-NEXT:    v_perm_b32 v0, v2, v0, s4531; GFX900-NEXT:    s_setpc_b64 s[30:31]532;533; GFX950-LABEL: v_minimumnum_v2bf16:534; GFX950:       ; %bb.0:535; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)536; GFX950-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0537; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v2, v2538; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 16, v1539; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v1540; GFX950-NEXT:    v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD541; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v5542; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v3543; GFX950-NEXT:    s_movk_i32 s0, 0x8000544; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc545; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v2546; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v5547; GFX950-NEXT:    s_nop 1548; GFX950-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc549; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3550; GFX950-NEXT:    s_nop 1551; GFX950-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc552; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2553; GFX950-NEXT:    s_nop 1554; GFX950-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc555; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v4556; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3557; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v0558; GFX950-NEXT:    s_nop 0559; GFX950-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc560; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3561; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v1562; GFX950-NEXT:    s_nop 0563; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc564; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v3565; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v0566; GFX950-NEXT:    s_nop 0567; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc568; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v1569; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v3570; GFX950-NEXT:    s_nop 1571; GFX950-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc572; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v0573; GFX950-NEXT:    s_nop 1574; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc575; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1576; GFX950-NEXT:    s_mov_b32 s0, 0x5040100577; GFX950-NEXT:    s_nop 0578; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc579; GFX950-NEXT:    v_lshlrev_b32_e32 v1, 16, v3580; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1581; GFX950-NEXT:    s_nop 1582; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc583; GFX950-NEXT:    v_perm_b32 v0, v2, v0, s0584; GFX950-NEXT:    s_setpc_b64 s[30:31]585;586; GFX10-LABEL: v_minimumnum_v2bf16:587; GFX10:       ; %bb.0:588; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)589; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0590; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v0591; GFX10-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1592; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v1593; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2594; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v1595; GFX10-NEXT:    v_cndmask_b32_sdwa v6, v0, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD596; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4597; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo598; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3599; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v6600; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo601; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5602; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v0603; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v2604; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo605; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v4606; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v1607; GFX10-NEXT:    v_cndmask_b32_e32 v3, v2, v6, vcc_lo608; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v7609; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v3610; GFX10-NEXT:    v_cndmask_b32_e32 v4, v1, v0, vcc_lo611; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6612; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v6, vcc_lo613; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0614; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v4615; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo616; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2617; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc_lo618; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1619; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo620; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7621; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc_lo622; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6623; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo624; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100625; GFX10-NEXT:    s_setpc_b64 s[30:31]626;627; GFX11-TRUE16-LABEL: v_minimumnum_v2bf16:628; GFX11-TRUE16:       ; %bb.0:629; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)630; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0631; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1632; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0633; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v1634; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)635; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2636; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v3, v3637; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)638; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l639; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0640; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v5, v5641; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo642; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v1.h, v4.h, s0643; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h644; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)645; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v2646; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo647; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3648; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.l649; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v4.h, s0650; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l651; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo652; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)653; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4654; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v1.l, v3.h, s1655; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v3.h656; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)657; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v3, v4658; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v4.h, v3.h, s0659; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h660; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)661; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, v3.h, s1662; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v2.h663; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v4.h, s0664; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v0.l665; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)666; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, s1667; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v4668; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)669; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo670; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s0671; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]672;673; GFX11-FAKE16-LABEL: v_minimumnum_v2bf16:674; GFX11-FAKE16:       ; %bb.0:675; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)676; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0677; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1678; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0679; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)680; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2681; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0682; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1683; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)684; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5685; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo686; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6687; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v2, vcc_lo688; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)689; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v3690; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1691; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4692; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2693; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)694; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v5695; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1696; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v0697; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)698; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v7699; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v4700; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v1, v0, vcc_lo701; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2702; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)703; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5704; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0705; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo706; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3707; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo708; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1709; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)710; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo711; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6712; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc_lo713; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7714; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)715; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo716; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100717; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]718;719; GFX12-TRUE16-LABEL: v_minimumnum_v2bf16:720; GFX12-TRUE16:       ; %bb.0:721; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x0722; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x0723; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0724; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x0725; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x0726; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0727; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1728; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0729; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v1730; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)731; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2732; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v3, v3733; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)734; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l735; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0736; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v5, v5737; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)738; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo739; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)740; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)741; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v1.h, v4.h, s0742; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h743; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v2744; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)745; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo746; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v3747; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.l748; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)749; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)750; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v4.h, s0751; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l752; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)753; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo754; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4755; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)756; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v1.l, v3.h, s1757; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v3.h758; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v3, v4759; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)760; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)761; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v4.h, v3.h, s0762; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h763; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, v3.h, s1764; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v2.h765; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)766; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)767; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v4.h, s0768; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v0.l769; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, s1770; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)771; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v4772; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)773; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo774; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)775; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)776; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s0777; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]778;779; GFX12-FAKE16-LABEL: v_minimumnum_v2bf16:780; GFX12-FAKE16:       ; %bb.0:781; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x0782; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x0783; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0784; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x0785; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x0786; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v0787; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1788; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v0789; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)790; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v2791; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)792; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v0793; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v1794; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)795; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v5796; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)797; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo798; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v6799; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)800; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v2, vcc_lo801; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)802; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v3803; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v1804; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v4805; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)806; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v2807; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)808; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v5809; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)810; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v1811; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v0812; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)813; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v7814; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v4815; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)816; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v1, v0, vcc_lo817; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2818; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)819; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)820; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v5821; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0822; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)823; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo824; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3825; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)826; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo827; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1828; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)829; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo830; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6831; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)832; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc_lo833; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7834; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)835; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo836; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)837; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100838; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]839  %result = call <2 x bfloat> @llvm.minimumnum.v2bf16(<2 x bfloat> %x, <2 x bfloat> %y)840  ret <2 x bfloat> %result841}842 843define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y) {844; GFX7-LABEL: v_minimumnum_v2bf16_nnan:845; GFX7:       ; %bb.0:846; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)847; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v0848; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v2849; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v1850; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v3851; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v3852; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1853; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v2854; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0855; GFX7-NEXT:    v_min_f32_e32 v1, v1, v3856; GFX7-NEXT:    v_min_f32_e32 v0, v0, v2857; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v0858; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v1859; GFX7-NEXT:    s_setpc_b64 s[30:31]860;861; GFX8-LABEL: v_minimumnum_v2bf16_nnan:862; GFX8:       ; %bb.0:863; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)864; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v1865; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v0866; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v2867; GFX8-NEXT:    s_movk_i32 s4, 0x8000868; GFX8-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc869; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0870; GFX8-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc871; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1872; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v2873; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc874; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4875; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc876; GFX8-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1877; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0878; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 16, v0879; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v1880; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v3881; GFX8-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc882; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0883; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc884; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1885; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc886; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v3887; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1888; GFX8-NEXT:    v_cndmask_b32_sdwa v0, v3, v0, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD889; GFX8-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD890; GFX8-NEXT:    s_setpc_b64 s[30:31]891;892; GFX900-LABEL: v_minimumnum_v2bf16_nnan:893; GFX900:       ; %bb.0:894; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)895; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v1896; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v0897; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v2898; GFX900-NEXT:    s_movk_i32 s4, 0x8000899; GFX900-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc900; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0901; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc902; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1903; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v2904; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc905; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4906; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc907; GFX900-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1908; GFX900-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0909; GFX900-NEXT:    v_lshrrev_b32_e32 v0, 16, v0910; GFX900-NEXT:    v_lshrrev_b32_e32 v1, 16, v1911; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v3912; GFX900-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc913; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v0914; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc915; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1916; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc917; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v3918; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1919; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc920; GFX900-NEXT:    s_mov_b32 s4, 0x5040100921; GFX900-NEXT:    v_perm_b32 v0, v0, v2, s4922; GFX900-NEXT:    s_setpc_b64 s[30:31]923;924; GFX950-LABEL: v_minimumnum_v2bf16_nnan:925; GFX950:       ; %bb.0:926; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)927; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v1928; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v0929; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v2930; GFX950-NEXT:    s_movk_i32 s0, 0x8000931; GFX950-NEXT:    s_nop 0932; GFX950-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc933; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v0934; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v2935; GFX950-NEXT:    s_nop 0936; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc937; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1938; GFX950-NEXT:    s_nop 1939; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc940; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4941; GFX950-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0942; GFX950-NEXT:    v_lshrrev_b32_e32 v0, 16, v0943; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc944; GFX950-NEXT:    v_and_b32_e32 v3, 0xffff0000, v1945; GFX950-NEXT:    v_lshrrev_b32_e32 v1, 16, v1946; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v3947; GFX950-NEXT:    s_nop 1948; GFX950-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc949; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v0950; GFX950-NEXT:    s_nop 1951; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc952; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1953; GFX950-NEXT:    s_mov_b32 s0, 0x5040100954; GFX950-NEXT:    s_nop 0955; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc956; GFX950-NEXT:    v_lshlrev_b32_e32 v1, 16, v3957; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1958; GFX950-NEXT:    s_nop 1959; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc960; GFX950-NEXT:    v_perm_b32 v0, v0, v2, s0961; GFX950-NEXT:    s_setpc_b64 s[30:31]962;963; GFX10-LABEL: v_minimumnum_v2bf16_nnan:964; GFX10:       ; %bb.0:965; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)966; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v1967; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v0968; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v1969; GFX10-NEXT:    v_and_b32_e32 v5, 0xffff0000, v0970; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v0971; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v1972; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v2973; GFX10-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo974; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v4975; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v2976; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v6, vcc_lo977; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0978; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo979; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6980; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v6, vcc_lo981; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1982; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v3983; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo984; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7985; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v7, vcc_lo986; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4987; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo988; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6989; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo990; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100991; GFX10-NEXT:    s_setpc_b64 s[30:31]992;993; GFX11-TRUE16-LABEL: v_minimumnum_v2bf16_nnan:994; GFX11-TRUE16:       ; %bb.0:995; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)996; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v1997; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v0998; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v0.l999; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v11000; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01001; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.h1002; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v21003; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 01004; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo1005; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l1006; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)1007; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v3.h, v0.l, s01008; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v31009; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)1010; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo1011; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41012; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.h, v0.l, s01013; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v1.h, v0.h, vcc_lo1014; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.h1015; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1016; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, v0.h, s11017; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo1018; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v31019; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1020; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo1021; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1022;1023; GFX11-FAKE16-LABEL: v_minimumnum_v2bf16_nnan:1024; GFX11-FAKE16:       ; %bb.0:1025; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1026; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v01027; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v01028; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v11029; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v11030; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v11031; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01032; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)1033; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v21034; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo1035; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41036; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)1037; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v21038; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v7, v6, vcc_lo1039; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01040; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1041; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v61042; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v3, v6, vcc_lo1043; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11044; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v31045; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo1046; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71047; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v5, v7, vcc_lo1048; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v41049; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)1050; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1051; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v61052; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1053; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1054; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x50401001055; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1056;1057; GFX12-TRUE16-LABEL: v_minimumnum_v2bf16_nnan:1058; GFX12-TRUE16:       ; %bb.0:1059; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01060; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01061; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01062; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01063; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01064; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v11065; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v01066; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v0.l1067; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v11068; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01069; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.h1070; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v21071; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 01072; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1073; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v1.l, v0.l, vcc_lo1074; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l1075; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1076; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)1077; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v3.h, v0.l, s01078; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v31079; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1080; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo1081; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41082; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1083; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)1084; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.h, v0.l, s01085; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1086; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v1.h, v0.h, vcc_lo1087; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.h1088; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, v0.h, s11089; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1090; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)1091; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v1.h, vcc_lo1092; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v31093; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1094; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo1095; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1096;1097; GFX12-FAKE16-LABEL: v_minimumnum_v2bf16_nnan:1098; GFX12-FAKE16:       ; %bb.0:1099; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01100; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01101; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01102; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01103; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01104; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v01105; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v01106; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v11107; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v11108; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v11109; GFX12-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01110; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)1111; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v21112; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1113; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo1114; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41115; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1116; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v21117; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1118; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v7, v6, vcc_lo1119; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01120; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1121; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1122; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v61123; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1124; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v3, v6, vcc_lo1125; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11126; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v31127; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1128; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo1129; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v71130; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1131; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v5, v7, vcc_lo1132; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v41133; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1134; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo1135; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v61136; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1137; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo1138; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1139; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x50401001140; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1141  %result = call nnan <2 x bfloat> @llvm.minimumnum.v2bf16(<2 x bfloat> %x, <2 x bfloat> %y)1142  ret <2 x bfloat> %result1143}1144 1145define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) {1146; GFX7-LABEL: v_minimumnum_v3bf16:1147; GFX7:       ; %bb.0:1148; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1149; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v01150; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v31151; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v11152; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v41153; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v21154; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v51155; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v51156; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v21157; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v41158; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v11159; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v31160; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01161; GFX7-NEXT:    v_min_f32_e32 v2, v2, v51162; GFX7-NEXT:    v_min_f32_e32 v1, v1, v41163; GFX7-NEXT:    v_min_f32_e32 v0, v0, v31164; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v21165; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01166; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v11167; GFX7-NEXT:    s_setpc_b64 s[30:31]1168;1169; GFX8-LABEL: v_minimumnum_v3bf16:1170; GFX8:       ; %bb.0:1171; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1172; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01173; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v4, v41174; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v21175; GFX8-NEXT:    v_and_b32_e32 v7, 0xffff0000, v21176; GFX8-NEXT:    v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1177; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v71178; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1179; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v51180; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v41181; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v71182; GFX8-NEXT:    s_movk_i32 s4, 0x80001183; GFX8-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc1184; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v51185; GFX8-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc1186; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v41187; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc1188; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v61189; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v51190; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v11191; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc1192; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v51193; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v31194; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1195; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v51196; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc1197; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v31198; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v11199; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v51200; GFX8-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc1201; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v11202; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1203; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v31204; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1205; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v51206; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v31207; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v01208; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1209; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v31210; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v21211; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1212; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v31213; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc1214; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v21215; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v01216; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v31217; GFX8-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc1218; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v01219; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc1220; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v21221; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1222; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v31223; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v21224; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc1225; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v41226; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1227; GFX8-NEXT:    s_setpc_b64 s[30:31]1228;1229; GFX900-LABEL: v_minimumnum_v3bf16:1230; GFX900:       ; %bb.0:1231; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1232; GFX900-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01233; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v4, v41234; GFX900-NEXT:    v_lshrrev_b32_e32 v4, 16, v21235; GFX900-NEXT:    v_and_b32_e32 v7, 0xffff0000, v21236; GFX900-NEXT:    v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1237; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v71238; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1239; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v51240; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v41241; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v71242; GFX900-NEXT:    s_movk_i32 s4, 0x80001243; GFX900-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc1244; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v51245; GFX900-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc1246; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v41247; GFX900-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc1248; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v61249; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v51250; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v11251; GFX900-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc1252; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v51253; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v31254; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1255; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v51256; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc1257; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v31258; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v11259; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v51260; GFX900-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc1261; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v11262; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1263; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v31264; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1265; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v51266; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v31267; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v01268; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1269; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v31270; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v21271; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1272; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v31273; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc1274; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v21275; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v01276; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v31277; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc1278; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v01279; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc1280; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v21281; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1282; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v31283; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v21284; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc1285; GFX900-NEXT:    s_mov_b32 s4, 0x50401001286; GFX900-NEXT:    v_perm_b32 v0, v4, v0, s41287; GFX900-NEXT:    s_setpc_b64 s[30:31]1288;1289; GFX950-LABEL: v_minimumnum_v3bf16:1290; GFX950:       ; %bb.0:1291; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1292; GFX950-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01293; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v4, v41294; GFX950-NEXT:    v_lshrrev_b32_e32 v4, 16, v21295; GFX950-NEXT:    v_and_b32_e32 v7, 0xffff0000, v21296; GFX950-NEXT:    v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1297; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v71298; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v51299; GFX950-NEXT:    s_movk_i32 s0, 0x80001300; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc1301; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v41302; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v71303; GFX950-NEXT:    s_nop 11304; GFX950-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc1305; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v51306; GFX950-NEXT:    s_nop 11307; GFX950-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc1308; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v41309; GFX950-NEXT:    s_nop 11310; GFX950-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc1311; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v61312; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v51313; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v11314; GFX950-NEXT:    s_nop 01315; GFX950-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc1316; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v51317; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v31318; GFX950-NEXT:    s_nop 01319; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1320; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v51321; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v11322; GFX950-NEXT:    s_nop 01323; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc1324; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v31325; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v51326; GFX950-NEXT:    s_nop 11327; GFX950-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc1328; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v11329; GFX950-NEXT:    s_nop 11330; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1331; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v31332; GFX950-NEXT:    s_nop 11333; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1334; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v51335; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v31336; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v01337; GFX950-NEXT:    s_nop 01338; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc1339; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v31340; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v21341; GFX950-NEXT:    s_nop 01342; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1343; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v31344; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v01345; GFX950-NEXT:    s_nop 01346; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc1347; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v21348; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v31349; GFX950-NEXT:    s_nop 11350; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc1351; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v01352; GFX950-NEXT:    s_nop 11353; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc1354; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v21355; GFX950-NEXT:    s_mov_b32 s0, 0x50401001356; GFX950-NEXT:    s_nop 01357; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1358; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v31359; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v21360; GFX950-NEXT:    s_nop 11361; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc1362; GFX950-NEXT:    v_perm_b32 v0, v4, v0, s01363; GFX950-NEXT:    s_setpc_b64 s[30:31]1364;1365; GFX10-LABEL: v_minimumnum_v3bf16:1366; GFX10:       ; %bb.0:1367; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1368; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01369; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v21370; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v01371; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v21372; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v21373; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v41374; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v11375; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v31376; GFX10-NEXT:    v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1377; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v81378; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1379; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v41380; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1381; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v61382; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v10, vcc_lo1383; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v91384; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v101385; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v11386; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v41387; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo1388; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v71389; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v01390; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v21391; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo1392; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v61393; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v31394; GFX10-NEXT:    v_cndmask_b32_e32 v5, v4, v10, vcc_lo1395; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v81396; GFX10-NEXT:    v_cndmask_b32_e32 v6, v2, v0, vcc_lo1397; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v111398; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v51399; GFX10-NEXT:    v_cndmask_b32_e32 v7, v3, v1, vcc_lo1400; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v101401; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v10, vcc_lo1402; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01403; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo1404; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v41405; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc_lo1406; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21407; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v61408; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1409; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v91410; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v4, vcc_lo1411; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11412; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v71413; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo1414; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v81415; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo1416; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v31417; GFX10-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001418; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1419; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v41420; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo1421; GFX10-NEXT:    s_setpc_b64 s[30:31]1422;1423; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16:1424; GFX11-TRUE16:       ; %bb.0:1425; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1426; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01427; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v21428; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 01429; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v31430; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1431; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v41432; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v51433; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)1434; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v6.l1435; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v11436; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v7, v71437; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo1438; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v21439; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.h, v6.h, s01440; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h1441; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1442; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v7, v71443; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v41444; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo1445; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v51446; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l1447; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)1448; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v6.h, s01449; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l1450; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo1451; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v61452; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1453; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v5.h, s11454; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v5.h1455; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v01456; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v5, v61457; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1458; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v5.h, s01459; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h1460; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v5.h, s11461; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v3, v31462; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1463; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s01464; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l1465; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s11466; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l1467; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1468; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v61469; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s21470; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v0.h1471; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1472; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s01473; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v0, v61474; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1475; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s11476; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v6.h1477; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s21478; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v4.h1479; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1480; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s11481; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l1482; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v4.h, s21483; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1484; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v61485; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo1486; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1487; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s11488; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1489;1490; GFX11-FAKE16-LABEL: v_minimumnum_v3bf16:1491; GFX11-FAKE16:       ; %bb.0:1492; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1493; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01494; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v21495; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v01496; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v01497; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)1498; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v41499; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v21500; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)1501; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v71502; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v11503; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v81504; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v31505; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v21506; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)1507; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v61508; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1509; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v71510; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v41511; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo1512; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v51513; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)1514; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v101515; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v4, vcc_lo1516; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v91517; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v11518; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v61519; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v41520; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v21521; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo1522; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51523; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1524; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v01525; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v81526; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v31527; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc_lo1528; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v101529; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo1530; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01531; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)1532; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo1533; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v71534; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v51535; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc_lo1536; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21537; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1538; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11539; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)1540; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v61541; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v71542; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo1543; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v31544; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)1545; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x50401001546; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1547; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v21548; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc_lo1549; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1550;1551; GFX12-TRUE16-LABEL: v_minimumnum_v3bf16:1552; GFX12-TRUE16:       ; %bb.0:1553; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x01554; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x01555; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x01556; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x01557; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x01558; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01559; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v21560; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 01561; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v31562; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)1563; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v41564; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v51565; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)1566; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v6.l1567; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v11568; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v7, v71569; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1570; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo1571; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v21572; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1573; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1574; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.h, v6.h, s01575; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h1576; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v7, v71577; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)1578; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v41579; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1580; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo1581; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v51582; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l1583; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1584; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)1585; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v6.h, s01586; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l1587; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1588; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo1589; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v61590; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1591; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v5.h, s11592; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v5.h1593; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v01594; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v5, v61595; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1596; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1597; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v5.h, s01598; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h1599; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v5.h, s11600; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v3, v31601; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1602; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1603; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s01604; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l1605; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s11606; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l1607; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1608; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v61609; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s21610; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v0.h1611; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1612; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)1613; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s01614; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v0, v61615; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1616; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1617; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s11618; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v6.h1619; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s21620; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v4.h1621; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1622; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1623; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s11624; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l1625; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v4.h, s21626; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)1627; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v61628; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)1629; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo1630; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)1631; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1632; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s11633; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]1634;1635; GFX12-FAKE16-LABEL: v_minimumnum_v3bf16:1636; GFX12-FAKE16:       ; %bb.0:1637; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x01638; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x01639; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x01640; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x01641; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x01642; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01643; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v21644; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v01645; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v01646; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)1647; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v41648; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1649; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v21650; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)1651; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v71652; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1653; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v11654; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v81655; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1656; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v31657; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v21658; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v61659; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1660; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1661; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)1662; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v71663; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v41664; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1665; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo1666; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v51667; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v101668; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1669; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v4, vcc_lo1670; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v91671; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v11672; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1673; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)1674; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v61675; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v41676; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v21677; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1678; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo1679; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v51680; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1681; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1682; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v01683; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v81684; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v31685; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1686; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc_lo1687; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v101688; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1689; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo1690; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01691; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1692; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo1693; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v71694; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v51695; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1696; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc_lo1697; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21698; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1699; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1700; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11701; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1702; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v61703; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v71704; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1705; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo1706; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v31707; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)1708; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x50401001709; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1710; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1711; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v21712; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)1713; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc_lo1714; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]1715  %result = call <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)1716  ret <3 x bfloat> %result1717}1718 1719define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y) {1720; GFX7-LABEL: v_minimumnum_v3bf16_nnan:1721; GFX7:       ; %bb.0:1722; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1723; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v01724; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v31725; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v11726; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v41727; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v21728; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v51729; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v51730; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v21731; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v41732; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v11733; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v31734; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01735; GFX7-NEXT:    v_min_f32_e32 v2, v2, v51736; GFX7-NEXT:    v_min_f32_e32 v1, v1, v41737; GFX7-NEXT:    v_min_f32_e32 v0, v0, v31738; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v21739; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01740; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v11741; GFX7-NEXT:    s_setpc_b64 s[30:31]1742;1743; GFX8-LABEL: v_minimumnum_v3bf16_nnan:1744; GFX8:       ; %bb.0:1745; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1746; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v31747; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v11748; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v41749; GFX8-NEXT:    s_movk_i32 s4, 0x80001750; GFX8-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc1751; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v11752; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1753; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v31754; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1755; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v41756; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v31757; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1758; GFX8-NEXT:    v_and_b32_e32 v3, 0xffff0000, v21759; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v01760; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 16, v01761; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v21762; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v31763; GFX8-NEXT:    v_cndmask_b32_e32 v3, v6, v5, vcc1764; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v51765; GFX8-NEXT:    v_cndmask_b32_e32 v4, v3, v5, vcc1766; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v61767; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v31768; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc1769; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v51770; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1771; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v21772; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v01773; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v41774; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc1775; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v01776; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc1777; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v21778; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1779; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v41780; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v21781; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc1782; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v31783; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD1784; GFX8-NEXT:    s_setpc_b64 s[30:31]1785;1786; GFX900-LABEL: v_minimumnum_v3bf16_nnan:1787; GFX900:       ; %bb.0:1788; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1789; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v31790; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v11791; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v41792; GFX900-NEXT:    s_movk_i32 s4, 0x80001793; GFX900-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc1794; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v11795; GFX900-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1796; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v31797; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1798; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v41799; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v31800; GFX900-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1801; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v21802; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v01803; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v31804; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc1805; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v01806; GFX900-NEXT:    v_cndmask_b32_e32 v4, v3, v0, vcc1807; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v21808; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v31809; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc1810; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v51811; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1812; GFX900-NEXT:    v_and_b32_e32 v4, 0xffff0000, v21813; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01814; GFX900-NEXT:    v_lshrrev_b32_e32 v0, 16, v01815; GFX900-NEXT:    v_lshrrev_b32_e32 v2, 16, v21816; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v41817; GFX900-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc1818; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v01819; GFX900-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc1820; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v21821; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1822; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v41823; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v21824; GFX900-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc1825; GFX900-NEXT:    s_mov_b32 s4, 0x50401001826; GFX900-NEXT:    v_perm_b32 v0, v0, v3, s41827; GFX900-NEXT:    s_setpc_b64 s[30:31]1828;1829; GFX950-LABEL: v_minimumnum_v3bf16_nnan:1830; GFX950:       ; %bb.0:1831; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1832; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v31833; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v11834; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v41835; GFX950-NEXT:    s_movk_i32 s0, 0x80001836; GFX950-NEXT:    s_nop 01837; GFX950-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc1838; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v11839; GFX950-NEXT:    s_nop 11840; GFX950-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1841; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v31842; GFX950-NEXT:    s_nop 11843; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1844; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v41845; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v31846; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v21847; GFX950-NEXT:    s_nop 01848; GFX950-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc1849; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v01850; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v31851; GFX950-NEXT:    s_nop 11852; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc1853; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v01854; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v31855; GFX950-NEXT:    s_nop 01856; GFX950-NEXT:    v_cndmask_b32_e32 v4, v3, v0, vcc1857; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v21858; GFX950-NEXT:    s_nop 11859; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v2, vcc1860; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v51861; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01862; GFX950-NEXT:    v_lshrrev_b32_e32 v0, 16, v01863; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1864; GFX950-NEXT:    v_and_b32_e32 v4, 0xffff0000, v21865; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 16, v21866; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v41867; GFX950-NEXT:    s_nop 11868; GFX950-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc1869; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v01870; GFX950-NEXT:    s_nop 11871; GFX950-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc1872; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v21873; GFX950-NEXT:    s_mov_b32 s0, 0x50401001874; GFX950-NEXT:    s_nop 01875; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1876; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v41877; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v21878; GFX950-NEXT:    s_nop 11879; GFX950-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc1880; GFX950-NEXT:    v_perm_b32 v0, v0, v3, s01881; GFX950-NEXT:    s_setpc_b64 s[30:31]1882;1883; GFX10-LABEL: v_minimumnum_v3bf16_nnan:1884; GFX10:       ; %bb.0:1885; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1886; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v21887; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v01888; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v31889; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v11890; GFX10-NEXT:    v_and_b32_e32 v8, 0xffff0000, v21891; GFX10-NEXT:    v_and_b32_e32 v9, 0xffff0000, v01892; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v61893; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v01894; GFX10-NEXT:    v_lshrrev_b32_e32 v11, 16, v21895; GFX10-NEXT:    v_cndmask_b32_e32 v6, v2, v0, vcc_lo1896; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41897; GFX10-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc_lo1898; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v81899; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v41900; GFX10-NEXT:    v_cndmask_b32_e32 v5, v11, v10, vcc_lo1901; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01902; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v51903; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo1904; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11905; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo1906; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v101907; GFX10-NEXT:    v_cndmask_b32_e32 v7, v5, v10, vcc_lo1908; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21909; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1910; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v61911; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v111912; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc_lo1913; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v21914; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo1915; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v81916; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v7, vcc_lo1917; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v31918; GFX10-NEXT:    v_perm_b32 v0, v2, v0, 0x50401001919; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1920; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v91921; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo1922; GFX10-NEXT:    s_setpc_b64 s[30:31]1923;1924; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16_nnan:1925; GFX11-TRUE16:       ; %bb.0:1926; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1927; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v31928; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v11929; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.l1930; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v01931; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.l1932; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)1933; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41934; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 01935; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v21936; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v3.l, v1.l, vcc_lo1937; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l1938; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.h, v1.l, s01939; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v41940; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)1941; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo1942; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v51943; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v21944; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v01945; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.h, v1.l, s01946; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.l, v0.l, vcc_lo1947; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l1948; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)1949; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.h, v0.l, s11950; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v41951; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.h1952; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.h, v2.l, vcc_lo1953; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v31954; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)1955; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v4.h, v0.l, s01956; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.h, v0.h, vcc_lo1957; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h1958; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v0.h, s11959; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v41960; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1961; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo1962; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v0.h, s01963; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1964;1965; GFX11-FAKE16-LABEL: v_minimumnum_v3bf16_nnan:1966; GFX11-FAKE16:       ; %bb.0:1967; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1968; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v21969; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v01970; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v01971; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v21972; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v31973; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v21974; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v61975; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v11976; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v01977; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v2, v0, vcc_lo1978; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)1979; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v41980; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc_lo1981; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v81982; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v11, v10, vcc_lo1983; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v01984; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1985; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v51986; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo1987; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11988; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo1989; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v101990; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v5, v10, vcc_lo1991; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v21992; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1993; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v61994; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v111995; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc_lo1996; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)1997; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v21998; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo1999; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v82000; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v5, v7 :: v_dual_lshlrev_b32 v9, 16, v42001; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32002; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2003; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2004; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v92005; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo2006; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401002007; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2008;2009; GFX12-TRUE16-LABEL: v_minimumnum_v3bf16_nnan:2010; GFX12-TRUE16:       ; %bb.0:2011; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02012; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x02013; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x02014; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x02015; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02016; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v32017; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v12018; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.l2019; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v02020; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.l2021; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)2022; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v42023; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 02024; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v22025; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2026; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v3.l, v1.l, vcc_lo2027; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l2028; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2029; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)2030; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.h, v1.l, s02031; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v42032; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2033; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v3.l, vcc_lo2034; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v52035; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v22036; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v02037; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2038; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.h, v1.l, s02039; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2040; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.l, v0.l, vcc_lo2041; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l2042; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)2043; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.h, v0.l, s12044; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v42045; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.h2046; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2047; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.h, v2.l, vcc_lo2048; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v32049; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2050; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)2051; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v4.h, v0.l, s02052; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2053; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.h, v0.h, vcc_lo2054; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h2055; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v0.h, s12056; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v42057; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2058; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)2059; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo2060; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2061; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v0.h, s02062; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]2063;2064; GFX12-FAKE16-LABEL: v_minimumnum_v3bf16_nnan:2065; GFX12-FAKE16:       ; %bb.0:2066; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02067; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x02068; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x02069; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x02070; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02071; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v22072; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v02073; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v02074; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v22075; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v32076; GFX12-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v22077; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v62078; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v12079; GFX12-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v02080; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2081; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v2, v0, vcc_lo2082; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2083; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v42084; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2085; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc_lo2086; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v82087; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2088; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v11, v10, vcc_lo2089; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v02090; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2091; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v52092; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2093; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo2094; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12095; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2096; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo2097; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v102098; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2099; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v5, v10, vcc_lo2100; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22101; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2102; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2103; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v62104; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v112105; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2106; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v11, vcc_lo2107; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2108; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v22109; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2110; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo2111; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v82112; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2113; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v5, v7 :: v_dual_lshlrev_b32 v9, 16, v42114; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32115; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2116; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2117; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)2118; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v92119; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2120; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo2121; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401002122; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]2123  %result = call nnan <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)2124  ret <3 x bfloat> %result2125}2126 2127define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) {2128; GFX7-LABEL: v_minimumnum_v4bf16:2129; GFX7:       ; %bb.0:2130; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2131; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v02132; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v42133; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v12134; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v52135; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v22136; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v62137; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v32138; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v72139; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v72140; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v32141; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v62142; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v22143; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v52144; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v12145; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v42146; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02147; GFX7-NEXT:    v_min_f32_e32 v3, v3, v72148; GFX7-NEXT:    v_min_f32_e32 v2, v2, v62149; GFX7-NEXT:    v_min_f32_e32 v1, v1, v52150; GFX7-NEXT:    v_min_f32_e32 v0, v0, v42151; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02152; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v12153; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v22154; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v32155; GFX7-NEXT:    s_setpc_b64 s[30:31]2156;2157; GFX8-LABEL: v_minimumnum_v4bf16:2158; GFX8:       ; %bb.0:2159; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2160; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12161; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v4, v42162; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v32163; GFX8-NEXT:    v_and_b32_e32 v7, 0xffff0000, v32164; GFX8-NEXT:    v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2165; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v72166; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc2167; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v52168; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v42169; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v72170; GFX8-NEXT:    s_movk_i32 s4, 0x80002171; GFX8-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc2172; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v52173; GFX8-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc2174; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v42175; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc2176; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v62177; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v52178; GFX8-NEXT:    v_and_b32_e32 v5, 0xffff0000, v02179; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc2180; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v22181; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v02182; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v52183; GFX8-NEXT:    v_and_b32_e32 v8, 0xffff0000, v22184; GFX8-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc2185; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v8, v82186; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc2187; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v52188; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v62189; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v82190; GFX8-NEXT:    v_cndmask_b32_e32 v7, v6, v5, vcc2191; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v52192; GFX8-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc2193; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v62194; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc2195; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v72196; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v62197; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v12198; GFX8-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc2199; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v62200; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v32201; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2202; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v62203; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc2204; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v32205; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v12206; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v62207; GFX8-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc2208; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v12209; GFX8-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc2210; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v32211; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2212; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v62213; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32214; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v02215; GFX8-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc2216; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v32217; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v22218; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2219; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v32220; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc2221; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v22222; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v02223; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v32224; GFX8-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc2225; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v02226; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc2227; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v22228; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2229; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v32230; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v22231; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc2232; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v52233; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2234; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v42235; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2236; GFX8-NEXT:    s_setpc_b64 s[30:31]2237;2238; GFX900-LABEL: v_minimumnum_v4bf16:2239; GFX900:       ; %bb.0:2240; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2241; GFX900-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12242; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v4, v42243; GFX900-NEXT:    v_lshrrev_b32_e32 v4, 16, v32244; GFX900-NEXT:    v_and_b32_e32 v7, 0xffff0000, v32245; GFX900-NEXT:    v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2246; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v72247; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc2248; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v52249; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v42250; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v72251; GFX900-NEXT:    s_movk_i32 s4, 0x80002252; GFX900-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc2253; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v52254; GFX900-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc2255; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v42256; GFX900-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc2257; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v62258; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v52259; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v02260; GFX900-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc2261; GFX900-NEXT:    v_lshrrev_b32_e32 v6, 16, v22262; GFX900-NEXT:    v_lshrrev_b32_e32 v7, 16, v02263; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v52264; GFX900-NEXT:    v_and_b32_e32 v8, 0xffff0000, v22265; GFX900-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc2266; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v8, v82267; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc2268; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v52269; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 16, v62270; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v82271; GFX900-NEXT:    v_cndmask_b32_e32 v7, v6, v5, vcc2272; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v52273; GFX900-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc2274; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v62275; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc2276; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v72277; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v62278; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v12279; GFX900-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc2280; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v62281; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v32282; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2283; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v62284; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc2285; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v32286; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v12287; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v62288; GFX900-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc2289; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v12290; GFX900-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc2291; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v32292; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2293; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v62294; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32295; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v02296; GFX900-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc2297; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v32298; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v22299; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2300; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v32301; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc2302; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v22303; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v02304; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v32305; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc2306; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v02307; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc2308; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v22309; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2310; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v32311; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v22312; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc2313; GFX900-NEXT:    s_mov_b32 s4, 0x50401002314; GFX900-NEXT:    v_perm_b32 v0, v5, v0, s42315; GFX900-NEXT:    v_perm_b32 v1, v4, v1, s42316; GFX900-NEXT:    s_setpc_b64 s[30:31]2317;2318; GFX950-LABEL: v_minimumnum_v4bf16:2319; GFX950:       ; %bb.0:2320; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2321; GFX950-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12322; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v4, v42323; GFX950-NEXT:    v_lshrrev_b32_e32 v4, 16, v32324; GFX950-NEXT:    v_and_b32_e32 v7, 0xffff0000, v32325; GFX950-NEXT:    v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2326; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v72327; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v52328; GFX950-NEXT:    s_movk_i32 s0, 0x80002329; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc2330; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v42331; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v72332; GFX950-NEXT:    v_lshrrev_b32_e32 v7, 16, v02333; GFX950-NEXT:    v_and_b32_e32 v8, 0xffff0000, v22334; GFX950-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc2335; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v52336; GFX950-NEXT:    s_nop 12337; GFX950-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc2338; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v42339; GFX950-NEXT:    s_nop 12340; GFX950-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc2341; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v62342; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v52343; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v02344; GFX950-NEXT:    s_nop 02345; GFX950-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc2346; GFX950-NEXT:    v_lshrrev_b32_e32 v6, 16, v22347; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v52348; GFX950-NEXT:    s_nop 12349; GFX950-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc2350; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v8, v82351; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v52352; GFX950-NEXT:    s_nop 02353; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc2354; GFX950-NEXT:    v_lshlrev_b32_e32 v8, 16, v62355; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v82356; GFX950-NEXT:    s_nop 12357; GFX950-NEXT:    v_cndmask_b32_e32 v7, v6, v5, vcc2358; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v52359; GFX950-NEXT:    s_nop 12360; GFX950-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc2361; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v62362; GFX950-NEXT:    s_nop 12363; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc2364; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v72365; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v62366; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v12367; GFX950-NEXT:    s_nop 02368; GFX950-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc2369; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v62370; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v32371; GFX950-NEXT:    s_nop 02372; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2373; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v62374; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v12375; GFX950-NEXT:    s_nop 02376; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc2377; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v32378; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v62379; GFX950-NEXT:    s_nop 12380; GFX950-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc2381; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v12382; GFX950-NEXT:    s_nop 12383; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc2384; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v32385; GFX950-NEXT:    s_nop 12386; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2387; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v62388; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32389; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v02390; GFX950-NEXT:    s_nop 02391; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc2392; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v32393; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v22394; GFX950-NEXT:    s_nop 02395; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2396; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v32397; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v02398; GFX950-NEXT:    s_nop 02399; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc2400; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v22401; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v32402; GFX950-NEXT:    s_nop 12403; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc2404; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v02405; GFX950-NEXT:    s_nop 12406; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc2407; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v22408; GFX950-NEXT:    s_mov_b32 s0, 0x50401002409; GFX950-NEXT:    v_perm_b32 v1, v4, v1, s02410; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2411; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v32412; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v22413; GFX950-NEXT:    s_nop 12414; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc2415; GFX950-NEXT:    v_perm_b32 v0, v5, v0, s02416; GFX950-NEXT:    s_setpc_b64 s[30:31]2417;2418; GFX10-LABEL: v_minimumnum_v4bf16:2419; GFX10:       ; %bb.0:2420; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2421; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12422; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v32423; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v32424; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v22425; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v02426; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42427; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v02428; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v12429; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v02430; GFX10-NEXT:    v_and_b32_e32 v9, 0xffff0000, v22431; GFX10-NEXT:    v_cndmask_b32_sdwa v10, v1, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2432; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v62433; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v32434; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v22435; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc_lo2436; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42437; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v52438; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v7, vcc_lo2439; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v112440; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v102441; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v42442; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2443; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v132444; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2445; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v142446; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v10, vcc_lo2447; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v92448; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v4, vcc_lo2449; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v122450; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo2451; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v102452; GFX10-NEXT:    v_cndmask_b32_e32 v9, v8, v10, vcc_lo2453; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v62454; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v72455; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v82456; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo2457; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52458; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo2459; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v62460; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v32461; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v02462; GFX10-NEXT:    v_cndmask_b32_e32 v6, v7, v4, vcc_lo2463; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v102464; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v22465; GFX10-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo2466; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v12467; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v42468; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo2469; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v92470; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v62471; GFX10-NEXT:    v_cndmask_b32_e32 v8, v3, v1, vcc_lo2472; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v72473; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc_lo2474; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v102475; GFX10-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo2476; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12477; GFX10-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo2478; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v02479; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo2480; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32481; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2482; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22483; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v72484; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2485; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v92486; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v82487; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo2488; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v32489; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo2490; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v22491; GFX10-NEXT:    v_perm_b32 v0, v4, v0, 0x50401002492; GFX10-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo2493; GFX10-NEXT:    v_perm_b32 v1, v5, v1, 0x50401002494; GFX10-NEXT:    s_setpc_b64 s[30:31]2495;2496; GFX11-TRUE16-LABEL: v_minimumnum_v4bf16:2497; GFX11-TRUE16:       ; %bb.0:2498; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2499; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12500; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v32501; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 02502; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v02503; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v22504; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42505; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v52506; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l2507; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v32508; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo2509; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)2510; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v9, v92511; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v22512; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.h, v6.h, s02513; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h2514; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2515; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v9, v92516; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v52517; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo2518; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v72519; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l2520; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)2521; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v6.h, s02522; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l2523; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v8, v82524; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v12525; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v62526; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo2527; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2528; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v2.h, v6.h, s02529; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h2530; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v72531; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v7.h2532; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo2533; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v82534; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l2535; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)2536; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.l, v6.h, s02537; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v5.l2538; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo2539; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v62540; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2541; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v8.h, s22542; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v8.h2543; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v02544; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v8, v62545; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2546; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v8.h, s02547; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h2548; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v8.h, s22549; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v3, v32550; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v1.h, v7.h, s42551; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)2552; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s02553; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l2554; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s22555; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l2556; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2557; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v62558; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s32559; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v0.h2560; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2561; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s02562; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v62563; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2564; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s22565; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v6.h2566; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s32567; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v5.h2568; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)2569; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s22570; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l2571; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v5.h, s32572; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2573; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v62574; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v0.h, s12575; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo2576; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2577; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s22578; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2579;2580; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16:2581; GFX11-FAKE16:       ; %bb.0:2582; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2583; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12584; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v32585; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v12586; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v02587; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12588; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42589; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)2590; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v32591; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v72592; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v22593; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v02594; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)2595; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v42596; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc_lo2597; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v52598; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2599; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v112600; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v22601; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v62602; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc_lo2603; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v122604; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2605; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v42606; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v32607; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v92608; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v02609; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52610; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v22611; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2612; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v72613; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v142614; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2615; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v102616; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2617; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v02618; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v82619; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v62620; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v132621; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo2622; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2623; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v92624; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v12625; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc_lo2626; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v152627; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v32628; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo2629; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v62630; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc_lo2631; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)2632; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v82633; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v52634; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v3, v1, vcc_lo2635; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v22636; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v72637; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc_lo2638; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)2639; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v102640; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo2641; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12642; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo2643; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v02644; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo2645; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32646; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)2647; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2648; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22649; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v72650; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v92651; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v82652; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)2653; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v32654; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo2655; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2656; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v22657; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401002658; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo2659; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2660; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401002661; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2662;2663; GFX12-TRUE16-LABEL: v_minimumnum_v4bf16:2664; GFX12-TRUE16:       ; %bb.0:2665; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x02666; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x02667; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x02668; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x02669; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x02670; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12671; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v32672; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 02673; GFX12-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v02674; GFX12-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v22675; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42676; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v52677; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l2678; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v32679; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2680; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo2681; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2682; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v9, v92683; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v22684; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2685; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.h, v6.h, s02686; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h2687; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)2688; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v9, v92689; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v52690; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2691; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo2692; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v72693; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l2694; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2695; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)2696; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v6.h, s02697; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l2698; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v8, v82699; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v12700; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v62701; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2702; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo2703; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2704; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2705; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v2.h, v6.h, s02706; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h2707; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v72708; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v7.h2709; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2710; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo2711; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v82712; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l2713; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2714; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)2715; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.l, v6.h, s02716; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v5.l2717; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2718; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo2719; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v62720; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)2721; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v8.h, s22722; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v8.h2723; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v02724; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v8, v62725; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2726; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)2727; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v8.h, s02728; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h2729; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v8.h, s22730; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v3, v32731; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v1.h, v7.h, s42732; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2733; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)2734; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s02735; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l2736; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s22737; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l2738; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v62739; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)2740; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s32741; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v0.h2742; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2743; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s02744; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)2745; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v62746; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2747; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s22748; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v6.h2749; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)2750; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s32751; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v5.h2752; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2753; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s22754; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l2755; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)2756; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v5.h, s32757; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v62758; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2759; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v0.h, s12760; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)2761; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo2762; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)2763; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s22764; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]2765;2766; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16:2767; GFX12-FAKE16:       ; %bb.0:2768; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x02769; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x02770; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x02771; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x02772; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x02773; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v12774; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v32775; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v12776; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v02777; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v12778; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v42779; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2780; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v32781; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)2782; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v72783; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v22784; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v02785; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v42786; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2787; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc_lo2788; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)2789; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v52790; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v112791; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2792; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v22793; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v62794; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2795; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc_lo2796; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v122797; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2798; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2799; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v42800; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2801; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v32802; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v92803; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2804; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v02805; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v52806; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v22807; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2808; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)2809; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v72810; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v142811; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2812; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2813; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v102814; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v02815; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)2816; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v82817; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2818; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v62819; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v132820; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2821; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo2822; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2823; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v92824; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v12825; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2826; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc_lo2827; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v152828; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v32829; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2830; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo2831; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v62832; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2833; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc_lo2834; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v82835; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v52836; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2837; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v3, v1, vcc_lo2838; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v22839; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v72840; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2841; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc_lo2842; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)2843; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v102844; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2845; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo2846; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v12847; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2848; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo2849; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v02850; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2851; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo2852; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v32853; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2854; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2855; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v22856; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2857; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v72858; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v92859; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2860; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v82861; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)2862; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v32863; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2864; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo2865; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v22866; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)2867; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x50401002868; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)2869; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo2870; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x50401002871; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]2872  %result = call <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)2873  ret <4 x bfloat> %result2874}2875 2876define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y) {2877; GFX7-LABEL: v_minimumnum_v4bf16_nnan:2878; GFX7:       ; %bb.0:2879; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2880; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v02881; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v42882; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v12883; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v52884; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v22885; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v62886; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v32887; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v72888; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v72889; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v32890; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v62891; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v22892; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v52893; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v12894; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v42895; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02896; GFX7-NEXT:    v_min_f32_e32 v3, v3, v72897; GFX7-NEXT:    v_min_f32_e32 v2, v2, v62898; GFX7-NEXT:    v_min_f32_e32 v1, v1, v52899; GFX7-NEXT:    v_min_f32_e32 v0, v0, v42900; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v02901; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v12902; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v22903; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v32904; GFX7-NEXT:    s_setpc_b64 s[30:31]2905;2906; GFX8-LABEL: v_minimumnum_v4bf16_nnan:2907; GFX8:       ; %bb.0:2908; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2909; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v32910; GFX8-NEXT:    v_and_b32_e32 v5, 0xffff0000, v12911; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v12912; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v32913; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v42914; GFX8-NEXT:    s_movk_i32 s4, 0x80002915; GFX8-NEXT:    v_cndmask_b32_e32 v4, v7, v6, vcc2916; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v62917; GFX8-NEXT:    v_cndmask_b32_e32 v5, v4, v6, vcc2918; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v72919; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v42920; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc2921; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v62922; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc2923; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v32924; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v12925; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v52926; GFX8-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc2927; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v12928; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc2929; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v32930; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2931; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v52932; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32933; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc2934; GFX8-NEXT:    v_and_b32_e32 v3, 0xffff0000, v22935; GFX8-NEXT:    v_and_b32_e32 v5, 0xffff0000, v02936; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v02937; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v22938; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v32939; GFX8-NEXT:    v_cndmask_b32_e32 v3, v7, v6, vcc2940; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v62941; GFX8-NEXT:    v_cndmask_b32_e32 v5, v3, v6, vcc2942; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v72943; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v32944; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc2945; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v62946; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc2947; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v22948; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v02949; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v52950; GFX8-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc2951; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v02952; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc2953; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v22954; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc2955; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v52956; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v22957; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc2958; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v32959; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2960; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v42961; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2962; GFX8-NEXT:    s_setpc_b64 s[30:31]2963;2964; GFX900-LABEL: v_minimumnum_v4bf16_nnan:2965; GFX900:       ; %bb.0:2966; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2967; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v32968; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v12969; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v42970; GFX900-NEXT:    s_movk_i32 s4, 0x80002971; GFX900-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc2972; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v12973; GFX900-NEXT:    v_cndmask_b32_e32 v5, v4, v1, vcc2974; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v32975; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v42976; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc2977; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v62978; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc2979; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v32980; GFX900-NEXT:    v_and_b32_e32 v6, 0xffff0000, v12981; GFX900-NEXT:    v_lshrrev_b32_e32 v1, 16, v12982; GFX900-NEXT:    v_lshrrev_b32_e32 v3, 16, v32983; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v52984; GFX900-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc2985; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v12986; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc2987; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v32988; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2989; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v52990; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32991; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc2992; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v22993; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v02994; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v32995; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc2996; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v02997; GFX900-NEXT:    v_cndmask_b32_e32 v5, v3, v0, vcc2998; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v22999; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v33000; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v2, vcc3001; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v63002; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc3003; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v23004; GFX900-NEXT:    v_and_b32_e32 v6, 0xffff0000, v03005; GFX900-NEXT:    v_lshrrev_b32_e32 v0, 16, v03006; GFX900-NEXT:    v_lshrrev_b32_e32 v2, 16, v23007; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v53008; GFX900-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc3009; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v03010; GFX900-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc3011; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v23012; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc3013; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v53014; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v23015; GFX900-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc3016; GFX900-NEXT:    s_mov_b32 s4, 0x50401003017; GFX900-NEXT:    v_perm_b32 v0, v0, v3, s43018; GFX900-NEXT:    v_perm_b32 v1, v1, v4, s43019; GFX900-NEXT:    s_setpc_b64 s[30:31]3020;3021; GFX950-LABEL: v_minimumnum_v4bf16_nnan:3022; GFX950:       ; %bb.0:3023; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3024; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v33025; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v13026; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v43027; GFX950-NEXT:    s_movk_i32 s0, 0x80003028; GFX950-NEXT:    s_nop 03029; GFX950-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc3030; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v13031; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v43032; GFX950-NEXT:    s_nop 03033; GFX950-NEXT:    v_cndmask_b32_e32 v5, v4, v1, vcc3034; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v33035; GFX950-NEXT:    s_nop 13036; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v3, vcc3037; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v63038; GFX950-NEXT:    v_and_b32_e32 v6, 0xffff0000, v13039; GFX950-NEXT:    v_lshrrev_b32_e32 v1, 16, v13040; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc3041; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v33042; GFX950-NEXT:    v_lshrrev_b32_e32 v3, 16, v33043; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v53044; GFX950-NEXT:    s_nop 13045; GFX950-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc3046; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v13047; GFX950-NEXT:    s_nop 13048; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3049; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v33050; GFX950-NEXT:    s_nop 13051; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc3052; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v53053; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v33054; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v23055; GFX950-NEXT:    s_nop 03056; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3057; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v03058; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v33059; GFX950-NEXT:    s_nop 13060; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc3061; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v03062; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v33063; GFX950-NEXT:    s_nop 03064; GFX950-NEXT:    v_cndmask_b32_e32 v5, v3, v0, vcc3065; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v23066; GFX950-NEXT:    s_nop 13067; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v2, vcc3068; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v63069; GFX950-NEXT:    v_and_b32_e32 v6, 0xffff0000, v03070; GFX950-NEXT:    v_lshrrev_b32_e32 v0, 16, v03071; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc3072; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v23073; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 16, v23074; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v53075; GFX950-NEXT:    s_nop 13076; GFX950-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc3077; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v03078; GFX950-NEXT:    s_nop 13079; GFX950-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc3080; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v23081; GFX950-NEXT:    s_mov_b32 s0, 0x50401003082; GFX950-NEXT:    v_perm_b32 v1, v1, v4, s03083; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc3084; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v53085; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v23086; GFX950-NEXT:    s_nop 13087; GFX950-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc3088; GFX950-NEXT:    v_perm_b32 v0, v0, v3, s03089; GFX950-NEXT:    s_setpc_b64 s[30:31]3090;3091; GFX10-LABEL: v_minimumnum_v4bf16_nnan:3092; GFX10:       ; %bb.0:3093; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3094; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v33095; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v13096; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v33097; GFX10-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13098; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v13099; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v23100; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v43101; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v33102; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v03103; GFX10-NEXT:    v_and_b32_e32 v11, 0xffff0000, v23104; GFX10-NEXT:    v_and_b32_e32 v12, 0xffff0000, v03105; GFX10-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc_lo3106; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13107; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v43108; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo3109; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33110; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo3111; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v63112; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 16, v03113; GFX10-NEXT:    v_cndmask_b32_e32 v6, v5, v8, vcc_lo3114; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v133115; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo3116; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v93117; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v23118; GFX10-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo3119; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83120; GFX10-NEXT:    v_cndmask_b32_e32 v8, v6, v8, vcc_lo3121; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v113122; GFX10-NEXT:    v_cndmask_b32_e32 v9, v4, v3, vcc_lo3123; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v03124; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo3125; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53126; GFX10-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo3127; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33128; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v93129; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo3130; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23131; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3132; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v73133; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v43134; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc_lo3135; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v23136; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v63137; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo3138; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v83139; GFX10-NEXT:    v_cndmask_b32_e32 v2, v9, v3, vcc_lo3140; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v43141; GFX10-NEXT:    v_perm_b32 v0, v2, v0, 0x50401003142; GFX10-NEXT:    v_cndmask_b32_e32 v3, v6, v5, vcc_lo3143; GFX10-NEXT:    v_perm_b32 v1, v3, v1, 0x50401003144; GFX10-NEXT:    s_setpc_b64 s[30:31]3145;3146; GFX11-TRUE16-LABEL: v_minimumnum_v4bf16_nnan:3147; GFX11-TRUE16:       ; %bb.0:3148; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3149; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v33150; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v13151; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.l3152; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v33153; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13154; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v1.h3155; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v43156; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 03157; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.l, v1.l, vcc_lo3158; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l3159; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)3160; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v5.h, v1.l, s03161; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53162; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)3163; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.l, v3.l, vcc_lo3164; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v63165; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v23166; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v03167; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v5.h, v1.l, s03168; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.h, v1.h, vcc_lo3169; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.h3170; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)3171; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.h, v1.h, s13172; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53173; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.l3174; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.h, v3.h, vcc_lo3175; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v43176; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v23177; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v03178; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)3179; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.h, v1.h, s03180; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v2.l, v0.l, vcc_lo3181; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l3182; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v5.h, v0.l, s13183; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53184; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.h3185; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)3186; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo3187; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v43188; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v5.h, v0.l, s03189; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v2.h, v0.h, vcc_lo3190; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h3191; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)3192; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.h, v0.h, s13193; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53194; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo3195; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3196; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.h, v0.h, s03197; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]3198;3199; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_nnan:3200; GFX11-FAKE16:       ; %bb.0:3201; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3202; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v33203; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v13204; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v13205; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v23206; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)3207; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v43208; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v33209; GFX11-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13210; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc_lo3211; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13212; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v33213; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)3214; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v43215; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo3216; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33217; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v03218; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v63219; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v03220; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v8, vcc_lo3221; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v133222; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v12, 0xffff0000, v03223; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v93224; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v23225; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo3226; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v23227; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83228; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v6, v8, vcc_lo3229; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)3230; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v113231; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v4, v3, vcc_lo3232; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v03233; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo3234; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53235; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo3236; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33237; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo3238; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23239; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3240; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v73241; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v43242; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v63243; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v93244; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)3245; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v23246; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo3247; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v83248; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v9, v3, vcc_lo3249; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v43250; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v6, v5, vcc_lo3251; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3252; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401003253; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x50401003254; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]3255;3256; GFX12-TRUE16-LABEL: v_minimumnum_v4bf16_nnan:3257; GFX12-TRUE16:       ; %bb.0:3258; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x03259; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x03260; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x03261; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x03262; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x03263; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v33264; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v13265; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.l3266; GFX12-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v33267; GFX12-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13268; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v1.h3269; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v43270; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 03271; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3272; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.l, v1.l, vcc_lo3273; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l3274; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)3275; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)3276; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v5.h, v1.l, s03277; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53278; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3279; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v4.l, v3.l, vcc_lo3280; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v63281; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v23282; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v03283; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)3284; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v5.h, v1.l, s03285; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3286; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.h, v1.h, vcc_lo3287; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.h3288; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3289; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.h, v1.h, s13290; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53291; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.l3292; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3293; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.h, v3.h, vcc_lo3294; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v43295; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v23296; GFX12-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v03297; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)3298; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.h, v1.h, s03299; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3300; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v2.l, v0.l, vcc_lo3301; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l3302; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3303; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v5.h, v0.l, s13304; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53305; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v0.h3306; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3307; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo3308; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v43309; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)3310; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)3311; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v5.h, v0.l, s03312; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3313; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v2.h, v0.h, vcc_lo3314; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h3315; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.h, v0.h, s13316; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v53317; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)3318; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)3319; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo3320; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)3321; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.h, v0.h, s03322; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]3323;3324; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16_nnan:3325; GFX12-FAKE16:       ; %bb.0:3326; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x03327; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x03328; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x03329; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x03330; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x03331; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v33332; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v13333; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v13334; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v23335; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)3336; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v43337; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v33338; GFX12-FAKE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13339; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3340; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v3, v1, vcc_lo3341; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13342; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v33343; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)3344; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v43345; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3346; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo3347; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33348; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3349; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v3 :: v_dual_lshlrev_b32 v10, 16, v03350; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v63351; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v03352; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3353; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v8, vcc_lo3354; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v133355; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3356; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v4, v1 :: v_dual_and_b32 v12, 0xffff0000, v03357; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v93358; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v23359; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3360; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo3361; GFX12-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v23362; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83363; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3364; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v6, v8, vcc_lo3365; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)3366; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v113367; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3368; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v4, v3, vcc_lo3369; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v03370; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3371; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo3372; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53373; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3374; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo3375; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33376; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3377; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo3378; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23379; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3380; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3381; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v73382; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v43383; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3384; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v4 :: v_dual_lshlrev_b32 v4, 16, v63385; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v93386; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v23387; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3388; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo3389; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)3390; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v83391; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3392; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v9, v3, vcc_lo3393; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v43394; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)3395; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v6, v5, vcc_lo3396; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)3397; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v2, v0, 0x50401003398; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v3, v1, 0x50401003399; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]3400  %result = call nnan <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)3401  ret <4 x bfloat> %result3402}3403 3404define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) {3405; GFX7-LABEL: v_minimumnum_v6bf16:3406; GFX7:       ; %bb.0:3407; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3408; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v03409; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v63410; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v13411; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v73412; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v23413; GFX7-NEXT:    v_mul_f32_e32 v8, 1.0, v83414; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v33415; GFX7-NEXT:    v_mul_f32_e32 v9, 1.0, v93416; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v43417; GFX7-NEXT:    v_mul_f32_e32 v10, 1.0, v103418; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v53419; GFX7-NEXT:    v_mul_f32_e32 v11, 1.0, v113420; GFX7-NEXT:    v_and_b32_e32 v11, 0xffff0000, v113421; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v53422; GFX7-NEXT:    v_and_b32_e32 v10, 0xffff0000, v103423; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v43424; GFX7-NEXT:    v_and_b32_e32 v9, 0xffff0000, v93425; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v33426; GFX7-NEXT:    v_and_b32_e32 v8, 0xffff0000, v83427; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v23428; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v73429; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v13430; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v63431; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v03432; GFX7-NEXT:    v_min_f32_e32 v5, v5, v113433; GFX7-NEXT:    v_min_f32_e32 v4, v4, v103434; GFX7-NEXT:    v_min_f32_e32 v3, v3, v93435; GFX7-NEXT:    v_min_f32_e32 v2, v2, v83436; GFX7-NEXT:    v_min_f32_e32 v1, v1, v73437; GFX7-NEXT:    v_min_f32_e32 v0, v0, v63438; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v03439; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v13440; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v23441; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v33442; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v43443; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v53444; GFX7-NEXT:    s_setpc_b64 s[30:31]3445;3446; GFX8-LABEL: v_minimumnum_v6bf16:3447; GFX8:       ; %bb.0:3448; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3449; GFX8-NEXT:    v_and_b32_e32 v6, 0xffff0000, v23450; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v53451; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 16, v23452; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v63453; GFX8-NEXT:    v_and_b32_e32 v9, 0xffff0000, v53454; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc3455; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93456; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc3457; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v63458; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v73459; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v8, v93460; GFX8-NEXT:    s_movk_i32 s4, 0x80003461; GFX8-NEXT:    v_cndmask_b32_e32 v8, v7, v6, vcc3462; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v63463; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc3464; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v73465; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc3466; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v83467; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v73468; GFX8-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13469; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc3470; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 16, v43471; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v13472; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v73473; GFX8-NEXT:    v_and_b32_e32 v10, 0xffff0000, v43474; GFX8-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc3475; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v10, v103476; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc3477; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v73478; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v83479; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v9, v103480; GFX8-NEXT:    v_cndmask_b32_e32 v9, v8, v7, vcc3481; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v73482; GFX8-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc3483; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v83484; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc3485; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v93486; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v83487; GFX8-NEXT:    v_and_b32_e32 v8, 0xffff0000, v03488; GFX8-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc3489; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v33490; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 16, v03491; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v8, v83492; GFX8-NEXT:    v_and_b32_e32 v11, 0xffff0000, v33493; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc3494; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v11, v113495; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc3496; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v83497; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v93498; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v113499; GFX8-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc3500; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v83501; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc3502; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v93503; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc3504; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v103505; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v93506; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v23507; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc3508; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93509; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v53510; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc3511; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93512; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v2, vcc3513; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v53514; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v23515; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v93516; GFX8-NEXT:    v_cndmask_b32_e32 v9, v5, v2, vcc3517; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v23518; GFX8-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc3519; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v53520; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc3521; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v93522; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v53523; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v13524; GFX8-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc3525; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v53526; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v43527; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc3528; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v53529; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc3530; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v43531; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v13532; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v9, v53533; GFX8-NEXT:    v_cndmask_b32_e32 v5, v4, v1, vcc3534; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v13535; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3536; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v43537; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc3538; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v53539; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v43540; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v03541; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3542; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v4, v43543; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v33544; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3545; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v4, v43546; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v0, vcc3547; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v33548; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v03549; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v43550; GFX8-NEXT:    v_cndmask_b32_e32 v4, v3, v0, vcc3551; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v03552; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc3553; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v33554; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3555; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v43556; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v33557; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc3558; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v83559; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3560; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v73561; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3562; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v63563; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD3564; GFX8-NEXT:    s_setpc_b64 s[30:31]3565;3566; GFX900-LABEL: v_minimumnum_v6bf16:3567; GFX900:       ; %bb.0:3568; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3569; GFX900-NEXT:    v_and_b32_e32 v6, 0xffff0000, v23570; GFX900-NEXT:    v_lshrrev_b32_e32 v7, 16, v53571; GFX900-NEXT:    v_lshrrev_b32_e32 v8, 16, v23572; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v63573; GFX900-NEXT:    v_and_b32_e32 v9, 0xffff0000, v53574; GFX900-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc3575; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93576; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc3577; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 16, v63578; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v73579; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v8, v93580; GFX900-NEXT:    s_movk_i32 s4, 0x80003581; GFX900-NEXT:    v_cndmask_b32_e32 v8, v7, v6, vcc3582; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v63583; GFX900-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc3584; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v73585; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc3586; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v83587; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v73588; GFX900-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13589; GFX900-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc3590; GFX900-NEXT:    v_lshrrev_b32_e32 v8, 16, v43591; GFX900-NEXT:    v_lshrrev_b32_e32 v9, 16, v13592; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v73593; GFX900-NEXT:    v_and_b32_e32 v10, 0xffff0000, v43594; GFX900-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc3595; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v10, v103596; GFX900-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc3597; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v73598; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v83599; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v9, v103600; GFX900-NEXT:    v_cndmask_b32_e32 v9, v8, v7, vcc3601; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v73602; GFX900-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc3603; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v83604; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc3605; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 16, v93606; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v83607; GFX900-NEXT:    v_and_b32_e32 v8, 0xffff0000, v03608; GFX900-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc3609; GFX900-NEXT:    v_lshrrev_b32_e32 v9, 16, v33610; GFX900-NEXT:    v_lshrrev_b32_e32 v10, 16, v03611; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v8, v83612; GFX900-NEXT:    v_and_b32_e32 v11, 0xffff0000, v33613; GFX900-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc3614; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v11, v113615; GFX900-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc3616; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v83617; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v93618; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v113619; GFX900-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc3620; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v83621; GFX900-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc3622; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v93623; GFX900-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc3624; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v103625; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v93626; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v23627; GFX900-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc3628; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93629; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v53630; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc3631; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93632; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v2, vcc3633; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v53634; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v23635; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v93636; GFX900-NEXT:    v_cndmask_b32_e32 v9, v5, v2, vcc3637; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v23638; GFX900-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc3639; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v53640; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc3641; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v93642; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v53643; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v13644; GFX900-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc3645; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v53646; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v43647; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc3648; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v53649; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc3650; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v43651; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v13652; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v9, v53653; GFX900-NEXT:    v_cndmask_b32_e32 v5, v4, v1, vcc3654; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v13655; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3656; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v43657; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc3658; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v53659; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v43660; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v03661; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3662; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v4, v43663; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v33664; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3665; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v4, v43666; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v0, vcc3667; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v33668; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v03669; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v43670; GFX900-NEXT:    v_cndmask_b32_e32 v4, v3, v0, vcc3671; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v03672; GFX900-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc3673; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v33674; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3675; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v43676; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v33677; GFX900-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc3678; GFX900-NEXT:    s_mov_b32 s4, 0x50401003679; GFX900-NEXT:    v_perm_b32 v0, v8, v0, s43680; GFX900-NEXT:    v_perm_b32 v1, v7, v1, s43681; GFX900-NEXT:    v_perm_b32 v2, v6, v2, s43682; GFX900-NEXT:    s_setpc_b64 s[30:31]3683;3684; GFX950-LABEL: v_minimumnum_v6bf16:3685; GFX950:       ; %bb.0:3686; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3687; GFX950-NEXT:    v_and_b32_e32 v6, 0xffff0000, v23688; GFX950-NEXT:    v_lshrrev_b32_e32 v7, 16, v53689; GFX950-NEXT:    v_lshrrev_b32_e32 v8, 16, v23690; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v63691; GFX950-NEXT:    v_and_b32_e32 v9, 0xffff0000, v53692; GFX950-NEXT:    s_movk_i32 s0, 0x80003693; GFX950-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc3694; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93695; GFX950-NEXT:    v_lshlrev_b32_e32 v8, 16, v63696; GFX950-NEXT:    v_and_b32_e32 v10, 0xffff0000, v43697; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc3698; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v73699; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v8, v93700; GFX950-NEXT:    v_lshrrev_b32_e32 v9, 16, v13701; GFX950-NEXT:    v_and_b32_e32 v11, 0xffff0000, v33702; GFX950-NEXT:    v_cndmask_b32_e32 v8, v7, v6, vcc3703; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v63704; GFX950-NEXT:    s_nop 13705; GFX950-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc3706; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v73707; GFX950-NEXT:    s_nop 13708; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc3709; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v83710; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v73711; GFX950-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13712; GFX950-NEXT:    s_nop 03713; GFX950-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc3714; GFX950-NEXT:    v_lshrrev_b32_e32 v8, 16, v43715; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v73716; GFX950-NEXT:    s_nop 13717; GFX950-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc3718; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v10, v103719; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v73720; GFX950-NEXT:    s_nop 03721; GFX950-NEXT:    v_cndmask_b32_e32 v8, v8, v7, vcc3722; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v83723; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v9, v103724; GFX950-NEXT:    v_lshrrev_b32_e32 v10, 16, v03725; GFX950-NEXT:    s_nop 03726; GFX950-NEXT:    v_cndmask_b32_e32 v9, v8, v7, vcc3727; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v73728; GFX950-NEXT:    s_nop 13729; GFX950-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc3730; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v83731; GFX950-NEXT:    s_nop 13732; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc3733; GFX950-NEXT:    v_lshlrev_b32_e32 v8, 16, v93734; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v83735; GFX950-NEXT:    v_and_b32_e32 v8, 0xffff0000, v03736; GFX950-NEXT:    s_nop 03737; GFX950-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc3738; GFX950-NEXT:    v_lshrrev_b32_e32 v9, 16, v33739; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v8, v83740; GFX950-NEXT:    s_nop 13741; GFX950-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc3742; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v11, v113743; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v83744; GFX950-NEXT:    s_nop 03745; GFX950-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc3746; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v93747; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v113748; GFX950-NEXT:    s_nop 13749; GFX950-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc3750; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v83751; GFX950-NEXT:    s_nop 13752; GFX950-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc3753; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v93754; GFX950-NEXT:    s_nop 13755; GFX950-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc3756; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v103757; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v93758; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v23759; GFX950-NEXT:    s_nop 03760; GFX950-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc3761; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93762; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v53763; GFX950-NEXT:    s_nop 03764; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc3765; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v9, v93766; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v23767; GFX950-NEXT:    s_nop 03768; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v2, vcc3769; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v53770; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v93771; GFX950-NEXT:    s_nop 13772; GFX950-NEXT:    v_cndmask_b32_e32 v9, v5, v2, vcc3773; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v23774; GFX950-NEXT:    s_nop 13775; GFX950-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc3776; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v53777; GFX950-NEXT:    s_nop 13778; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc3779; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v93780; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v53781; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v13782; GFX950-NEXT:    s_nop 03783; GFX950-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc3784; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v53785; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v43786; GFX950-NEXT:    s_nop 03787; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc3788; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v53789; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v13790; GFX950-NEXT:    s_nop 03791; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc3792; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v43793; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v9, v53794; GFX950-NEXT:    s_nop 13795; GFX950-NEXT:    v_cndmask_b32_e32 v5, v4, v1, vcc3796; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v13797; GFX950-NEXT:    s_nop 13798; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3799; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v43800; GFX950-NEXT:    s_nop 13801; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc3802; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v53803; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v43804; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v03805; GFX950-NEXT:    s_nop 03806; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc3807; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v4, v43808; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v33809; GFX950-NEXT:    s_nop 03810; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3811; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v4, v43812; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v03813; GFX950-NEXT:    s_nop 03814; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v0, vcc3815; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v33816; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v43817; GFX950-NEXT:    s_nop 13818; GFX950-NEXT:    v_cndmask_b32_e32 v4, v3, v0, vcc3819; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v03820; GFX950-NEXT:    s_nop 13821; GFX950-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc3822; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v33823; GFX950-NEXT:    s_mov_b32 s0, 0x50401003824; GFX950-NEXT:    v_perm_b32 v1, v7, v1, s03825; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3826; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v43827; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v33828; GFX950-NEXT:    v_perm_b32 v2, v6, v2, s03829; GFX950-NEXT:    s_nop 03830; GFX950-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc3831; GFX950-NEXT:    v_perm_b32 v0, v8, v0, s03832; GFX950-NEXT:    s_setpc_b64 s[30:31]3833;3834; GFX10-LABEL: v_minimumnum_v6bf16:3835; GFX10:       ; %bb.0:3836; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3837; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v23838; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v53839; GFX10-NEXT:    v_and_b32_e32 v8, 0xffff0000, v53840; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 16, v43841; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v13842; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v63843; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v13844; GFX10-NEXT:    v_and_b32_e32 v13, 0xffff0000, v03845; GFX10-NEXT:    v_and_b32_e32 v11, 0xffff0000, v43846; GFX10-NEXT:    v_lshrrev_b32_e32 v14, 16, v33847; GFX10-NEXT:    v_cndmask_b32_sdwa v12, v2, v7, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3848; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v83849; GFX10-NEXT:    v_lshrrev_b32_e32 v15, 16, v03850; GFX10-NEXT:    v_and_b32_e32 v8, 0xffff0000, v33851; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v12, vcc_lo3852; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v63853; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v73854; GFX10-NEXT:    v_cndmask_b32_e32 v6, v10, v9, vcc_lo3855; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v133856; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v123857; GFX10-NEXT:    v_cndmask_b32_e32 v13, v15, v14, vcc_lo3858; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v113859; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v63860; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v133861; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v6, vcc_lo3862; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v163863; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v93864; GFX10-NEXT:    v_cndmask_b32_e32 v10, v7, v12, vcc_lo3865; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v123866; GFX10-NEXT:    v_cndmask_b32_e32 v12, v10, v12, vcc_lo3867; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v83868; GFX10-NEXT:    v_cndmask_b32_e32 v8, v14, v13, vcc_lo3869; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v73870; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v103871; GFX10-NEXT:    v_cndmask_b32_e32 v7, v12, v7, vcc_lo3872; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v163873; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v83874; GFX10-NEXT:    v_cndmask_b32_e32 v11, v9, v6, vcc_lo3875; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v143876; GFX10-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo3877; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v63878; GFX10-NEXT:    v_cndmask_b32_e32 v6, v11, v6, vcc_lo3879; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v123880; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v113881; GFX10-NEXT:    v_cndmask_b32_e32 v10, v8, v13, vcc_lo3882; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v93883; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc_lo3884; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v133885; GFX10-NEXT:    v_cndmask_b32_e32 v9, v10, v13, vcc_lo3886; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v123887; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v23888; GFX10-NEXT:    v_cndmask_b32_e32 v6, v11, v6, vcc_lo3889; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v83890; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v103891; GFX10-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo3892; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v133893; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v53894; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo3895; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v113896; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v03897; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc_lo3898; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v13899; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v93900; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v43901; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v2, vcc_lo3902; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v103903; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v33904; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo3905; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v113906; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v23907; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v13908; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo3909; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v93910; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v53911; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v03912; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc_lo3913; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v103914; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v43915; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v0, vcc_lo3916; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v93917; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v33918; GFX10-NEXT:    v_cndmask_b32_e32 v9, v5, v2, vcc_lo3919; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v103920; GFX10-NEXT:    v_cndmask_b32_e32 v10, v4, v1, vcc_lo3921; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23922; GFX10-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo3923; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v13, v113924; GFX10-NEXT:    v_cndmask_b32_e32 v11, v3, v0, vcc_lo3925; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v13926; GFX10-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc_lo3927; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v53928; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo3929; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v03930; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v113931; GFX10-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo3932; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v43933; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo3934; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v103935; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v33936; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo3937; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v43938; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v93939; GFX10-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc_lo3940; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v53941; GFX10-NEXT:    v_perm_b32 v1, v6, v1, 0x50401003942; GFX10-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo3943; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v33944; GFX10-NEXT:    v_perm_b32 v0, v8, v0, 0x50401003945; GFX10-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo3946; GFX10-NEXT:    v_perm_b32 v2, v7, v2, 0x50401003947; GFX10-NEXT:    s_setpc_b64 s[30:31]3948;3949; GFX11-TRUE16-LABEL: v_minimumnum_v6bf16:3950; GFX11-TRUE16:       ; %bb.0:3951; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3952; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v23953; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v53954; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, 03955; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v43956; GFX11-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v03957; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v63958; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v7, v73959; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v9.l3960; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v13961; GFX11-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v33962; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v2.h, v5.h, vcc_lo3963; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v53964; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)3965; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v5.h, v9.h, s03966; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h3967; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v13, v133968; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v43969; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)3970; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v83971; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v13, v133972; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.l, v8.h, v9.h, vcc_lo3973; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v73974; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)3975; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v6.l, v9.h, s03976; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v6.l3977; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v10, v103978; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v9.l3979; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v93980; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v1.h, v4.h, vcc_lo3981; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3982; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.h, v4.h, v9.h, s03983; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h3984; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v103985; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v10.h3986; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v10.h, v9.h, vcc_lo3987; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v113988; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v9.l3989; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)3990; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v7.l, v9.h, s03991; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v7.l3992; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v12, v123993; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v23994; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v93995; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v0.h, v3.h, vcc_lo3996; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)3997; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.h, v3.h, v9.h, s03998; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h3999; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v114000; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v11.h4001; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.l, v11.h, v9.h, vcc_lo4002; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v124003; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v9.l4004; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)4005; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v8.l, v9.h, s04006; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v8.l4007; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v2.l, v5.l, vcc_lo4008; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v94009; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)4010; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v5.l, v12.h, s34011; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v12.h4012; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v14013; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v12, v94014; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4015; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v9.h, v12.h, s04016; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h4017; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v2.l, v12.h, s34018; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v5, v54019; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v04020; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v34021; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)4022; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v1.h, v9.h, s04023; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l4024; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.l, v4.l, s34025; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v9.l4026; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v12, v124027; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v94028; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)4029; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v4.l, v1.h, s44030; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v1.h4031; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v2.h, v11.h, s74032; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v4.h, s04033; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)4034; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s3, v1, v94035; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v9.h, v1.h, s34036; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v9.h4037; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)4038; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v1.h, s44039; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v5, v54040; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v7.h, v10.h, s64041; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v0.h, v9.h, s34042; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v1.l4043; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)4044; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v3.l, s44045; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v9.l4046; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v7.l, v1.h, s24047; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v94048; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)4049; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v3.l, v0.h, s54050; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v0.h4051; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v3.h, s34052; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)4053; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v0, v94054; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v9.h, v0.h, s44055; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v9.h4056; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)4057; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s54058; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v8.h4059; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v0.h, v9.h, s44060; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v0.l4061; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4062; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v6.h, v8.h, s54063; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v94064; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)4065; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v6.l, v0.h, s14066; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v8.l, v4.l, vcc_lo4067; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v3.l, s44068; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]4069;4070; GFX11-FAKE16-LABEL: v_minimumnum_v6bf16:4071; GFX11-FAKE16:       ; %bb.0:4072; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4073; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v24074; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v54075; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v24076; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v14077; GFX11-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v04078; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v64079; GFX11-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v54080; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v34081; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc_lo4082; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)4083; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v94084; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v14085; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v44086; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc_lo4087; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)4088; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v84089; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v44090; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v74091; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v64092; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4093; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v134094; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v04095; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v7, v6, vcc_lo4096; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v114097; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v84098; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc_lo4099; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64100; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc_lo4101; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v144102; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo4103; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v74104; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)4105; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc_lo4106; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v34107; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v134108; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v104109; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v94110; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)4111; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v144112; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v124113; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v8, vcc_lo4114; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v134115; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v114116; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84117; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v74118; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)4119; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v154120; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v7, v12, vcc_lo4121; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v94122; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc_lo4123; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v124124; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)4125; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v10, v12, vcc_lo4126; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v134127; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v24128; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v11, v8, vcc_lo4129; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v74130; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v104131; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc_lo4132; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v124133; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v54134; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo4135; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v114136; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v04137; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo4138; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v94139; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v14140; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4141; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v104142; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo4143; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v114144; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v44145; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v24146; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v34147; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)4148; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v94149; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v54150; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc_lo4151; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v104152; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v14153; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)4154; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v94155; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v44156; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)4157; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v104158; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v34159; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24160; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)4161; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v04162; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v13, v114163; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v3, v0, vcc_lo4164; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14165; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc_lo4166; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54167; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo4168; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v04169; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo4170; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v44171; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v104172; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34173; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)4174; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v94175; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v114176; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v44177; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc_lo4178; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)4179; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v54180; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo4181; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v34182; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x50401004183; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo4184; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v8, v1, 0x50401004185; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)4186; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v6, v2, 0x50401004187; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]4188;4189; GFX12-TRUE16-LABEL: v_minimumnum_v6bf16:4190; GFX12-TRUE16:       ; %bb.0:4191; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x04192; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x04193; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x04194; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x04195; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x04196; GFX12-TRUE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v24197; GFX12-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v54198; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.l, 04199; GFX12-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v44200; GFX12-TRUE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v04201; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v64202; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v7, v74203; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v9.l4204; GFX12-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v14205; GFX12-TRUE16-NEXT:    v_and_b32_e32 v12, 0xffff0000, v34206; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4207; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v2.h, v5.h, vcc_lo4208; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v54209; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4210; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)4211; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v5.h, v9.h, s04212; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h4213; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v13, v134214; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v44215; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)4216; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v84217; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v13, v134218; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4219; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.l, v8.h, v9.h, vcc_lo4220; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v74221; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4222; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)4223; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v6.l, v9.h, s04224; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v6.l4225; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v10, v104226; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v9.l4227; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v94228; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4229; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v1.h, v4.h, vcc_lo4230; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4231; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4232; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.h, v4.h, v9.h, s04233; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h4234; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v104235; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v10.h4236; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4237; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.l, v10.h, v9.h, vcc_lo4238; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v114239; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v9.l4240; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4241; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)4242; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v7.l, v9.h, s04243; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v7.l4244; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v12, v124245; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v24246; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v94247; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4248; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v0.h, v3.h, vcc_lo4249; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4250; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4251; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.h, v3.h, v9.h, s04252; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h4253; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v114254; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v11.h4255; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4256; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.l, v11.h, v9.h, vcc_lo4257; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v124258; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v9.l4259; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4260; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)4261; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v8.l, v9.h, s04262; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v8.l4263; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4264; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v2.l, v5.l, vcc_lo4265; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v94266; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)4267; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v5.l, v12.h, s34268; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v12.h4269; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v14270; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v12, v94271; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4272; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4273; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v9.h, v12.h, s04274; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v9.h4275; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v2.l, v12.h, s34276; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v5, v54277; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v04278; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v34279; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4280; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v1.h, v9.h, s04281; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v2.l4282; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.l, v4.l, s34283; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v9.l4284; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v12, v124285; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)4286; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v94287; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v4.l, v1.h, s44288; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v1.h4289; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v2.h, v11.h, s74290; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4291; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v4.h, s04292; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s3, v1, v94293; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4294; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)4295; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v9.h, v1.h, s34296; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v9.h4297; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v1.h, s44298; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v5, v54299; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v7.h, v10.h, s64300; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4301; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)4302; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v0.h, v9.h, s34303; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v1.l4304; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v3.l, s44305; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v9.l4306; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v7.l, v1.h, s24307; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v94308; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)4309; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v3.l, v0.h, s54310; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v0.h4311; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4312; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v3.h, s34313; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)4314; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v0, v94315; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4316; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v9.h, v0.h, s44317; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v9.h4318; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)4319; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s54320; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v8.h4321; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4322; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v0.h, v9.h, s44323; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.h, v0.l4324; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)4325; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v6.h, v8.h, s54326; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v94327; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)4328; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v6.l, v0.h, s14329; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)4330; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v8.l, v4.l, vcc_lo4331; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)4332; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v3.l, s44333; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]4334;4335; GFX12-FAKE16-LABEL: v_minimumnum_v6bf16:4336; GFX12-FAKE16:       ; %bb.0:4337; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x04338; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x04339; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x04340; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x04341; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x04342; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v24343; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v54344; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v24345; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v14346; GFX12-FAKE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v04347; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v64348; GFX12-FAKE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v54349; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v15, 16, v34350; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4351; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc_lo4352; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)4353; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v94354; GFX12-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v14355; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v44356; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4357; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc_lo4358; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v84359; GFX12-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v44360; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4361; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)4362; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v10, v9 :: v_dual_lshlrev_b32 v13, 16, v74363; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v64364; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v134365; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v04366; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4367; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v7, v6, vcc_lo4368; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v114369; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v84370; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4371; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc_lo4372; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v64373; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4374; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc_lo4375; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v144376; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4377; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc_lo4378; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v74379; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4380; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc_lo4381; GFX12-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v34382; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)4383; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v134384; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v104385; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4386; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v15, v12 :: v_dual_lshlrev_b32 v14, 16, v94387; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v144388; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v124389; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4390; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v8, vcc_lo4391; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v134392; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4393; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)4394; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v10, v6 :: v_dual_lshlrev_b32 v13, 16, v114395; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v84396; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4397; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v11, v8 :: v_dual_lshlrev_b32 v15, 16, v74398; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v154399; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4400; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v7, v12, vcc_lo4401; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v94402; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4403; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc_lo4404; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v124405; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4406; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v10, v12, vcc_lo4407; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v134408; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v24409; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4410; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v11, v8, vcc_lo4411; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v74412; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v104413; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4414; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc_lo4415; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v124416; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v54417; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4418; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo4419; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v114420; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v04421; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4422; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo4423; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v94424; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4425; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v14426; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4427; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v104428; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4429; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo4430; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v114431; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v44432; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4433; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v11, 16, v24434; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v34435; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)4436; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v94437; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v54438; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4439; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v1, vcc_lo4440; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v104441; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4442; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v0 :: v_dual_lshlrev_b32 v12, 16, v14443; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v94444; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4445; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v5, v2 :: v_dual_lshlrev_b32 v10, 16, v44446; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4447; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v104448; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4449; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v4, v1 :: v_dual_lshlrev_b32 v11, 16, v34450; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v24451; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4452; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v9, v2 :: v_dual_lshlrev_b32 v13, 16, v04453; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4454; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v13, v114455; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4456; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v3, v0, vcc_lo4457; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14458; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4459; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc_lo4460; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v54461; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4462; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo4463; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v04464; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4465; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo4466; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v44467; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4468; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v4 :: v_dual_lshlrev_b32 v4, 16, v104469; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v34470; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4471; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v3 :: v_dual_lshlrev_b32 v3, 16, v94472; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v114473; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v44474; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4475; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc_lo4476; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)4477; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v54478; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4479; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo4480; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v34481; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v7, v0, 0x50401004482; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)4483; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo4484; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v8, v1, 0x50401004485; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)4486; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v6, v2, 0x50401004487; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]4488  %result = call <6 x bfloat> @llvm.minimumnum.v6bf16(<6 x bfloat> %x, <6 x bfloat> %y)4489  ret <6 x bfloat> %result4490}4491 4492define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) {4493; GFX7-LABEL: v_minimumnum_v8bf16:4494; GFX7:       ; %bb.0:4495; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4496; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v04497; GFX7-NEXT:    v_mul_f32_e32 v8, 1.0, v84498; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v14499; GFX7-NEXT:    v_mul_f32_e32 v9, 1.0, v94500; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v24501; GFX7-NEXT:    v_mul_f32_e32 v10, 1.0, v104502; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v34503; GFX7-NEXT:    v_mul_f32_e32 v11, 1.0, v114504; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v44505; GFX7-NEXT:    v_mul_f32_e32 v12, 1.0, v124506; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v54507; GFX7-NEXT:    v_mul_f32_e32 v13, 1.0, v134508; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v64509; GFX7-NEXT:    v_mul_f32_e32 v14, 1.0, v144510; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v74511; GFX7-NEXT:    v_mul_f32_e32 v15, 1.0, v154512; GFX7-NEXT:    v_and_b32_e32 v15, 0xffff0000, v154513; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v74514; GFX7-NEXT:    v_and_b32_e32 v14, 0xffff0000, v144515; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v64516; GFX7-NEXT:    v_and_b32_e32 v13, 0xffff0000, v134517; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v54518; GFX7-NEXT:    v_and_b32_e32 v12, 0xffff0000, v124519; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v44520; GFX7-NEXT:    v_and_b32_e32 v11, 0xffff0000, v114521; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v34522; GFX7-NEXT:    v_and_b32_e32 v10, 0xffff0000, v104523; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v24524; GFX7-NEXT:    v_and_b32_e32 v9, 0xffff0000, v94525; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v14526; GFX7-NEXT:    v_and_b32_e32 v8, 0xffff0000, v84527; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v04528; GFX7-NEXT:    v_min_f32_e32 v7, v7, v154529; GFX7-NEXT:    v_min_f32_e32 v6, v6, v144530; GFX7-NEXT:    v_min_f32_e32 v5, v5, v134531; GFX7-NEXT:    v_min_f32_e32 v4, v4, v124532; GFX7-NEXT:    v_min_f32_e32 v3, v3, v114533; GFX7-NEXT:    v_min_f32_e32 v2, v2, v104534; GFX7-NEXT:    v_min_f32_e32 v1, v1, v94535; GFX7-NEXT:    v_min_f32_e32 v0, v0, v84536; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v04537; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v14538; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v24539; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v34540; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v44541; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v54542; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v64543; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v74544; GFX7-NEXT:    s_setpc_b64 s[30:31]4545;4546; GFX8-LABEL: v_minimumnum_v8bf16:4547; GFX8:       ; %bb.0:4548; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4549; GFX8-NEXT:    v_and_b32_e32 v8, 0xffff0000, v34550; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v74551; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 16, v34552; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v8, v84553; GFX8-NEXT:    v_and_b32_e32 v11, 0xffff0000, v74554; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc4555; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v11, v114556; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc4557; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v84558; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v94559; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v114560; GFX8-NEXT:    s_movk_i32 s4, 0x80004561; GFX8-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc4562; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v84563; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc4564; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v94565; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc4566; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v104567; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v94568; GFX8-NEXT:    v_and_b32_e32 v9, 0xffff0000, v24569; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc4570; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 16, v64571; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 16, v24572; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v9, v94573; GFX8-NEXT:    v_and_b32_e32 v12, 0xffff0000, v64574; GFX8-NEXT:    v_cndmask_b32_e32 v9, v11, v10, vcc4575; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124576; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v9, vcc4577; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v94578; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v104579; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v11, v124580; GFX8-NEXT:    v_cndmask_b32_e32 v11, v10, v9, vcc4581; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v94582; GFX8-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc4583; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v104584; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc4585; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v114586; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v104587; GFX8-NEXT:    v_and_b32_e32 v10, 0xffff0000, v14588; GFX8-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc4589; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 16, v54590; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 16, v14591; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v10, v104592; GFX8-NEXT:    v_and_b32_e32 v13, 0xffff0000, v54593; GFX8-NEXT:    v_cndmask_b32_e32 v10, v12, v11, vcc4594; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v13, v134595; GFX8-NEXT:    v_cndmask_b32_e32 v11, v11, v10, vcc4596; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v104597; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v114598; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v134599; GFX8-NEXT:    v_cndmask_b32_e32 v12, v11, v10, vcc4600; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v104601; GFX8-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc4602; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114603; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc4604; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v124605; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114606; GFX8-NEXT:    v_and_b32_e32 v11, 0xffff0000, v04607; GFX8-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc4608; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 16, v44609; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 16, v04610; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v11, v114611; GFX8-NEXT:    v_and_b32_e32 v14, 0xffff0000, v44612; GFX8-NEXT:    v_cndmask_b32_e32 v11, v13, v12, vcc4613; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v14, v144614; GFX8-NEXT:    v_cndmask_b32_e32 v12, v12, v11, vcc4615; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v114616; GFX8-NEXT:    v_lshlrev_b32_e32 v14, 16, v124617; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v144618; GFX8-NEXT:    v_cndmask_b32_e32 v13, v12, v11, vcc4619; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114620; GFX8-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc4621; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v124622; GFX8-NEXT:    v_cndmask_b32_e32 v11, v11, v12, vcc4623; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v134624; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v124625; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v34626; GFX8-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc4627; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124628; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v74629; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc4630; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124631; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc4632; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v74633; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v34634; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v124635; GFX8-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc4636; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v34637; GFX8-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc4638; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v74639; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc4640; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v124641; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v74642; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v24643; GFX8-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc4644; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v74645; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v64646; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc4647; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v74648; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v2, vcc4649; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v64650; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v24651; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v74652; GFX8-NEXT:    v_cndmask_b32_e32 v7, v6, v2, vcc4653; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v24654; GFX8-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc4655; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v64656; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc4657; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v74658; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v64659; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v14660; GFX8-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc4661; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v64662; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v54663; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc4664; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v64665; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v1, vcc4666; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v54667; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v14668; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v64669; GFX8-NEXT:    v_cndmask_b32_e32 v6, v5, v1, vcc4670; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v14671; GFX8-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc4672; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v54673; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc4674; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v64675; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v54676; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v04677; GFX8-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc4678; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v54679; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v44680; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc4681; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v54682; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v0, vcc4683; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v44684; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v04685; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v54686; GFX8-NEXT:    v_cndmask_b32_e32 v5, v4, v0, vcc4687; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v04688; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc4689; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v44690; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc4691; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v54692; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v44693; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc4694; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v114695; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4696; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v104697; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4698; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v94699; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4700; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v84701; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4702; GFX8-NEXT:    s_setpc_b64 s[30:31]4703;4704; GFX900-LABEL: v_minimumnum_v8bf16:4705; GFX900:       ; %bb.0:4706; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4707; GFX900-NEXT:    v_and_b32_e32 v8, 0xffff0000, v34708; GFX900-NEXT:    v_lshrrev_b32_e32 v9, 16, v74709; GFX900-NEXT:    v_lshrrev_b32_e32 v10, 16, v34710; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v8, v84711; GFX900-NEXT:    v_and_b32_e32 v11, 0xffff0000, v74712; GFX900-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc4713; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v11, v114714; GFX900-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc4715; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v84716; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v94717; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v114718; GFX900-NEXT:    s_movk_i32 s4, 0x80004719; GFX900-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc4720; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v84721; GFX900-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc4722; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v94723; GFX900-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc4724; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v104725; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v94726; GFX900-NEXT:    v_and_b32_e32 v9, 0xffff0000, v24727; GFX900-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc4728; GFX900-NEXT:    v_lshrrev_b32_e32 v10, 16, v64729; GFX900-NEXT:    v_lshrrev_b32_e32 v11, 16, v24730; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v9, v94731; GFX900-NEXT:    v_and_b32_e32 v12, 0xffff0000, v64732; GFX900-NEXT:    v_cndmask_b32_e32 v9, v11, v10, vcc4733; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124734; GFX900-NEXT:    v_cndmask_b32_e32 v10, v10, v9, vcc4735; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v94736; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v104737; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v11, v124738; GFX900-NEXT:    v_cndmask_b32_e32 v11, v10, v9, vcc4739; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v94740; GFX900-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc4741; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v104742; GFX900-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc4743; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v114744; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v104745; GFX900-NEXT:    v_and_b32_e32 v10, 0xffff0000, v14746; GFX900-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc4747; GFX900-NEXT:    v_lshrrev_b32_e32 v11, 16, v54748; GFX900-NEXT:    v_lshrrev_b32_e32 v12, 16, v14749; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v10, v104750; GFX900-NEXT:    v_and_b32_e32 v13, 0xffff0000, v54751; GFX900-NEXT:    v_cndmask_b32_e32 v10, v12, v11, vcc4752; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v13, v134753; GFX900-NEXT:    v_cndmask_b32_e32 v11, v11, v10, vcc4754; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v104755; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v114756; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v134757; GFX900-NEXT:    v_cndmask_b32_e32 v12, v11, v10, vcc4758; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v104759; GFX900-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc4760; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114761; GFX900-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc4762; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v124763; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114764; GFX900-NEXT:    v_and_b32_e32 v11, 0xffff0000, v04765; GFX900-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc4766; GFX900-NEXT:    v_lshrrev_b32_e32 v12, 16, v44767; GFX900-NEXT:    v_lshrrev_b32_e32 v13, 16, v04768; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v11, v114769; GFX900-NEXT:    v_and_b32_e32 v14, 0xffff0000, v44770; GFX900-NEXT:    v_cndmask_b32_e32 v11, v13, v12, vcc4771; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v14, v144772; GFX900-NEXT:    v_cndmask_b32_e32 v12, v12, v11, vcc4773; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v114774; GFX900-NEXT:    v_lshlrev_b32_e32 v14, 16, v124775; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v144776; GFX900-NEXT:    v_cndmask_b32_e32 v13, v12, v11, vcc4777; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114778; GFX900-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc4779; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v124780; GFX900-NEXT:    v_cndmask_b32_e32 v11, v11, v12, vcc4781; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v134782; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v124783; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v34784; GFX900-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc4785; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124786; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v74787; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc4788; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124789; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc4790; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v74791; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v34792; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v124793; GFX900-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc4794; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v34795; GFX900-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc4796; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v74797; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc4798; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v124799; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v74800; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v24801; GFX900-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc4802; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v74803; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v64804; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc4805; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v74806; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v2, vcc4807; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v64808; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v24809; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v74810; GFX900-NEXT:    v_cndmask_b32_e32 v7, v6, v2, vcc4811; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v24812; GFX900-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc4813; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v64814; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc4815; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v74816; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v64817; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v14818; GFX900-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc4819; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v64820; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v54821; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc4822; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v64823; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v1, vcc4824; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v54825; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v14826; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v64827; GFX900-NEXT:    v_cndmask_b32_e32 v6, v5, v1, vcc4828; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v14829; GFX900-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc4830; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v54831; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc4832; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v64833; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v54834; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v04835; GFX900-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc4836; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v54837; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v44838; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc4839; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v54840; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v0, vcc4841; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v44842; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v04843; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v54844; GFX900-NEXT:    v_cndmask_b32_e32 v5, v4, v0, vcc4845; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v04846; GFX900-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc4847; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v44848; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc4849; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v54850; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v44851; GFX900-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc4852; GFX900-NEXT:    s_mov_b32 s4, 0x50401004853; GFX900-NEXT:    v_perm_b32 v0, v11, v0, s44854; GFX900-NEXT:    v_perm_b32 v1, v10, v1, s44855; GFX900-NEXT:    v_perm_b32 v2, v9, v2, s44856; GFX900-NEXT:    v_perm_b32 v3, v8, v3, s44857; GFX900-NEXT:    s_setpc_b64 s[30:31]4858;4859; GFX950-LABEL: v_minimumnum_v8bf16:4860; GFX950:       ; %bb.0:4861; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4862; GFX950-NEXT:    v_and_b32_e32 v8, 0xffff0000, v34863; GFX950-NEXT:    v_lshrrev_b32_e32 v9, 16, v74864; GFX950-NEXT:    v_lshrrev_b32_e32 v10, 16, v34865; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v8, v84866; GFX950-NEXT:    v_and_b32_e32 v11, 0xffff0000, v74867; GFX950-NEXT:    s_movk_i32 s0, 0x80004868; GFX950-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc4869; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v11, v114870; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v84871; GFX950-NEXT:    v_and_b32_e32 v12, 0xffff0000, v64872; GFX950-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc4873; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v94874; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v114875; GFX950-NEXT:    v_lshrrev_b32_e32 v11, 16, v24876; GFX950-NEXT:    v_and_b32_e32 v13, 0xffff0000, v54877; GFX950-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc4878; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v84879; GFX950-NEXT:    v_and_b32_e32 v14, 0xffff0000, v44880; GFX950-NEXT:    s_nop 04881; GFX950-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc4882; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v94883; GFX950-NEXT:    s_nop 14884; GFX950-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc4885; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v104886; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v94887; GFX950-NEXT:    v_and_b32_e32 v9, 0xffff0000, v24888; GFX950-NEXT:    s_nop 04889; GFX950-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc4890; GFX950-NEXT:    v_lshrrev_b32_e32 v10, 16, v64891; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v9, v94892; GFX950-NEXT:    s_nop 14893; GFX950-NEXT:    v_cndmask_b32_e32 v9, v11, v10, vcc4894; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124895; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v94896; GFX950-NEXT:    s_nop 04897; GFX950-NEXT:    v_cndmask_b32_e32 v10, v10, v9, vcc4898; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v104899; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v11, v124900; GFX950-NEXT:    v_lshrrev_b32_e32 v12, 16, v14901; GFX950-NEXT:    s_nop 04902; GFX950-NEXT:    v_cndmask_b32_e32 v11, v10, v9, vcc4903; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v94904; GFX950-NEXT:    s_nop 14905; GFX950-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc4906; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v104907; GFX950-NEXT:    s_nop 14908; GFX950-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc4909; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v114910; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v104911; GFX950-NEXT:    v_and_b32_e32 v10, 0xffff0000, v14912; GFX950-NEXT:    s_nop 04913; GFX950-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc4914; GFX950-NEXT:    v_lshrrev_b32_e32 v11, 16, v54915; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v10, v104916; GFX950-NEXT:    s_nop 14917; GFX950-NEXT:    v_cndmask_b32_e32 v10, v12, v11, vcc4918; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v13, v134919; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v104920; GFX950-NEXT:    s_nop 04921; GFX950-NEXT:    v_cndmask_b32_e32 v11, v11, v10, vcc4922; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v114923; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v134924; GFX950-NEXT:    v_lshrrev_b32_e32 v13, 16, v04925; GFX950-NEXT:    s_nop 04926; GFX950-NEXT:    v_cndmask_b32_e32 v12, v11, v10, vcc4927; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v104928; GFX950-NEXT:    s_nop 14929; GFX950-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc4930; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v114931; GFX950-NEXT:    s_nop 14932; GFX950-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc4933; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v124934; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114935; GFX950-NEXT:    v_and_b32_e32 v11, 0xffff0000, v04936; GFX950-NEXT:    s_nop 04937; GFX950-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc4938; GFX950-NEXT:    v_lshrrev_b32_e32 v12, 16, v44939; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v11, v114940; GFX950-NEXT:    s_nop 14941; GFX950-NEXT:    v_cndmask_b32_e32 v11, v13, v12, vcc4942; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v14, v144943; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v114944; GFX950-NEXT:    s_nop 04945; GFX950-NEXT:    v_cndmask_b32_e32 v12, v12, v11, vcc4946; GFX950-NEXT:    v_lshlrev_b32_e32 v14, 16, v124947; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v144948; GFX950-NEXT:    s_nop 14949; GFX950-NEXT:    v_cndmask_b32_e32 v13, v12, v11, vcc4950; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v114951; GFX950-NEXT:    s_nop 14952; GFX950-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc4953; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v124954; GFX950-NEXT:    s_nop 14955; GFX950-NEXT:    v_cndmask_b32_e32 v11, v11, v12, vcc4956; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v134957; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v124958; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v34959; GFX950-NEXT:    s_nop 04960; GFX950-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc4961; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124962; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v74963; GFX950-NEXT:    s_nop 04964; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc4965; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v12, v124966; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v34967; GFX950-NEXT:    s_nop 04968; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc4969; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v74970; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v124971; GFX950-NEXT:    s_nop 14972; GFX950-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc4973; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v34974; GFX950-NEXT:    s_nop 14975; GFX950-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc4976; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v74977; GFX950-NEXT:    s_nop 14978; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc4979; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v124980; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v74981; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v24982; GFX950-NEXT:    s_nop 04983; GFX950-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc4984; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v74985; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v64986; GFX950-NEXT:    s_nop 04987; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc4988; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v74989; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v24990; GFX950-NEXT:    s_nop 04991; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v2, vcc4992; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v64993; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v74994; GFX950-NEXT:    s_nop 14995; GFX950-NEXT:    v_cndmask_b32_e32 v7, v6, v2, vcc4996; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v24997; GFX950-NEXT:    s_nop 14998; GFX950-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc4999; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v65000; GFX950-NEXT:    s_nop 15001; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc5002; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v75003; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v65004; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v15005; GFX950-NEXT:    s_nop 05006; GFX950-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc5007; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v65008; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v55009; GFX950-NEXT:    s_nop 05010; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc5011; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v65012; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v15013; GFX950-NEXT:    s_nop 05014; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v1, vcc5015; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v55016; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v65017; GFX950-NEXT:    s_nop 15018; GFX950-NEXT:    v_cndmask_b32_e32 v6, v5, v1, vcc5019; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v15020; GFX950-NEXT:    s_nop 15021; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc5022; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v55023; GFX950-NEXT:    s_nop 15024; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc5025; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v65026; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v55027; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v05028; GFX950-NEXT:    s_nop 05029; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc5030; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v55031; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v45032; GFX950-NEXT:    s_nop 05033; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc5034; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v55035; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v05036; GFX950-NEXT:    s_nop 05037; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v0, vcc5038; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v45039; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v55040; GFX950-NEXT:    s_nop 15041; GFX950-NEXT:    v_cndmask_b32_e32 v5, v4, v0, vcc5042; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v05043; GFX950-NEXT:    s_nop 15044; GFX950-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc5045; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v45046; GFX950-NEXT:    s_mov_b32 s0, 0x50401005047; GFX950-NEXT:    v_perm_b32 v1, v10, v1, s05048; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc5049; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v55050; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v45051; GFX950-NEXT:    v_perm_b32 v2, v9, v2, s05052; GFX950-NEXT:    v_perm_b32 v3, v8, v3, s05053; GFX950-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc5054; GFX950-NEXT:    v_perm_b32 v0, v11, v0, s05055; GFX950-NEXT:    s_setpc_b64 s[30:31]5056;5057; GFX10-LABEL: v_minimumnum_v8bf16:5058; GFX10:       ; %bb.0:5059; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5060; GFX10-NEXT:    v_and_b32_e32 v8, 0xffff0000, v35061; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 16, v75062; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v35063; GFX10-NEXT:    v_and_b32_e32 v11, 0xffff0000, v75064; GFX10-NEXT:    v_lshrrev_b32_e32 v12, 16, v25065; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v85066; GFX10-NEXT:    v_and_b32_e32 v15, 0xffff0000, v65067; GFX10-NEXT:    v_lshrrev_b32_e32 v16, 16, v55068; GFX10-NEXT:    v_lshrrev_b32_e32 v17, 16, v05069; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc_lo5070; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v115071; GFX10-NEXT:    v_and_b32_e32 v10, 0xffff0000, v25072; GFX10-NEXT:    v_lshrrev_b32_e32 v11, 16, v65073; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v85074; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v8, vcc_lo5075; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v105076; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v95077; GFX10-NEXT:    v_cndmask_b32_e32 v10, v12, v11, vcc_lo5078; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v13, v145079; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v105080; GFX10-NEXT:    v_and_b32_e32 v13, 0xffff0000, v15081; GFX10-NEXT:    v_cndmask_b32_e32 v12, v9, v8, vcc_lo5082; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155083; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v10, vcc_lo5084; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v85085; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v115086; GFX10-NEXT:    v_cndmask_b32_e32 v8, v12, v8, vcc_lo5087; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v95088; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc_lo5089; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v155090; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 16, v15091; GFX10-NEXT:    v_and_b32_e32 v15, 0xffff0000, v55092; GFX10-NEXT:    v_cndmask_b32_e32 v14, v11, v10, vcc_lo5093; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135094; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v125095; GFX10-NEXT:    v_lshlrev_b32_e32 v18, 16, v145096; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc_lo5097; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v105098; GFX10-NEXT:    v_cndmask_b32_e32 v10, v14, v10, vcc_lo5099; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155100; GFX10-NEXT:    v_cndmask_b32_e32 v15, v16, v9, vcc_lo5101; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v135102; GFX10-NEXT:    v_and_b32_e32 v13, 0xffff0000, v05103; GFX10-NEXT:    v_lshrrev_b32_e32 v16, 16, v45104; GFX10-NEXT:    v_cndmask_b32_e32 v8, v12, v8, vcc_lo5105; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115106; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v155107; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc_lo5108; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v95109; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v125110; GFX10-NEXT:    v_cndmask_b32_e32 v11, v15, v9, vcc_lo5111; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135112; GFX10-NEXT:    v_and_b32_e32 v13, 0xffff0000, v45113; GFX10-NEXT:    v_cndmask_b32_e32 v12, v17, v16, vcc_lo5114; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v185115; GFX10-NEXT:    v_lshlrev_b32_e32 v17, 16, v75116; GFX10-NEXT:    v_cndmask_b32_e32 v10, v14, v10, vcc_lo5117; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v95118; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v35119; GFX10-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc_lo5120; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135121; GFX10-NEXT:    v_cndmask_b32_e32 v13, v16, v12, vcc_lo5122; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v155123; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v135124; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc_lo5125; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v125126; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v145127; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v115128; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo5129; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v165130; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v25131; GFX10-NEXT:    v_cndmask_b32_e32 v15, v13, v12, vcc_lo5132; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v175133; GFX10-NEXT:    v_lshlrev_b32_e32 v17, 16, v55134; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc_lo5135; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v145136; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v35137; GFX10-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc_lo5138; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v125139; GFX10-NEXT:    v_cndmask_b32_e32 v11, v15, v12, vcc_lo5140; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v75141; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v135142; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc_lo5143; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v125144; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v155145; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v65146; GFX10-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc_lo5147; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v165148; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo5149; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35150; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v25151; GFX10-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc_lo5152; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v135153; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v15154; GFX10-NEXT:    v_cndmask_b32_e32 v11, v15, v11, vcc_lo5155; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v145156; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v05157; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v2, vcc_lo5158; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v75159; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v65160; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo5161; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135162; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v45163; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v125164; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo5165; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155166; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v15167; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo5168; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v175169; GFX10-NEXT:    v_lshlrev_b32_e32 v17, 16, v05170; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v1, vcc_lo5171; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v16, v145172; GFX10-NEXT:    v_cndmask_b32_e32 v14, v6, v2, vcc_lo5173; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135174; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v55175; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v0, vcc_lo5176; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25177; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v45178; GFX10-NEXT:    v_cndmask_b32_e32 v2, v14, v2, vcc_lo5179; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v135180; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v145181; GFX10-NEXT:    v_cndmask_b32_e32 v13, v5, v1, vcc_lo5182; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65183; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo5184; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v17, v165185; GFX10-NEXT:    v_cndmask_b32_e32 v6, v4, v0, vcc_lo5186; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15187; GFX10-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc_lo5188; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v05189; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo5190; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55191; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo5192; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v45193; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v65194; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo5195; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v155196; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v135197; GFX10-NEXT:    v_cndmask_b32_e32 v2, v14, v2, vcc_lo5198; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v55199; GFX10-NEXT:    v_perm_b32 v2, v10, v2, 0x50401005200; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo5201; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v45202; GFX10-NEXT:    v_perm_b32 v0, v11, v0, 0x50401005203; GFX10-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc_lo5204; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v75205; GFX10-NEXT:    v_perm_b32 v1, v9, v1, 0x50401005206; GFX10-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc_lo5207; GFX10-NEXT:    v_perm_b32 v3, v8, v3, 0x50401005208; GFX10-NEXT:    s_setpc_b64 s[30:31]5209;5210; GFX11-TRUE16-LABEL: v_minimumnum_v8bf16:5211; GFX11-TRUE16:       ; %bb.0:5212; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5213; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v35214; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v75215; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, 05216; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v65217; GFX11-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v55218; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v85219; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v9, v95220; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v12.l5221; GFX11-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v25222; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l5223; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v3.h, v7.h, vcc_lo5224; GFX11-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v05225; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v45226; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v75227; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)5228; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.h, v7.h, v12.h, s05229; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5230; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v17, v175231; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v65232; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)5233; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v115234; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v17, v175235; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.l, v11.h, v12.h, vcc_lo5236; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v95237; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)5238; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v8.l, v12.h, s05239; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v8.l5240; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v10, v105241; GFX11-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v15242; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v125243; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v2.h, v6.h, vcc_lo5244; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5245; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.h, v6.h, v12.h, s05246; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5247; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v135248; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v13.h5249; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.l, v13.h, v12.h, vcc_lo5250; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v105251; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)5252; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v9.l, v12.h, s05253; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v9.l5254; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v14, v145255; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v12.l5256; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v125257; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v1.h, v5.h, vcc_lo5258; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5259; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.h, v5.h, v12.h, s05260; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5261; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v145262; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.l, v14.h, v12.h, vcc_lo5263; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155264; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v12.l5265; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)5266; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.h, v10.l, v12.h, s05267; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v10.l5268; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v16, v165269; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v35270; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v125271; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v0.h, v4.h, vcc_lo5272; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5273; GFX11-TRUE16-NEXT:    v_cndmask_b16 v15.h, v4.h, v12.h, s05274; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5275; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v155276; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.l, v15.h, v12.h, vcc_lo5277; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v165278; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v12.l5279; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)5280; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v11.l, v12.h, s05281; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v11.l5282; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v3.l, v7.l, vcc_lo5283; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v125284; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)5285; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v7.l, v16.h, s45286; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v16.h5287; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v25288; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v16, v125289; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5290; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v12.h, v16.h, s05291; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5292; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v3.l, v16.h, s45293; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v7, v75294; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v15295; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v55296; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)5297; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.h, v12.h, s05298; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v3.l5299; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v2.l, v6.l, s45300; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v12.l5301; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v16, v165302; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v45303; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v125304; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v6.l, v2.h, s55305; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v2.h5306; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5307; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v16, v165308; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, v6.h, s05309; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)5310; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v2, v125311; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v12.h, v2.h, s45312; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v12.h5313; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)5314; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v2.l, v2.h, s55315; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v7, v75316; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v05317; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v9.h, v13.h, s85318; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v1.h, v12.h, s45319; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v2.l5320; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.l, v5.l, s55321; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v12.l5322; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v9.l, v2.h, s25323; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5324; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v125325; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v5.l, v1.h, s65326; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v1.h5327; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5328; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v5.h, s45329; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s5, v1, v125330; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5331; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v12.h, v1.h, s55332; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v12.h5333; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v1.h, s65334; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v7, v75335; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5336; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v0.h, v12.h, s55337; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v1.l5338; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v4.l, s65339; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v12.l5340; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5341; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s5, 0, v125342; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v4.l, v0.h, s75343; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v0.h5344; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5345; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v4.h, s55346; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s6, v0, v125347; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v12.h5348; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)5349; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v12.h, v0.h, s65350; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v11.h5351; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s75352; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)5353; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v8.h, v11.h, s65354; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v14.h5355; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v15.h5356; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.h, v12.h, s95357; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v0.l5358; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5359; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v10.h, v14.h, s65360; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v3.h, v15.h, s75361; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v8.l, v1.h, s15362; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5363; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v125364; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v10.l, v0.h, s35365; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)5366; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v11.l, v5.l, vcc_lo5367; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v4.l, s15368; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5369;5370; GFX11-FAKE16-LABEL: v_minimumnum_v8bf16:5371; GFX11-FAKE16:       ; %bb.0:5372; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5373; GFX11-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v35374; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v75375; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v35376; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v25377; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v55378; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v85379; GFX11-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v75380; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v05381; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc_lo5382; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)5383; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v115384; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v65385; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v25386; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)5387; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v105388; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v85389; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v95390; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v12, v11, vcc_lo5391; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5392; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v13, v145393; GFX11-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v65394; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v105395; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v9, v8, vcc_lo5396; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)5397; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155398; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v10, vcc_lo5399; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v85400; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v15401; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v95402; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5403; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v115404; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v155405; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v15406; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v55407; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135408; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)5409; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc_lo5410; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v105411; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v125412; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155413; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)5414; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v16, v9, vcc_lo5415; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v135416; GFX11-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v05417; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v45418; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v12, v8, vcc_lo5419; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115420; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v155421; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v95422; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)5423; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v125424; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v145425; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135426; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v75427; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v185428; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v45429; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v95430; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35431; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)5432; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135433; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v16, v12, vcc_lo5434; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v155435; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v135436; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v145437; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo5438; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v125439; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)5440; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v165441; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v115442; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v25443; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v175444; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc_lo5445; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v145446; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35447; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v125448; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)5449; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v75450; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v135451; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc_lo5452; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5453; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v125454; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v65455; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc_lo5456; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v165457; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v155458; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35459; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)5460; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v25461; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v135462; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v15463; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v15, v11, vcc_lo5464; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v145465; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v05466; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v75467; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v55468; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5469; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v65470; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135471; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo5472; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155473; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo5474; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v175475; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)5476; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v05477; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v1, vcc_lo5478; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v16, v145479; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v125480; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v45481; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135482; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v55483; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25484; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)5485; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v45486; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v15487; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v135488; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v145489; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v5, v1, vcc_lo5490; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65491; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo5492; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v17, v165493; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v4, v0, vcc_lo5494; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15495; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc_lo5496; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v05497; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)5498; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo5499; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55500; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo5501; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v45502; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)5503; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v65504; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v155505; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v14, v2, vcc_lo5506; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v55507; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)5508; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v10, v2, 0x50401005509; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo5510; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v135511; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v11, v0, 0x50401005512; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)5513; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v45514; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc_lo5515; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v75516; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v9, v1, 0x50401005517; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc_lo5518; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5519; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v8, v3, 0x50401005520; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5521;5522; GFX12-TRUE16-LABEL: v_minimumnum_v8bf16:5523; GFX12-TRUE16:       ; %bb.0:5524; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x05525; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x05526; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x05527; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x05528; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x05529; GFX12-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v35530; GFX12-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v75531; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.l, 05532; GFX12-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v65533; GFX12-TRUE16-NEXT:    v_and_b32_e32 v14, 0xffff0000, v55534; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v85535; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v9, v95536; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v12.l5537; GFX12-TRUE16-NEXT:    v_and_b32_e32 v9, 0xffff0000, v25538; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v12.l5539; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5540; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v3.h, v7.h, vcc_lo5541; GFX12-TRUE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v05542; GFX12-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v45543; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v75544; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5545; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.h, v7.h, v12.h, s05546; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5547; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)5548; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v17, v175549; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v65550; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v115551; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)5552; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v17, v175553; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5554; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.l, v11.h, v12.h, vcc_lo5555; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v95556; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5557; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v8.l, v12.h, s05558; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v8.l5559; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v10, v105560; GFX12-TRUE16-NEXT:    v_and_b32_e32 v10, 0xffff0000, v15561; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)5562; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v125563; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5564; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v2.h, v6.h, vcc_lo5565; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5566; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.h, v6.h, v12.h, s05567; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5568; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5569; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v135570; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v13.h5571; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5572; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.l, v13.h, v12.h, vcc_lo5573; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v105574; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5575; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)5576; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v9.l, v12.h, s05577; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v9.l5578; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v14, v145579; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v12.l5580; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v125581; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5582; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v1.h, v5.h, vcc_lo5583; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5584; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5585; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.h, v5.h, v12.h, s05586; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5587; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v145588; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5589; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.l, v14.h, v12.h, vcc_lo5590; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155591; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v15.l, v12.l5592; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5593; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)5594; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.h, v10.l, v12.h, s05595; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v10.l5596; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v16, v165597; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v35598; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v125599; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5600; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v0.h, v4.h, vcc_lo5601; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5602; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5603; GFX12-TRUE16-NEXT:    v_cndmask_b16 v15.h, v4.h, v12.h, s05604; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5605; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v12, v155606; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5607; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.l, v15.h, v12.h, vcc_lo5608; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v165609; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.l, v12.l5610; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5611; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)5612; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v11.l, v12.h, s05613; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v11.l5614; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5615; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v3.l, v7.l, vcc_lo5616; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v125617; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)5618; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v7.l, v16.h, s45619; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v16.h5620; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v25621; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v16, v125622; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5623; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5624; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v12.h, v16.h, s05625; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v12.h5626; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v3.l, v16.h, s45627; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v7, v75628; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v15629; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v55630; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5631; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.h, v12.h, s05632; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v3.l5633; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v2.l, v6.l, s45634; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v12.l5635; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v16, v165636; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v45637; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v125638; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v6.l, v2.h, s55639; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v2.h5640; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)5641; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v16, v165642; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5643; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, v6.h, s05644; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v2, v125645; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5646; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v12.h, v2.h, s45647; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v12.h5648; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5649; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v2.l, v2.h, s55650; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v7, v75651; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v05652; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v9.h, v13.h, s85653; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5654; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v1.h, v12.h, s45655; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v2.l5656; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.l, v5.l, s55657; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v12.l5658; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v9.l, v2.h, s25659; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)5660; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v125661; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v5.l, v1.h, s65662; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v1.h5663; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5664; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5665; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v5.h, s45666; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s5, v1, v125667; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5668; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5669; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v12.h, v1.h, s55670; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v12.h5671; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v1.h, s65672; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v7, v75673; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5674; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5675; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v0.h, v12.h, s55676; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v1.l5677; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v4.l, s65678; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v12.l5679; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5680; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s5, 0, v125681; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v4.l, v0.h, s75682; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v0.h5683; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5684; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)5685; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v4.h, s55686; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s6, v0, v125687; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v12.h5688; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5689; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)5690; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v12.h, v0.h, s65691; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v11.h5692; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s75693; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5694; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5695; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v8.h, v11.h, s65696; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v14.h5697; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v15.h5698; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.h, v12.h, s95699; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.h, v0.l5700; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5701; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v10.h, v14.h, s65702; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v3.h, v15.h, s75703; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v8.l, v1.h, s15704; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v125705; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)5706; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v10.l, v0.h, s35707; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)5708; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v11.l, v5.l, vcc_lo5709; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)5710; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v4.l, s15711; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]5712;5713; GFX12-FAKE16-LABEL: v_minimumnum_v8bf16:5714; GFX12-FAKE16:       ; %bb.0:5715; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x05716; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x05717; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x05718; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x05719; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x05720; GFX12-FAKE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v35721; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v75722; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v35723; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v25724; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v55725; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v85726; GFX12-FAKE16-NEXT:    v_and_b32_e32 v11, 0xffff0000, v75727; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v05728; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5729; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v10, v9, vcc_lo5730; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)5731; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v115732; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v65733; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5734; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v8 :: v_dual_and_b32 v10, 0xffff0000, v25735; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)5736; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v10, v105737; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v85738; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v95739; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5740; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v12, v11, vcc_lo5741; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5742; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v13, v145743; GFX12-FAKE16-NEXT:    v_and_b32_e32 v15, 0xffff0000, v65744; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v105745; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5746; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v9, v8, vcc_lo5747; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5748; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155749; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5750; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v10, vcc_lo5751; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v85752; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5753; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v12, v8 :: v_dual_and_b32 v13, 0xffff0000, v15754; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v95755; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5756; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)5757; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v8, v9 :: v_dual_lshlrev_b32 v15, 16, v115758; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v155759; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v15760; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5761; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v11, v10 :: v_dual_and_b32 v15, 0xffff0000, v55762; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135763; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5764; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v16, vcc_lo5765; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v105766; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5767; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v14, v10 :: v_dual_lshlrev_b32 v13, 16, v125768; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155769; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5770; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v16, v9, vcc_lo5771; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5772; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v135773; GFX12-FAKE16-NEXT:    v_and_b32_e32 v13, 0xffff0000, v05774; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v16, 16, v45775; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5776; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v12, v8, vcc_lo5777; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115778; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v155779; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5780; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v10, v11 :: v_dual_lshlrev_b32 v11, 16, v95781; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5782; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v125783; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5784; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v15, v9 :: v_dual_lshlrev_b32 v18, 16, v145785; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135786; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5787; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v12, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v75788; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5789; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v185790; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5791; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v14, v10 :: v_dual_and_b32 v13, 0xffff0000, v45792; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v95793; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5794; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35795; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)5796; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135797; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5798; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v16, v12, vcc_lo5799; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v155800; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5801; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v15 :: v_dual_lshlrev_b32 v16, 16, v135802; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v145803; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5804; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo5805; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v125806; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5807; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v165808; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v115809; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5810; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v13, v12 :: v_dual_lshlrev_b32 v16, 16, v25811; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v175812; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5813; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v3, vcc_lo5814; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v145815; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5816; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_lshlrev_b32 v14, 16, v35817; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v125818; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5819; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v15, v12 :: v_dual_lshlrev_b32 v12, 16, v75820; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v135821; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5822; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)5823; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc_lo5824; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v125825; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v65826; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5827; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v7, v3, vcc_lo5828; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v165829; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5830; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v2, v6 :: v_dual_lshlrev_b32 v13, 16, v155831; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v35832; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5833; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)5834; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v12, v3 :: v_dual_lshlrev_b32 v16, 16, v25835; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v135836; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v15837; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5838; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v15, v11, vcc_lo5839; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v145840; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5841; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v6, v6, v2 :: v_dual_lshlrev_b32 v15, 16, v05842; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v75843; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v55844; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5845; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5846; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v7 :: v_dual_lshlrev_b32 v14, 16, v65847; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135848; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5849; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo5850; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v155851; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5852; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo5853; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v175854; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5855; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v05856; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5857; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v1, vcc_lo5858; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v16, v145859; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5860; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v6, v2 :: v_dual_lshlrev_b32 v7, 16, v125861; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v45862; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)5863; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v135864; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5865; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v0 :: v_dual_lshlrev_b32 v13, 16, v55866; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v25867; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v16, 16, v45868; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5869; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v14, v2 :: v_dual_lshlrev_b32 v15, 16, v15870; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5871; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v135872; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v145873; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5874; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v5, v1, vcc_lo5875; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v65876; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5877; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo5878; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v17, v165879; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5880; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v4, v0, vcc_lo5881; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15882; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5883; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc_lo5884; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v05885; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5886; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo5887; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v55888; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5889; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo5890; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v45891; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5892; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v4 :: v_dual_lshlrev_b32 v5, 16, v65893; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v155894; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5895; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v14, v2, vcc_lo5896; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)5897; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v55898; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v10, v2, 0x50401005899; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5900; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo5901; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v135902; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5903; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v11, v0, 0x50401005904; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v45905; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5906; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc_lo5907; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v75908; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)5909; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v9, v1, 0x50401005910; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)5911; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc_lo5912; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v8, v3, 0x50401005913; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]5914  %result = call <8 x bfloat> @llvm.minimumnum.v8bf16(<8 x bfloat> %x, <8 x bfloat> %y)5915  ret <8 x bfloat> %result5916}5917 5918define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) {5919; GFX7-LABEL: v_minimumnum_v16bf16:5920; GFX7:       ; %bb.0:5921; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5922; GFX7-NEXT:    v_mul_f32_e32 v11, 1.0, v115923; GFX7-NEXT:    v_mul_f32_e32 v27, 1.0, v275924; GFX7-NEXT:    v_and_b32_e32 v27, 0xffff0000, v275925; GFX7-NEXT:    v_and_b32_e32 v11, 0xffff0000, v115926; GFX7-NEXT:    v_min_f32_e32 v11, v11, v275927; GFX7-NEXT:    buffer_load_dword v27, off, s[0:3], s325928; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v65929; GFX7-NEXT:    v_mul_f32_e32 v22, 1.0, v225930; GFX7-NEXT:    v_and_b32_e32 v22, 0xffff0000, v225931; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v65932; GFX7-NEXT:    v_mul_f32_e32 v14, 1.0, v145933; GFX7-NEXT:    v_mul_f32_e32 v30, 1.0, v305934; GFX7-NEXT:    v_mul_f32_e32 v13, 1.0, v135935; GFX7-NEXT:    v_mul_f32_e32 v29, 1.0, v295936; GFX7-NEXT:    v_mul_f32_e32 v12, 1.0, v125937; GFX7-NEXT:    v_mul_f32_e32 v28, 1.0, v285938; GFX7-NEXT:    v_mul_f32_e32 v10, 1.0, v105939; GFX7-NEXT:    v_mul_f32_e32 v26, 1.0, v265940; GFX7-NEXT:    v_mul_f32_e32 v9, 1.0, v95941; GFX7-NEXT:    v_mul_f32_e32 v25, 1.0, v255942; GFX7-NEXT:    v_mul_f32_e32 v8, 1.0, v85943; GFX7-NEXT:    v_mul_f32_e32 v24, 1.0, v245944; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v75945; GFX7-NEXT:    v_mul_f32_e32 v23, 1.0, v235946; GFX7-NEXT:    v_mul_f32_e32 v15, 1.0, v155947; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v55948; GFX7-NEXT:    v_min_f32_e32 v6, v6, v225949; GFX7-NEXT:    v_mul_f32_e32 v21, 1.0, v215950; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v45951; GFX7-NEXT:    v_mul_f32_e32 v20, 1.0, v205952; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v35953; GFX7-NEXT:    v_mul_f32_e32 v19, 1.0, v195954; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v25955; GFX7-NEXT:    v_mul_f32_e32 v18, 1.0, v185956; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v15957; GFX7-NEXT:    v_mul_f32_e32 v17, 1.0, v175958; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v05959; GFX7-NEXT:    v_mul_f32_e32 v16, 1.0, v165960; GFX7-NEXT:    v_and_b32_e32 v30, 0xffff0000, v305961; GFX7-NEXT:    v_and_b32_e32 v14, 0xffff0000, v145962; GFX7-NEXT:    v_and_b32_e32 v29, 0xffff0000, v295963; GFX7-NEXT:    v_and_b32_e32 v13, 0xffff0000, v135964; GFX7-NEXT:    v_and_b32_e32 v28, 0xffff0000, v285965; GFX7-NEXT:    v_and_b32_e32 v12, 0xffff0000, v125966; GFX7-NEXT:    v_and_b32_e32 v26, 0xffff0000, v265967; GFX7-NEXT:    v_and_b32_e32 v10, 0xffff0000, v105968; GFX7-NEXT:    v_and_b32_e32 v25, 0xffff0000, v255969; GFX7-NEXT:    v_and_b32_e32 v9, 0xffff0000, v95970; GFX7-NEXT:    v_and_b32_e32 v24, 0xffff0000, v245971; GFX7-NEXT:    v_and_b32_e32 v8, 0xffff0000, v85972; GFX7-NEXT:    v_and_b32_e32 v23, 0xffff0000, v235973; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v75974; GFX7-NEXT:    v_and_b32_e32 v15, 0xffff0000, v155975; GFX7-NEXT:    v_and_b32_e32 v21, 0xffff0000, v215976; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v55977; GFX7-NEXT:    v_and_b32_e32 v20, 0xffff0000, v205978; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v45979; GFX7-NEXT:    v_and_b32_e32 v19, 0xffff0000, v195980; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v35981; GFX7-NEXT:    v_and_b32_e32 v18, 0xffff0000, v185982; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v25983; GFX7-NEXT:    v_and_b32_e32 v17, 0xffff0000, v175984; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v15985; GFX7-NEXT:    v_and_b32_e32 v16, 0xffff0000, v165986; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05987; GFX7-NEXT:    v_min_f32_e32 v14, v14, v305988; GFX7-NEXT:    v_min_f32_e32 v13, v13, v295989; GFX7-NEXT:    v_min_f32_e32 v12, v12, v285990; GFX7-NEXT:    v_min_f32_e32 v10, v10, v265991; GFX7-NEXT:    v_min_f32_e32 v9, v9, v255992; GFX7-NEXT:    v_min_f32_e32 v8, v8, v245993; GFX7-NEXT:    v_min_f32_e32 v7, v7, v235994; GFX7-NEXT:    v_min_f32_e32 v5, v5, v215995; GFX7-NEXT:    v_min_f32_e32 v4, v4, v205996; GFX7-NEXT:    v_min_f32_e32 v3, v3, v195997; GFX7-NEXT:    v_min_f32_e32 v2, v2, v185998; GFX7-NEXT:    v_min_f32_e32 v1, v1, v175999; GFX7-NEXT:    v_min_f32_e32 v0, v0, v166000; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v06001; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v16002; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v26003; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v36004; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v46005; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v56006; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v66007; GFX7-NEXT:    s_waitcnt vmcnt(0)6008; GFX7-NEXT:    v_mul_f32_e32 v22, 1.0, v276009; GFX7-NEXT:    v_and_b32_e32 v22, 0xffff0000, v226010; GFX7-NEXT:    v_min_f32_e32 v15, v15, v226011; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v76012; GFX7-NEXT:    v_and_b32_e32 v8, 0xffff0000, v86013; GFX7-NEXT:    v_and_b32_e32 v9, 0xffff0000, v96014; GFX7-NEXT:    v_and_b32_e32 v10, 0xffff0000, v106015; GFX7-NEXT:    v_and_b32_e32 v11, 0xffff0000, v116016; GFX7-NEXT:    v_and_b32_e32 v12, 0xffff0000, v126017; GFX7-NEXT:    v_and_b32_e32 v13, 0xffff0000, v136018; GFX7-NEXT:    v_and_b32_e32 v14, 0xffff0000, v146019; GFX7-NEXT:    v_and_b32_e32 v15, 0xffff0000, v156020; GFX7-NEXT:    s_setpc_b64 s[30:31]6021;6022; GFX8-LABEL: v_minimumnum_v16bf16:6023; GFX8:       ; %bb.0:6024; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6025; GFX8-NEXT:    v_and_b32_e32 v16, 0xffff0000, v76026; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v16, v166027; GFX8-NEXT:    v_lshrrev_b32_e32 v16, 16, v156028; GFX8-NEXT:    v_lshrrev_b32_e32 v17, 16, v76029; GFX8-NEXT:    v_and_b32_e32 v19, 0xffff0000, v156030; GFX8-NEXT:    v_cndmask_b32_e32 v17, v17, v16, vcc6031; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v19, v196032; GFX8-NEXT:    v_cndmask_b32_e32 v16, v16, v17, vcc6033; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v176034; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v166035; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v18, v196036; GFX8-NEXT:    s_movk_i32 s4, 0x80006037; GFX8-NEXT:    v_cndmask_b32_e32 v18, v16, v17, vcc6038; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v176039; GFX8-NEXT:    v_cndmask_b32_e32 v17, v18, v17, vcc6040; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v166041; GFX8-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc6042; GFX8-NEXT:    v_lshlrev_b32_e32 v17, 16, v186043; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v176044; GFX8-NEXT:    v_and_b32_e32 v17, 0xffff0000, v66045; GFX8-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc6046; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v17, v176047; GFX8-NEXT:    v_lshrrev_b32_e32 v17, 16, v146048; GFX8-NEXT:    v_lshrrev_b32_e32 v18, 16, v66049; GFX8-NEXT:    v_and_b32_e32 v20, 0xffff0000, v146050; GFX8-NEXT:    v_cndmask_b32_e32 v18, v18, v17, vcc6051; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v20, v206052; GFX8-NEXT:    v_cndmask_b32_e32 v17, v17, v18, vcc6053; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v186054; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v176055; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v19, v206056; GFX8-NEXT:    v_cndmask_b32_e32 v19, v17, v18, vcc6057; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v186058; GFX8-NEXT:    v_cndmask_b32_e32 v18, v19, v18, vcc6059; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v176060; GFX8-NEXT:    v_cndmask_b32_e32 v17, v18, v17, vcc6061; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v196062; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v186063; GFX8-NEXT:    v_and_b32_e32 v18, 0xffff0000, v56064; GFX8-NEXT:    v_cndmask_b32_e32 v17, v19, v17, vcc6065; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v18, v186066; GFX8-NEXT:    v_lshrrev_b32_e32 v18, 16, v136067; GFX8-NEXT:    v_lshrrev_b32_e32 v19, 16, v56068; GFX8-NEXT:    v_and_b32_e32 v21, 0xffff0000, v136069; GFX8-NEXT:    v_cndmask_b32_e32 v19, v19, v18, vcc6070; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v21, v216071; GFX8-NEXT:    v_cndmask_b32_e32 v18, v18, v19, vcc6072; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v196073; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v186074; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v20, v216075; GFX8-NEXT:    v_cndmask_b32_e32 v20, v18, v19, vcc6076; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v196077; GFX8-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc6078; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v186079; GFX8-NEXT:    v_cndmask_b32_e32 v18, v19, v18, vcc6080; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v206081; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v196082; GFX8-NEXT:    v_and_b32_e32 v19, 0xffff0000, v46083; GFX8-NEXT:    v_cndmask_b32_e32 v18, v20, v18, vcc6084; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v19, v196085; GFX8-NEXT:    v_lshrrev_b32_e32 v19, 16, v126086; GFX8-NEXT:    v_lshrrev_b32_e32 v20, 16, v46087; GFX8-NEXT:    v_and_b32_e32 v22, 0xffff0000, v126088; GFX8-NEXT:    v_cndmask_b32_e32 v20, v20, v19, vcc6089; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v22, v226090; GFX8-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc6091; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v206092; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v196093; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v21, v226094; GFX8-NEXT:    v_cndmask_b32_e32 v21, v19, v20, vcc6095; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v206096; GFX8-NEXT:    v_cndmask_b32_e32 v20, v21, v20, vcc6097; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v196098; GFX8-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc6099; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v216100; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v206101; GFX8-NEXT:    v_and_b32_e32 v20, 0xffff0000, v36102; GFX8-NEXT:    v_cndmask_b32_e32 v19, v21, v19, vcc6103; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v20, v206104; GFX8-NEXT:    v_lshrrev_b32_e32 v20, 16, v116105; GFX8-NEXT:    v_lshrrev_b32_e32 v21, 16, v36106; GFX8-NEXT:    v_and_b32_e32 v23, 0xffff0000, v116107; GFX8-NEXT:    v_cndmask_b32_e32 v21, v21, v20, vcc6108; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v23, v236109; GFX8-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc6110; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v216111; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v206112; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v22, v236113; GFX8-NEXT:    v_cndmask_b32_e32 v22, v20, v21, vcc6114; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v216115; GFX8-NEXT:    v_cndmask_b32_e32 v21, v22, v21, vcc6116; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v206117; GFX8-NEXT:    v_cndmask_b32_e32 v20, v21, v20, vcc6118; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v226119; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v216120; GFX8-NEXT:    v_and_b32_e32 v21, 0xffff0000, v26121; GFX8-NEXT:    v_cndmask_b32_e32 v20, v22, v20, vcc6122; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v21, v216123; GFX8-NEXT:    v_lshrrev_b32_e32 v21, 16, v106124; GFX8-NEXT:    v_lshrrev_b32_e32 v22, 16, v26125; GFX8-NEXT:    v_and_b32_e32 v24, 0xffff0000, v106126; GFX8-NEXT:    v_cndmask_b32_e32 v22, v22, v21, vcc6127; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246128; GFX8-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc6129; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v226130; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v216131; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v23, v246132; GFX8-NEXT:    v_cndmask_b32_e32 v23, v21, v22, vcc6133; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v226134; GFX8-NEXT:    v_cndmask_b32_e32 v22, v23, v22, vcc6135; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v216136; GFX8-NEXT:    v_cndmask_b32_e32 v21, v22, v21, vcc6137; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v236138; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v226139; GFX8-NEXT:    v_and_b32_e32 v22, 0xffff0000, v16140; GFX8-NEXT:    v_cndmask_b32_e32 v21, v23, v21, vcc6141; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v22, v226142; GFX8-NEXT:    v_lshrrev_b32_e32 v22, 16, v96143; GFX8-NEXT:    v_lshrrev_b32_e32 v23, 16, v16144; GFX8-NEXT:    v_and_b32_e32 v25, 0xffff0000, v96145; GFX8-NEXT:    v_cndmask_b32_e32 v23, v23, v22, vcc6146; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v25, v256147; GFX8-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc6148; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v236149; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v226150; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v256151; GFX8-NEXT:    v_cndmask_b32_e32 v24, v22, v23, vcc6152; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v236153; GFX8-NEXT:    v_cndmask_b32_e32 v23, v24, v23, vcc6154; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v226155; GFX8-NEXT:    v_cndmask_b32_e32 v22, v23, v22, vcc6156; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v246157; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v236158; GFX8-NEXT:    v_and_b32_e32 v23, 0xffff0000, v06159; GFX8-NEXT:    v_cndmask_b32_e32 v22, v24, v22, vcc6160; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v23, v236161; GFX8-NEXT:    v_lshrrev_b32_e32 v23, 16, v86162; GFX8-NEXT:    v_lshrrev_b32_e32 v24, 16, v06163; GFX8-NEXT:    v_and_b32_e32 v26, 0xffff0000, v86164; GFX8-NEXT:    v_cndmask_b32_e32 v24, v24, v23, vcc6165; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v26, v266166; GFX8-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc6167; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v246168; GFX8-NEXT:    v_lshlrev_b32_e32 v26, 16, v236169; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v266170; GFX8-NEXT:    v_cndmask_b32_e32 v25, v23, v24, vcc6171; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v246172; GFX8-NEXT:    v_cndmask_b32_e32 v24, v25, v24, vcc6173; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v236174; GFX8-NEXT:    v_cndmask_b32_e32 v23, v24, v23, vcc6175; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v256176; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v246177; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v76178; GFX8-NEXT:    v_cndmask_b32_e32 v23, v25, v23, vcc6179; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246180; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v156181; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc6182; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246183; GFX8-NEXT:    v_cndmask_b32_e32 v15, v15, v7, vcc6184; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v156185; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v76186; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v246187; GFX8-NEXT:    v_cndmask_b32_e32 v24, v15, v7, vcc6188; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v76189; GFX8-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc6190; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v156191; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc6192; GFX8-NEXT:    v_lshlrev_b32_e32 v15, 16, v246193; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v156194; GFX8-NEXT:    v_lshlrev_b32_e32 v15, 16, v66195; GFX8-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc6196; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v15, v156197; GFX8-NEXT:    v_lshlrev_b32_e32 v15, 16, v146198; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc6199; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v15, v156200; GFX8-NEXT:    v_cndmask_b32_e32 v14, v14, v6, vcc6201; GFX8-NEXT:    v_lshlrev_b32_e32 v15, 16, v146202; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v66203; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v156204; GFX8-NEXT:    v_cndmask_b32_e32 v15, v14, v6, vcc6205; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v66206; GFX8-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc6207; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v146208; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc6209; GFX8-NEXT:    v_lshlrev_b32_e32 v14, 16, v156210; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v146211; GFX8-NEXT:    v_lshlrev_b32_e32 v14, 16, v56212; GFX8-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc6213; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v14, v146214; GFX8-NEXT:    v_lshlrev_b32_e32 v14, 16, v136215; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc6216; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v14, v146217; GFX8-NEXT:    v_cndmask_b32_e32 v13, v13, v5, vcc6218; GFX8-NEXT:    v_lshlrev_b32_e32 v14, 16, v136219; GFX8-NEXT:    v_lshlrev_b32_e32 v15, 16, v56220; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v15, v146221; GFX8-NEXT:    v_cndmask_b32_e32 v14, v13, v5, vcc6222; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v56223; GFX8-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc6224; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v136225; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc6226; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v146227; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v136228; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v46229; GFX8-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc6230; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v13, v136231; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v126232; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc6233; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v13, v136234; GFX8-NEXT:    v_cndmask_b32_e32 v12, v12, v4, vcc6235; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v126236; GFX8-NEXT:    v_lshlrev_b32_e32 v14, 16, v46237; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v14, v136238; GFX8-NEXT:    v_cndmask_b32_e32 v13, v12, v4, vcc6239; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v46240; GFX8-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc6241; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v126242; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc6243; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v136244; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v126245; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v36246; GFX8-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc6247; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v12, v126248; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v116249; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc6250; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v12, v126251; GFX8-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc6252; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v116253; GFX8-NEXT:    v_lshlrev_b32_e32 v13, 16, v36254; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v126255; GFX8-NEXT:    v_cndmask_b32_e32 v12, v11, v3, vcc6256; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v36257; GFX8-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc6258; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v116259; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc6260; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v126261; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v116262; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v26263; GFX8-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc6264; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v11, v116265; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v106266; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc6267; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v11, v116268; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc6269; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v106270; GFX8-NEXT:    v_lshlrev_b32_e32 v12, 16, v26271; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v116272; GFX8-NEXT:    v_cndmask_b32_e32 v11, v10, v2, vcc6273; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v26274; GFX8-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc6275; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v106276; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc6277; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v116278; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v106279; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v16280; GFX8-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc6281; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v10, v106282; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v96283; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc6284; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v10, v106285; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v1, vcc6286; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v96287; GFX8-NEXT:    v_lshlrev_b32_e32 v11, 16, v16288; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v11, v106289; GFX8-NEXT:    v_cndmask_b32_e32 v10, v9, v1, vcc6290; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v16291; GFX8-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc6292; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v96293; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc6294; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v106295; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v96296; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v06297; GFX8-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc6298; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v9, v96299; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v86300; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc6301; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v9, v96302; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v0, vcc6303; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v86304; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v06305; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v96306; GFX8-NEXT:    v_cndmask_b32_e32 v9, v8, v0, vcc6307; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v06308; GFX8-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc6309; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v86310; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc6311; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v96312; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v86313; GFX8-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc6314; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v236315; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6316; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v226317; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6318; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v216319; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6320; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v206321; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6322; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v196323; GFX8-NEXT:    v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6324; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v186325; GFX8-NEXT:    v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6326; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v176327; GFX8-NEXT:    v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6328; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v166329; GFX8-NEXT:    v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6330; GFX8-NEXT:    s_setpc_b64 s[30:31]6331;6332; GFX900-LABEL: v_minimumnum_v16bf16:6333; GFX900:       ; %bb.0:6334; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6335; GFX900-NEXT:    v_and_b32_e32 v16, 0xffff0000, v76336; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v16, v166337; GFX900-NEXT:    v_lshrrev_b32_e32 v16, 16, v156338; GFX900-NEXT:    v_lshrrev_b32_e32 v17, 16, v76339; GFX900-NEXT:    v_and_b32_e32 v19, 0xffff0000, v156340; GFX900-NEXT:    v_cndmask_b32_e32 v17, v17, v16, vcc6341; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v19, v196342; GFX900-NEXT:    v_cndmask_b32_e32 v16, v16, v17, vcc6343; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v176344; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v166345; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v18, v196346; GFX900-NEXT:    s_movk_i32 s4, 0x80006347; GFX900-NEXT:    v_cndmask_b32_e32 v18, v16, v17, vcc6348; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v176349; GFX900-NEXT:    v_cndmask_b32_e32 v17, v18, v17, vcc6350; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v166351; GFX900-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc6352; GFX900-NEXT:    v_lshlrev_b32_e32 v17, 16, v186353; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v176354; GFX900-NEXT:    v_and_b32_e32 v17, 0xffff0000, v66355; GFX900-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc6356; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v17, v176357; GFX900-NEXT:    v_lshrrev_b32_e32 v17, 16, v146358; GFX900-NEXT:    v_lshrrev_b32_e32 v18, 16, v66359; GFX900-NEXT:    v_and_b32_e32 v20, 0xffff0000, v146360; GFX900-NEXT:    v_cndmask_b32_e32 v18, v18, v17, vcc6361; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v20, v206362; GFX900-NEXT:    v_cndmask_b32_e32 v17, v17, v18, vcc6363; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v186364; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v176365; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v19, v206366; GFX900-NEXT:    v_cndmask_b32_e32 v19, v17, v18, vcc6367; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v186368; GFX900-NEXT:    v_cndmask_b32_e32 v18, v19, v18, vcc6369; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v176370; GFX900-NEXT:    v_cndmask_b32_e32 v17, v18, v17, vcc6371; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v196372; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v186373; GFX900-NEXT:    v_and_b32_e32 v18, 0xffff0000, v56374; GFX900-NEXT:    v_cndmask_b32_e32 v17, v19, v17, vcc6375; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v18, v186376; GFX900-NEXT:    v_lshrrev_b32_e32 v18, 16, v136377; GFX900-NEXT:    v_lshrrev_b32_e32 v19, 16, v56378; GFX900-NEXT:    v_and_b32_e32 v21, 0xffff0000, v136379; GFX900-NEXT:    v_cndmask_b32_e32 v19, v19, v18, vcc6380; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v21, v216381; GFX900-NEXT:    v_cndmask_b32_e32 v18, v18, v19, vcc6382; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v196383; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v186384; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v20, v216385; GFX900-NEXT:    v_cndmask_b32_e32 v20, v18, v19, vcc6386; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v196387; GFX900-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc6388; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v186389; GFX900-NEXT:    v_cndmask_b32_e32 v18, v19, v18, vcc6390; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v206391; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v196392; GFX900-NEXT:    v_and_b32_e32 v19, 0xffff0000, v46393; GFX900-NEXT:    v_cndmask_b32_e32 v18, v20, v18, vcc6394; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v19, v196395; GFX900-NEXT:    v_lshrrev_b32_e32 v19, 16, v126396; GFX900-NEXT:    v_lshrrev_b32_e32 v20, 16, v46397; GFX900-NEXT:    v_and_b32_e32 v22, 0xffff0000, v126398; GFX900-NEXT:    v_cndmask_b32_e32 v20, v20, v19, vcc6399; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v22, v226400; GFX900-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc6401; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v206402; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v196403; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v21, v226404; GFX900-NEXT:    v_cndmask_b32_e32 v21, v19, v20, vcc6405; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v206406; GFX900-NEXT:    v_cndmask_b32_e32 v20, v21, v20, vcc6407; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v196408; GFX900-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc6409; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v216410; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v206411; GFX900-NEXT:    v_and_b32_e32 v20, 0xffff0000, v36412; GFX900-NEXT:    v_cndmask_b32_e32 v19, v21, v19, vcc6413; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v20, v206414; GFX900-NEXT:    v_lshrrev_b32_e32 v20, 16, v116415; GFX900-NEXT:    v_lshrrev_b32_e32 v21, 16, v36416; GFX900-NEXT:    v_and_b32_e32 v23, 0xffff0000, v116417; GFX900-NEXT:    v_cndmask_b32_e32 v21, v21, v20, vcc6418; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v23, v236419; GFX900-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc6420; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v216421; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v206422; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v22, v236423; GFX900-NEXT:    v_cndmask_b32_e32 v22, v20, v21, vcc6424; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v216425; GFX900-NEXT:    v_cndmask_b32_e32 v21, v22, v21, vcc6426; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v206427; GFX900-NEXT:    v_cndmask_b32_e32 v20, v21, v20, vcc6428; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v226429; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v216430; GFX900-NEXT:    v_and_b32_e32 v21, 0xffff0000, v26431; GFX900-NEXT:    v_cndmask_b32_e32 v20, v22, v20, vcc6432; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v21, v216433; GFX900-NEXT:    v_lshrrev_b32_e32 v21, 16, v106434; GFX900-NEXT:    v_lshrrev_b32_e32 v22, 16, v26435; GFX900-NEXT:    v_and_b32_e32 v24, 0xffff0000, v106436; GFX900-NEXT:    v_cndmask_b32_e32 v22, v22, v21, vcc6437; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246438; GFX900-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc6439; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v226440; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v216441; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v23, v246442; GFX900-NEXT:    v_cndmask_b32_e32 v23, v21, v22, vcc6443; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v226444; GFX900-NEXT:    v_cndmask_b32_e32 v22, v23, v22, vcc6445; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v216446; GFX900-NEXT:    v_cndmask_b32_e32 v21, v22, v21, vcc6447; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v236448; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v226449; GFX900-NEXT:    v_and_b32_e32 v22, 0xffff0000, v16450; GFX900-NEXT:    v_cndmask_b32_e32 v21, v23, v21, vcc6451; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v22, v226452; GFX900-NEXT:    v_lshrrev_b32_e32 v22, 16, v96453; GFX900-NEXT:    v_lshrrev_b32_e32 v23, 16, v16454; GFX900-NEXT:    v_and_b32_e32 v25, 0xffff0000, v96455; GFX900-NEXT:    v_cndmask_b32_e32 v23, v23, v22, vcc6456; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v25, v256457; GFX900-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc6458; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v236459; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v226460; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v256461; GFX900-NEXT:    v_cndmask_b32_e32 v24, v22, v23, vcc6462; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v236463; GFX900-NEXT:    v_cndmask_b32_e32 v23, v24, v23, vcc6464; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v226465; GFX900-NEXT:    v_cndmask_b32_e32 v22, v23, v22, vcc6466; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v246467; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v236468; GFX900-NEXT:    v_and_b32_e32 v23, 0xffff0000, v06469; GFX900-NEXT:    v_cndmask_b32_e32 v22, v24, v22, vcc6470; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v23, v236471; GFX900-NEXT:    v_lshrrev_b32_e32 v23, 16, v86472; GFX900-NEXT:    v_lshrrev_b32_e32 v24, 16, v06473; GFX900-NEXT:    v_and_b32_e32 v26, 0xffff0000, v86474; GFX900-NEXT:    v_cndmask_b32_e32 v24, v24, v23, vcc6475; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v26, v266476; GFX900-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc6477; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v246478; GFX900-NEXT:    v_lshlrev_b32_e32 v26, 16, v236479; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v266480; GFX900-NEXT:    v_cndmask_b32_e32 v25, v23, v24, vcc6481; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v246482; GFX900-NEXT:    v_cndmask_b32_e32 v24, v25, v24, vcc6483; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v236484; GFX900-NEXT:    v_cndmask_b32_e32 v23, v24, v23, vcc6485; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v256486; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v246487; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v76488; GFX900-NEXT:    v_cndmask_b32_e32 v23, v25, v23, vcc6489; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246490; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v156491; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc6492; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246493; GFX900-NEXT:    v_cndmask_b32_e32 v15, v15, v7, vcc6494; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v156495; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v76496; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v246497; GFX900-NEXT:    v_cndmask_b32_e32 v24, v15, v7, vcc6498; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v76499; GFX900-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc6500; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v156501; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc6502; GFX900-NEXT:    v_lshlrev_b32_e32 v15, 16, v246503; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v156504; GFX900-NEXT:    v_lshlrev_b32_e32 v15, 16, v66505; GFX900-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc6506; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v15, v156507; GFX900-NEXT:    v_lshlrev_b32_e32 v15, 16, v146508; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc6509; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v15, v156510; GFX900-NEXT:    v_cndmask_b32_e32 v14, v14, v6, vcc6511; GFX900-NEXT:    v_lshlrev_b32_e32 v15, 16, v146512; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v66513; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v156514; GFX900-NEXT:    v_cndmask_b32_e32 v15, v14, v6, vcc6515; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v66516; GFX900-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc6517; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v146518; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc6519; GFX900-NEXT:    v_lshlrev_b32_e32 v14, 16, v156520; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v146521; GFX900-NEXT:    v_lshlrev_b32_e32 v14, 16, v56522; GFX900-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc6523; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v14, v146524; GFX900-NEXT:    v_lshlrev_b32_e32 v14, 16, v136525; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc6526; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v14, v146527; GFX900-NEXT:    v_cndmask_b32_e32 v13, v13, v5, vcc6528; GFX900-NEXT:    v_lshlrev_b32_e32 v14, 16, v136529; GFX900-NEXT:    v_lshlrev_b32_e32 v15, 16, v56530; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v15, v146531; GFX900-NEXT:    v_cndmask_b32_e32 v14, v13, v5, vcc6532; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v56533; GFX900-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc6534; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v136535; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc6536; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v146537; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v136538; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v46539; GFX900-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc6540; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v13, v136541; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v126542; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc6543; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v13, v136544; GFX900-NEXT:    v_cndmask_b32_e32 v12, v12, v4, vcc6545; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v126546; GFX900-NEXT:    v_lshlrev_b32_e32 v14, 16, v46547; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v14, v136548; GFX900-NEXT:    v_cndmask_b32_e32 v13, v12, v4, vcc6549; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v46550; GFX900-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc6551; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v126552; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc6553; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v136554; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v126555; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v36556; GFX900-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc6557; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v12, v126558; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v116559; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc6560; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v12, v126561; GFX900-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc6562; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v116563; GFX900-NEXT:    v_lshlrev_b32_e32 v13, 16, v36564; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v126565; GFX900-NEXT:    v_cndmask_b32_e32 v12, v11, v3, vcc6566; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v36567; GFX900-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc6568; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v116569; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc6570; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v126571; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v116572; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v26573; GFX900-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc6574; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v11, v116575; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v106576; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc6577; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v11, v116578; GFX900-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc6579; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v106580; GFX900-NEXT:    v_lshlrev_b32_e32 v12, 16, v26581; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v116582; GFX900-NEXT:    v_cndmask_b32_e32 v11, v10, v2, vcc6583; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v26584; GFX900-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc6585; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v106586; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc6587; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v116588; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v106589; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v16590; GFX900-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc6591; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v10, v106592; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v96593; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc6594; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v10, v106595; GFX900-NEXT:    v_cndmask_b32_e32 v9, v9, v1, vcc6596; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v96597; GFX900-NEXT:    v_lshlrev_b32_e32 v11, 16, v16598; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v11, v106599; GFX900-NEXT:    v_cndmask_b32_e32 v10, v9, v1, vcc6600; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v16601; GFX900-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc6602; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v96603; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc6604; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v106605; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v96606; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v06607; GFX900-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc6608; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v9, v96609; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v86610; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc6611; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v9, v96612; GFX900-NEXT:    v_cndmask_b32_e32 v8, v8, v0, vcc6613; GFX900-NEXT:    v_lshlrev_b32_e32 v9, 16, v86614; GFX900-NEXT:    v_lshlrev_b32_e32 v10, 16, v06615; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v96616; GFX900-NEXT:    v_cndmask_b32_e32 v9, v8, v0, vcc6617; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v06618; GFX900-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc6619; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v86620; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc6621; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 16, v96622; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v86623; GFX900-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc6624; GFX900-NEXT:    s_mov_b32 s4, 0x50401006625; GFX900-NEXT:    v_perm_b32 v0, v23, v0, s46626; GFX900-NEXT:    v_perm_b32 v1, v22, v1, s46627; GFX900-NEXT:    v_perm_b32 v2, v21, v2, s46628; GFX900-NEXT:    v_perm_b32 v3, v20, v3, s46629; GFX900-NEXT:    v_perm_b32 v4, v19, v4, s46630; GFX900-NEXT:    v_perm_b32 v5, v18, v5, s46631; GFX900-NEXT:    v_perm_b32 v6, v17, v6, s46632; GFX900-NEXT:    v_perm_b32 v7, v16, v7, s46633; GFX900-NEXT:    s_setpc_b64 s[30:31]6634;6635; GFX950-LABEL: v_minimumnum_v16bf16:6636; GFX950:       ; %bb.0:6637; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6638; GFX950-NEXT:    v_and_b32_e32 v16, 0xffff0000, v76639; GFX950-NEXT:    v_lshrrev_b32_e32 v17, 16, v156640; GFX950-NEXT:    v_lshrrev_b32_e32 v18, 16, v76641; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v16, v166642; GFX950-NEXT:    v_and_b32_e32 v19, 0xffff0000, v156643; GFX950-NEXT:    s_movk_i32 s0, 0x80006644; GFX950-NEXT:    v_cndmask_b32_e32 v16, v18, v17, vcc6645; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v19, v196646; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v166647; GFX950-NEXT:    v_and_b32_e32 v20, 0xffff0000, v146648; GFX950-NEXT:    v_cndmask_b32_e32 v17, v17, v16, vcc6649; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v176650; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v18, v196651; GFX950-NEXT:    v_lshrrev_b32_e32 v19, 16, v66652; GFX950-NEXT:    v_and_b32_e32 v21, 0xffff0000, v136653; GFX950-NEXT:    v_cndmask_b32_e32 v18, v17, v16, vcc6654; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v166655; GFX950-NEXT:    v_and_b32_e32 v22, 0xffff0000, v126656; GFX950-NEXT:    v_and_b32_e32 v23, 0xffff0000, v116657; GFX950-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc6658; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v176659; GFX950-NEXT:    v_and_b32_e32 v24, 0xffff0000, v106660; GFX950-NEXT:    v_and_b32_e32 v25, 0xffff0000, v96661; GFX950-NEXT:    v_cndmask_b32_e32 v16, v16, v17, vcc6662; GFX950-NEXT:    v_lshlrev_b32_e32 v17, 16, v186663; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v176664; GFX950-NEXT:    v_and_b32_e32 v17, 0xffff0000, v66665; GFX950-NEXT:    v_and_b32_e32 v26, 0xffff0000, v86666; GFX950-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc6667; GFX950-NEXT:    v_lshrrev_b32_e32 v18, 16, v146668; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v17, v176669; GFX950-NEXT:    s_nop 16670; GFX950-NEXT:    v_cndmask_b32_e32 v17, v19, v18, vcc6671; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v20, v206672; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v176673; GFX950-NEXT:    s_nop 06674; GFX950-NEXT:    v_cndmask_b32_e32 v18, v18, v17, vcc6675; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v186676; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v19, v206677; GFX950-NEXT:    v_lshrrev_b32_e32 v20, 16, v56678; GFX950-NEXT:    s_nop 06679; GFX950-NEXT:    v_cndmask_b32_e32 v19, v18, v17, vcc6680; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v176681; GFX950-NEXT:    s_nop 16682; GFX950-NEXT:    v_cndmask_b32_e32 v17, v19, v17, vcc6683; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v186684; GFX950-NEXT:    s_nop 16685; GFX950-NEXT:    v_cndmask_b32_e32 v17, v17, v18, vcc6686; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v196687; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v186688; GFX950-NEXT:    v_and_b32_e32 v18, 0xffff0000, v56689; GFX950-NEXT:    s_nop 06690; GFX950-NEXT:    v_cndmask_b32_e32 v17, v19, v17, vcc6691; GFX950-NEXT:    v_lshrrev_b32_e32 v19, 16, v136692; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v18, v186693; GFX950-NEXT:    s_nop 16694; GFX950-NEXT:    v_cndmask_b32_e32 v18, v20, v19, vcc6695; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v21, v216696; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v186697; GFX950-NEXT:    s_nop 06698; GFX950-NEXT:    v_cndmask_b32_e32 v19, v19, v18, vcc6699; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v196700; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v20, v216701; GFX950-NEXT:    v_lshrrev_b32_e32 v21, 16, v46702; GFX950-NEXT:    s_nop 06703; GFX950-NEXT:    v_cndmask_b32_e32 v20, v19, v18, vcc6704; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v186705; GFX950-NEXT:    s_nop 16706; GFX950-NEXT:    v_cndmask_b32_e32 v18, v20, v18, vcc6707; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v196708; GFX950-NEXT:    s_nop 16709; GFX950-NEXT:    v_cndmask_b32_e32 v18, v18, v19, vcc6710; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v206711; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v196712; GFX950-NEXT:    v_and_b32_e32 v19, 0xffff0000, v46713; GFX950-NEXT:    s_nop 06714; GFX950-NEXT:    v_cndmask_b32_e32 v18, v20, v18, vcc6715; GFX950-NEXT:    v_lshrrev_b32_e32 v20, 16, v126716; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v19, v196717; GFX950-NEXT:    s_nop 16718; GFX950-NEXT:    v_cndmask_b32_e32 v19, v21, v20, vcc6719; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v22, v226720; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v196721; GFX950-NEXT:    s_nop 06722; GFX950-NEXT:    v_cndmask_b32_e32 v20, v20, v19, vcc6723; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v206724; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v21, v226725; GFX950-NEXT:    v_lshrrev_b32_e32 v22, 16, v36726; GFX950-NEXT:    s_nop 06727; GFX950-NEXT:    v_cndmask_b32_e32 v21, v20, v19, vcc6728; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v196729; GFX950-NEXT:    s_nop 16730; GFX950-NEXT:    v_cndmask_b32_e32 v19, v21, v19, vcc6731; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v206732; GFX950-NEXT:    s_nop 16733; GFX950-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc6734; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v216735; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v206736; GFX950-NEXT:    v_and_b32_e32 v20, 0xffff0000, v36737; GFX950-NEXT:    s_nop 06738; GFX950-NEXT:    v_cndmask_b32_e32 v19, v21, v19, vcc6739; GFX950-NEXT:    v_lshrrev_b32_e32 v21, 16, v116740; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v20, v206741; GFX950-NEXT:    s_nop 16742; GFX950-NEXT:    v_cndmask_b32_e32 v20, v22, v21, vcc6743; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v23, v236744; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v206745; GFX950-NEXT:    s_nop 06746; GFX950-NEXT:    v_cndmask_b32_e32 v21, v21, v20, vcc6747; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v216748; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v22, v236749; GFX950-NEXT:    v_lshrrev_b32_e32 v23, 16, v26750; GFX950-NEXT:    s_nop 06751; GFX950-NEXT:    v_cndmask_b32_e32 v22, v21, v20, vcc6752; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v206753; GFX950-NEXT:    s_nop 16754; GFX950-NEXT:    v_cndmask_b32_e32 v20, v22, v20, vcc6755; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v216756; GFX950-NEXT:    s_nop 16757; GFX950-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc6758; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v226759; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v216760; GFX950-NEXT:    v_and_b32_e32 v21, 0xffff0000, v26761; GFX950-NEXT:    s_nop 06762; GFX950-NEXT:    v_cndmask_b32_e32 v20, v22, v20, vcc6763; GFX950-NEXT:    v_lshrrev_b32_e32 v22, 16, v106764; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v21, v216765; GFX950-NEXT:    s_nop 16766; GFX950-NEXT:    v_cndmask_b32_e32 v21, v23, v22, vcc6767; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246768; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v216769; GFX950-NEXT:    s_nop 06770; GFX950-NEXT:    v_cndmask_b32_e32 v22, v22, v21, vcc6771; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v226772; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v23, v246773; GFX950-NEXT:    v_lshrrev_b32_e32 v24, 16, v16774; GFX950-NEXT:    s_nop 06775; GFX950-NEXT:    v_cndmask_b32_e32 v23, v22, v21, vcc6776; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v216777; GFX950-NEXT:    s_nop 16778; GFX950-NEXT:    v_cndmask_b32_e32 v21, v23, v21, vcc6779; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v226780; GFX950-NEXT:    s_nop 16781; GFX950-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc6782; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v236783; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v226784; GFX950-NEXT:    v_and_b32_e32 v22, 0xffff0000, v16785; GFX950-NEXT:    s_nop 06786; GFX950-NEXT:    v_cndmask_b32_e32 v21, v23, v21, vcc6787; GFX950-NEXT:    v_lshrrev_b32_e32 v23, 16, v96788; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v22, v226789; GFX950-NEXT:    s_nop 16790; GFX950-NEXT:    v_cndmask_b32_e32 v22, v24, v23, vcc6791; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v25, v256792; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v226793; GFX950-NEXT:    s_nop 06794; GFX950-NEXT:    v_cndmask_b32_e32 v23, v23, v22, vcc6795; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v236796; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v256797; GFX950-NEXT:    v_lshrrev_b32_e32 v25, 16, v06798; GFX950-NEXT:    s_nop 06799; GFX950-NEXT:    v_cndmask_b32_e32 v24, v23, v22, vcc6800; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v226801; GFX950-NEXT:    s_nop 16802; GFX950-NEXT:    v_cndmask_b32_e32 v22, v24, v22, vcc6803; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v236804; GFX950-NEXT:    s_nop 16805; GFX950-NEXT:    v_cndmask_b32_e32 v22, v22, v23, vcc6806; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v246807; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v236808; GFX950-NEXT:    v_and_b32_e32 v23, 0xffff0000, v06809; GFX950-NEXT:    s_nop 06810; GFX950-NEXT:    v_cndmask_b32_e32 v22, v24, v22, vcc6811; GFX950-NEXT:    v_lshrrev_b32_e32 v24, 16, v86812; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v23, v236813; GFX950-NEXT:    s_nop 16814; GFX950-NEXT:    v_cndmask_b32_e32 v23, v25, v24, vcc6815; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v26, v266816; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v236817; GFX950-NEXT:    s_nop 06818; GFX950-NEXT:    v_cndmask_b32_e32 v24, v24, v23, vcc6819; GFX950-NEXT:    v_lshlrev_b32_e32 v26, 16, v246820; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v266821; GFX950-NEXT:    s_nop 16822; GFX950-NEXT:    v_cndmask_b32_e32 v25, v24, v23, vcc6823; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v236824; GFX950-NEXT:    s_nop 16825; GFX950-NEXT:    v_cndmask_b32_e32 v23, v25, v23, vcc6826; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v246827; GFX950-NEXT:    s_nop 16828; GFX950-NEXT:    v_cndmask_b32_e32 v23, v23, v24, vcc6829; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v256830; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v246831; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v76832; GFX950-NEXT:    s_nop 06833; GFX950-NEXT:    v_cndmask_b32_e32 v23, v25, v23, vcc6834; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246835; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v156836; GFX950-NEXT:    s_nop 06837; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc6838; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v24, v246839; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v76840; GFX950-NEXT:    s_nop 06841; GFX950-NEXT:    v_cndmask_b32_e32 v15, v15, v7, vcc6842; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v156843; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v246844; GFX950-NEXT:    s_nop 16845; GFX950-NEXT:    v_cndmask_b32_e32 v24, v15, v7, vcc6846; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v76847; GFX950-NEXT:    s_nop 16848; GFX950-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc6849; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v156850; GFX950-NEXT:    s_nop 16851; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc6852; GFX950-NEXT:    v_lshlrev_b32_e32 v15, 16, v246853; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v156854; GFX950-NEXT:    v_lshlrev_b32_e32 v15, 16, v66855; GFX950-NEXT:    s_nop 06856; GFX950-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc6857; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v15, v156858; GFX950-NEXT:    v_lshlrev_b32_e32 v15, 16, v146859; GFX950-NEXT:    s_nop 06860; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc6861; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v15, v156862; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v66863; GFX950-NEXT:    s_nop 06864; GFX950-NEXT:    v_cndmask_b32_e32 v14, v14, v6, vcc6865; GFX950-NEXT:    v_lshlrev_b32_e32 v15, 16, v146866; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v156867; GFX950-NEXT:    s_nop 16868; GFX950-NEXT:    v_cndmask_b32_e32 v15, v14, v6, vcc6869; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v66870; GFX950-NEXT:    s_nop 16871; GFX950-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc6872; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v146873; GFX950-NEXT:    s_nop 16874; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc6875; GFX950-NEXT:    v_lshlrev_b32_e32 v14, 16, v156876; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v146877; GFX950-NEXT:    v_lshlrev_b32_e32 v14, 16, v56878; GFX950-NEXT:    s_nop 06879; GFX950-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc6880; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v14, v146881; GFX950-NEXT:    v_lshlrev_b32_e32 v14, 16, v136882; GFX950-NEXT:    s_nop 06883; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc6884; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v14, v146885; GFX950-NEXT:    v_lshlrev_b32_e32 v15, 16, v56886; GFX950-NEXT:    s_nop 06887; GFX950-NEXT:    v_cndmask_b32_e32 v13, v13, v5, vcc6888; GFX950-NEXT:    v_lshlrev_b32_e32 v14, 16, v136889; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v15, v146890; GFX950-NEXT:    s_nop 16891; GFX950-NEXT:    v_cndmask_b32_e32 v14, v13, v5, vcc6892; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v56893; GFX950-NEXT:    s_nop 16894; GFX950-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc6895; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v136896; GFX950-NEXT:    s_nop 16897; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc6898; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v146899; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v136900; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v46901; GFX950-NEXT:    s_nop 06902; GFX950-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc6903; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v13, v136904; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v126905; GFX950-NEXT:    s_nop 06906; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc6907; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v13, v136908; GFX950-NEXT:    v_lshlrev_b32_e32 v14, 16, v46909; GFX950-NEXT:    s_nop 06910; GFX950-NEXT:    v_cndmask_b32_e32 v12, v12, v4, vcc6911; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v126912; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v14, v136913; GFX950-NEXT:    s_nop 16914; GFX950-NEXT:    v_cndmask_b32_e32 v13, v12, v4, vcc6915; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v46916; GFX950-NEXT:    s_nop 16917; GFX950-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc6918; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v126919; GFX950-NEXT:    s_nop 16920; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc6921; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v136922; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v126923; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v36924; GFX950-NEXT:    s_nop 06925; GFX950-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc6926; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v12, v126927; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v116928; GFX950-NEXT:    s_nop 06929; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc6930; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v12, v126931; GFX950-NEXT:    v_lshlrev_b32_e32 v13, 16, v36932; GFX950-NEXT:    s_nop 06933; GFX950-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc6934; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v116935; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v13, v126936; GFX950-NEXT:    s_nop 16937; GFX950-NEXT:    v_cndmask_b32_e32 v12, v11, v3, vcc6938; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v36939; GFX950-NEXT:    s_nop 16940; GFX950-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc6941; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v116942; GFX950-NEXT:    s_nop 16943; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc6944; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v126945; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v116946; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v26947; GFX950-NEXT:    s_nop 06948; GFX950-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc6949; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v11, v116950; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v106951; GFX950-NEXT:    s_nop 06952; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc6953; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v11, v116954; GFX950-NEXT:    v_lshlrev_b32_e32 v12, 16, v26955; GFX950-NEXT:    s_nop 06956; GFX950-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc6957; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v106958; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v12, v116959; GFX950-NEXT:    s_nop 16960; GFX950-NEXT:    v_cndmask_b32_e32 v11, v10, v2, vcc6961; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v26962; GFX950-NEXT:    s_nop 16963; GFX950-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc6964; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v106965; GFX950-NEXT:    s_nop 16966; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc6967; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v116968; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v106969; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v16970; GFX950-NEXT:    s_nop 06971; GFX950-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc6972; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v10, v106973; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v96974; GFX950-NEXT:    s_nop 06975; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc6976; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v10, v106977; GFX950-NEXT:    v_lshlrev_b32_e32 v11, 16, v16978; GFX950-NEXT:    s_nop 06979; GFX950-NEXT:    v_cndmask_b32_e32 v9, v9, v1, vcc6980; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v96981; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v11, v106982; GFX950-NEXT:    s_nop 16983; GFX950-NEXT:    v_cndmask_b32_e32 v10, v9, v1, vcc6984; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v16985; GFX950-NEXT:    s_nop 16986; GFX950-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc6987; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v96988; GFX950-NEXT:    s_nop 16989; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc6990; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v106991; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v96992; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v06993; GFX950-NEXT:    s_nop 06994; GFX950-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc6995; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v9, v96996; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v86997; GFX950-NEXT:    s_nop 06998; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc6999; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v9, v97000; GFX950-NEXT:    v_lshlrev_b32_e32 v10, 16, v07001; GFX950-NEXT:    s_nop 07002; GFX950-NEXT:    v_cndmask_b32_e32 v8, v8, v0, vcc7003; GFX950-NEXT:    v_lshlrev_b32_e32 v9, 16, v87004; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v10, v97005; GFX950-NEXT:    s_nop 17006; GFX950-NEXT:    v_cndmask_b32_e32 v9, v8, v0, vcc7007; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v07008; GFX950-NEXT:    s_nop 17009; GFX950-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc7010; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v87011; GFX950-NEXT:    s_mov_b32 s0, 0x50401007012; GFX950-NEXT:    v_perm_b32 v1, v22, v1, s07013; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc7014; GFX950-NEXT:    v_lshlrev_b32_e32 v8, 16, v97015; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v87016; GFX950-NEXT:    v_perm_b32 v2, v21, v2, s07017; GFX950-NEXT:    v_perm_b32 v3, v20, v3, s07018; GFX950-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc7019; GFX950-NEXT:    v_perm_b32 v0, v23, v0, s07020; GFX950-NEXT:    v_perm_b32 v4, v19, v4, s07021; GFX950-NEXT:    v_perm_b32 v5, v18, v5, s07022; GFX950-NEXT:    v_perm_b32 v6, v17, v6, s07023; GFX950-NEXT:    v_perm_b32 v7, v16, v7, s07024; GFX950-NEXT:    s_setpc_b64 s[30:31]7025;7026; GFX10-LABEL: v_minimumnum_v16bf16:7027; GFX10:       ; %bb.0:7028; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7029; GFX10-NEXT:    v_and_b32_e32 v16, 0xffff0000, v77030; GFX10-NEXT:    v_lshrrev_b32_e32 v17, 16, v157031; GFX10-NEXT:    v_lshrrev_b32_e32 v18, 16, v77032; GFX10-NEXT:    v_and_b32_e32 v19, 0xffff0000, v157033; GFX10-NEXT:    v_and_b32_e32 v20, 0xffff0000, v67034; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v167035; GFX10-NEXT:    v_lshrrev_b32_e32 v21, 16, v147036; GFX10-NEXT:    v_lshrrev_b32_e32 v22, 16, v67037; GFX10-NEXT:    v_and_b32_e32 v23, 0xffff0000, v137038; GFX10-NEXT:    v_lshrrev_b32_e32 v24, 16, v127039; GFX10-NEXT:    v_cndmask_b32_e32 v16, v18, v17, vcc_lo7040; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v197041; GFX10-NEXT:    v_lshrrev_b32_e32 v25, 16, v47042; GFX10-NEXT:    v_and_b32_e32 v26, 0xffff0000, v127043; GFX10-NEXT:    v_lshrrev_b32_e32 v28, 16, v17044; GFX10-NEXT:    v_lshlrev_b32_e32 v18, 16, v167045; GFX10-NEXT:    v_cndmask_b32_e32 v17, v17, v16, vcc_lo7046; GFX10-NEXT:    v_lshlrev_b32_e32 v19, 16, v177047; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v18, v197048; GFX10-NEXT:    v_and_b32_e32 v19, 0xffff0000, v147049; GFX10-NEXT:    v_cndmask_b32_e32 v18, v17, v16, vcc_lo7050; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v207051; GFX10-NEXT:    v_cndmask_b32_e32 v20, v22, v21, vcc_lo7052; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v167053; GFX10-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc_lo7054; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v197055; GFX10-NEXT:    v_cndmask_b32_e32 v19, v21, v20, vcc_lo7056; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v177057; GFX10-NEXT:    v_lshlrev_b32_e32 v21, 16, v207058; GFX10-NEXT:    v_lshlrev_b32_e32 v22, 16, v197059; GFX10-NEXT:    v_cndmask_b32_e32 v16, v16, v17, vcc_lo7060; GFX10-NEXT:    v_lshlrev_b32_e32 v17, 16, v187061; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v177062; GFX10-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc_lo7063; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v21, v227064; GFX10-NEXT:    v_and_b32_e32 v18, 0xffff0000, v57065; GFX10-NEXT:    v_lshrrev_b32_e32 v21, 16, v137066; GFX10-NEXT:    v_lshrrev_b32_e32 v22, 16, v57067; GFX10-NEXT:    v_cndmask_b32_e32 v17, v19, v20, vcc_lo7068; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v207069; GFX10-NEXT:    v_cndmask_b32_e32 v20, v17, v20, vcc_lo7070; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v187071; GFX10-NEXT:    v_cndmask_b32_e32 v18, v22, v21, vcc_lo7072; GFX10-NEXT:    v_and_b32_e32 v22, 0xffff0000, v47073; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237074; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v187075; GFX10-NEXT:    v_cndmask_b32_e32 v21, v21, v18, vcc_lo7076; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v227077; GFX10-NEXT:    v_cndmask_b32_e32 v22, v25, v24, vcc_lo7078; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v197079; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v217080; GFX10-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc_lo7081; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v267082; GFX10-NEXT:    v_cndmask_b32_e32 v20, v24, v22, vcc_lo7083; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v257084; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v177085; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v227086; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v207087; GFX10-NEXT:    v_cndmask_b32_e32 v23, v21, v18, vcc_lo7088; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v187089; GFX10-NEXT:    v_cndmask_b32_e32 v18, v23, v18, vcc_lo7090; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v247091; GFX10-NEXT:    v_and_b32_e32 v24, 0xffff0000, v37092; GFX10-NEXT:    v_cndmask_b32_e32 v17, v17, v19, vcc_lo7093; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v267094; GFX10-NEXT:    v_lshrrev_b32_e32 v25, 16, v117095; GFX10-NEXT:    v_lshrrev_b32_e32 v26, 16, v37096; GFX10-NEXT:    v_cndmask_b32_e32 v19, v20, v22, vcc_lo7097; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v217098; GFX10-NEXT:    v_lshlrev_b32_e32 v27, 16, v197099; GFX10-NEXT:    v_cndmask_b32_e32 v18, v18, v21, vcc_lo7100; GFX10-NEXT:    v_lshlrev_b32_e32 v21, 16, v237101; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v227102; GFX10-NEXT:    v_cndmask_b32_e32 v22, v19, v22, vcc_lo7103; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v217104; GFX10-NEXT:    v_cndmask_b32_e32 v18, v23, v18, vcc_lo7105; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v207106; GFX10-NEXT:    v_and_b32_e32 v23, 0xffff0000, v27107; GFX10-NEXT:    v_cndmask_b32_e32 v20, v22, v20, vcc_lo7108; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247109; GFX10-NEXT:    v_and_b32_e32 v22, 0xffff0000, v117110; GFX10-NEXT:    v_lshrrev_b32_e32 v24, 16, v107111; GFX10-NEXT:    v_cndmask_b32_e32 v21, v26, v25, vcc_lo7112; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v227113; GFX10-NEXT:    v_lshrrev_b32_e32 v26, 16, v27114; GFX10-NEXT:    v_cndmask_b32_e32 v22, v25, v21, vcc_lo7115; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237116; GFX10-NEXT:    v_and_b32_e32 v25, 0xffff0000, v107117; GFX10-NEXT:    v_cndmask_b32_e32 v23, v26, v24, vcc_lo7118; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v277119; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v227120; GFX10-NEXT:    v_lshrrev_b32_e32 v27, 16, v97121; GFX10-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo7122; GFX10-NEXT:    v_lshlrev_b32_e32 v20, 16, v217123; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v257124; GFX10-NEXT:    v_and_b32_e32 v25, 0xffff0000, v17125; GFX10-NEXT:    v_cndmask_b32_e32 v24, v24, v23, vcc_lo7126; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v20, v267127; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v237128; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v247129; GFX10-NEXT:    v_cndmask_b32_e32 v20, v22, v21, vcc_lo7130; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v257131; GFX10-NEXT:    v_cndmask_b32_e32 v25, v28, v27, vcc_lo7132; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v217133; GFX10-NEXT:    v_and_b32_e32 v28, 0xffff0000, v97134; GFX10-NEXT:    v_cndmask_b32_e32 v21, v20, v21, vcc_lo7135; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v26, v297136; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v207137; GFX10-NEXT:    v_cndmask_b32_e32 v26, v24, v23, vcc_lo7138; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v287139; GFX10-NEXT:    v_cndmask_b32_e32 v27, v27, v25, vcc_lo7140; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v227141; GFX10-NEXT:    v_lshlrev_b32_e32 v28, 16, v277142; GFX10-NEXT:    v_cndmask_b32_e32 v21, v21, v22, vcc_lo7143; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v237144; GFX10-NEXT:    v_cndmask_b32_e32 v22, v26, v23, vcc_lo7145; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v257146; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v247147; GFX10-NEXT:    v_cndmask_b32_e32 v22, v22, v24, vcc_lo7148; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v287149; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v267150; GFX10-NEXT:    v_lshlrev_b32_e32 v28, 16, v157151; GFX10-NEXT:    v_cndmask_b32_e32 v23, v27, v25, vcc_lo7152; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v297153; GFX10-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo7154; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v247155; GFX10-NEXT:    v_and_b32_e32 v24, 0xffff0000, v07156; GFX10-NEXT:    v_cndmask_b32_e32 v21, v26, v22, vcc_lo7157; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v257158; GFX10-NEXT:    v_lshrrev_b32_e32 v26, 16, v07159; GFX10-NEXT:    v_cndmask_b32_e32 v22, v23, v25, vcc_lo7160; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v277161; GFX10-NEXT:    v_lshrrev_b32_e32 v25, 16, v87162; GFX10-NEXT:    v_cndmask_b32_e32 v22, v22, v27, vcc_lo7163; GFX10-NEXT:    v_lshlrev_b32_e32 v27, 16, v77164; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247165; GFX10-NEXT:    v_cndmask_b32_e32 v24, v26, v25, vcc_lo7166; GFX10-NEXT:    v_and_b32_e32 v26, 0xffff0000, v87167; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v277168; GFX10-NEXT:    v_lshlrev_b32_e32 v27, 16, v237169; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc_lo7170; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v267171; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v247172; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v77173; GFX10-NEXT:    v_cndmask_b32_e32 v25, v25, v24, vcc_lo7174; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v287175; GFX10-NEXT:    v_cndmask_b32_e32 v15, v15, v7, vcc_lo7176; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v277177; GFX10-NEXT:    v_lshlrev_b32_e32 v27, 16, v257178; GFX10-NEXT:    v_lshlrev_b32_e32 v28, 16, v157179; GFX10-NEXT:    v_cndmask_b32_e32 v22, v23, v22, vcc_lo7180; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v67181; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237182; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v147183; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo7184; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v26, v277185; GFX10-NEXT:    v_cndmask_b32_e32 v26, v25, v24, vcc_lo7186; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v29, v287187; GFX10-NEXT:    v_lshlrev_b32_e32 v28, 16, v67188; GFX10-NEXT:    v_cndmask_b32_e32 v27, v15, v7, vcc_lo7189; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237190; GFX10-NEXT:    v_cndmask_b32_e32 v14, v14, v6, vcc_lo7191; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v247192; GFX10-NEXT:    v_cndmask_b32_e32 v23, v26, v24, vcc_lo7193; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v77194; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v147195; GFX10-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo7196; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v257197; GFX10-NEXT:    v_cndmask_b32_e32 v23, v23, v25, vcc_lo7198; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v157199; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v267200; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc_lo7201; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v28, v247202; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v277203; GFX10-NEXT:    v_cndmask_b32_e32 v15, v14, v6, vcc_lo7204; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v257205; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v137206; GFX10-NEXT:    v_cndmask_b32_e32 v23, v26, v23, vcc_lo7207; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67208; GFX10-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc_lo7209; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v247210; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v57211; GFX10-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo7212; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v147213; GFX10-NEXT:    v_perm_b32 v7, v16, v7, 0x50401007214; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo7215; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v157216; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247217; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v47218; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo7219; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v147220; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v127221; GFX10-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc_lo7222; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v257223; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v37224; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v57225; GFX10-NEXT:    v_perm_b32 v6, v17, v6, 0x50401007226; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v5, vcc_lo7227; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247228; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v137229; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo7230; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v147231; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v117232; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v4, vcc_lo7233; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v157234; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo7235; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v247236; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v127237; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v47238; GFX10-NEXT:    v_cndmask_b32_e32 v15, v13, v5, vcc_lo7239; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v147240; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc_lo7241; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v57242; GFX10-NEXT:    v_cndmask_b32_e32 v5, v15, v5, vcc_lo7243; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v247244; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v117245; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v37246; GFX10-NEXT:    v_cndmask_b32_e32 v14, v12, v4, vcc_lo7247; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v137248; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo7249; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v47250; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v157251; GFX10-NEXT:    v_cndmask_b32_e32 v4, v14, v4, vcc_lo7252; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v247253; GFX10-NEXT:    v_cndmask_b32_e32 v24, v11, v3, vcc_lo7254; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v137255; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v147256; GFX10-NEXT:    v_cndmask_b32_e32 v5, v15, v5, vcc_lo7257; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v127258; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v247259; GFX10-NEXT:    v_perm_b32 v5, v18, v5, 0x50401007260; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo7261; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v37262; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v27263; GFX10-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo7264; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v117265; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo7266; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v127267; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v107268; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v17269; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc_lo7270; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v157271; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v07272; GFX10-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo7273; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v117274; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v97275; GFX10-NEXT:    v_perm_b32 v3, v20, v3, 0x50401007276; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc_lo7277; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v127278; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v87279; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo7280; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v157281; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v27282; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v17283; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo7284; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v117285; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v107286; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v07287; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v1, vcc_lo7288; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v127289; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v97290; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v0, vcc_lo7291; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v117292; GFX10-NEXT:    v_lshlrev_b32_e32 v15, 16, v87293; GFX10-NEXT:    v_cndmask_b32_e32 v11, v10, v2, vcc_lo7294; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v24, v127295; GFX10-NEXT:    v_cndmask_b32_e32 v12, v9, v1, vcc_lo7296; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27297; GFX10-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc_lo7298; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v157299; GFX10-NEXT:    v_cndmask_b32_e32 v15, v8, v0, vcc_lo7300; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17301; GFX10-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc_lo7302; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v107303; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc_lo7304; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v07305; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v157306; GFX10-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc_lo7307; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v97308; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo7309; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v127310; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v87311; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo7312; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v97313; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v117314; GFX10-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc_lo7315; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v107316; GFX10-NEXT:    v_perm_b32 v1, v22, v1, 0x50401007317; GFX10-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc_lo7318; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v87319; GFX10-NEXT:    v_perm_b32 v0, v23, v0, 0x50401007320; GFX10-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc_lo7321; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v137322; GFX10-NEXT:    v_perm_b32 v2, v21, v2, 0x50401007323; GFX10-NEXT:    v_cndmask_b32_e32 v4, v14, v4, vcc_lo7324; GFX10-NEXT:    v_perm_b32 v4, v19, v4, 0x50401007325; GFX10-NEXT:    s_setpc_b64 s[30:31]7326;7327; GFX11-TRUE16-LABEL: v_minimumnum_v16bf16:7328; GFX11-TRUE16:       ; %bb.0:7329; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7330; GFX11-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v77331; GFX11-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v157332; GFX11-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v67333; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v147334; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v137335; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v167336; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.l, 07337; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v127338; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v20, v207339; GFX11-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v57340; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v7.h, v15.h, vcc_lo7341; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v177342; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v16.l7343; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v21, v217344; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v16.l7345; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v16.h7346; GFX11-TRUE16-NEXT:    v_cndmask_b16 v17.h, v15.h, v16.h, vcc_lo7347; GFX11-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v47348; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v22, v227349; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v16.l7350; GFX11-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v37351; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v16, v177352; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v117353; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v16.l7354; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v107355; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v16.l7356; GFX11-TRUE16-NEXT:    v_cndmask_b16 v17.l, v17.h, v16.h, vcc_lo7357; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v23, v237358; GFX11-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v27359; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v24, v247360; GFX11-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v17361; GFX11-TRUE16-NEXT:    v_cndmask_b16 v19.l, v17.l, v16.h, s07362; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v17.l7363; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v18, v187364; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v16.l7365; GFX11-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v97366; GFX11-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v07367; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v167368; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v6.h, v14.h, s07369; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v87370; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v29, v297371; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v16.l7372; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v157373; GFX11-TRUE16-NEXT:    v_cndmask_b16 v18.h, v14.h, v16.h, s17374; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v16.h7375; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v31, v317376; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v77377; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v32, v327378; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v16, v187379; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v147380; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7381; GFX11-TRUE16-NEXT:    v_cndmask_b16 v18.l, v18.h, v16.h, s07382; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v32, v327383; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v137384; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7385; GFX11-TRUE16-NEXT:    v_cndmask_b16 v19.h, v18.l, v16.h, s17386; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v18.l7387; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v20, v207388; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v32, v327389; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v127390; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)7391; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v167392; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v5.h, v13.h, s17393; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7394; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v32, v327395; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v117396; GFX11-TRUE16-NEXT:    v_cndmask_b16 v25.h, v13.h, v16.h, s27397; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v16.h7398; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7399; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v32, v327400; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v107401; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v16, v257402; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v25.h7403; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7404; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v32, v327405; GFX11-TRUE16-NEXT:    v_cndmask_b16 v20.l, v25.h, v16.h, s17406; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v97407; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)7408; GFX11-TRUE16-NEXT:    v_cndmask_b16 v20.h, v20.l, v16.h, s27409; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v20.l7410; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v21, v217411; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v32, v327412; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v16.l7413; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)7414; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v167415; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v4.h, v12.h, s27416; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7417; GFX11-TRUE16-NEXT:    v_cndmask_b16 v26.h, v12.h, v16.h, s37418; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v16.h7419; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v16, v267420; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7421; GFX11-TRUE16-NEXT:    v_cndmask_b16 v21.l, v26.h, v16.h, s27422; GFX11-TRUE16-NEXT:    v_cndmask_b16 v21.h, v21.l, v16.h, s37423; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v21.l7424; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v22, v227425; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7426; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v167427; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v3.h, v11.h, s37428; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7429; GFX11-TRUE16-NEXT:    v_cndmask_b16 v27.h, v11.h, v16.h, s47430; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v16.h7431; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s3, v16, v277432; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7433; GFX11-TRUE16-NEXT:    v_cndmask_b16 v22.l, v27.h, v16.h, s37434; GFX11-TRUE16-NEXT:    v_cndmask_b16 v22.h, v22.l, v16.h, s47435; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v22.l7436; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v23, v237437; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7438; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v167439; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v2.h, v10.h, s47440; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7441; GFX11-TRUE16-NEXT:    v_cndmask_b16 v28.h, v10.h, v16.h, s57442; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v16.h7443; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v16, v287444; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7445; GFX11-TRUE16-NEXT:    v_cndmask_b16 v23.l, v28.h, v16.h, s47446; GFX11-TRUE16-NEXT:    v_cndmask_b16 v23.h, v23.l, v16.h, s57447; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v23.l7448; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v24, v247449; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7450; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v167451; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v1.h, v9.h, s57452; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7453; GFX11-TRUE16-NEXT:    v_cndmask_b16 v29.h, v9.h, v16.h, s67454; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v16.h7455; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s5, v16, v297456; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7457; GFX11-TRUE16-NEXT:    v_cndmask_b16 v24.l, v29.h, v16.h, s57458; GFX11-TRUE16-NEXT:    v_cndmask_b16 v24.h, v24.l, v16.h, s67459; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v24.l7460; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v30, v307461; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v16.l7462; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7463; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s5, 0, v167464; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v0.h, v8.h, s67465; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7466; GFX11-TRUE16-NEXT:    v_cndmask_b16 v30.h, v8.h, v16.h, s77467; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v16.h7468; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s6, v16, v307469; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)7470; GFX11-TRUE16-NEXT:    v_cndmask_b16 v15.h, v30.h, v16.h, s67471; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v31, v317472; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v67473; GFX11-TRUE16-NEXT:    v_cndmask_b16 v25.l, v15.h, v16.h, s77474; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v15.h7475; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)7476; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v7.l, v15.l, s67477; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v16.l7478; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s6, 0, v167479; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)7480; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v15.l, v7.h, s87481; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v7.h7482; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s7, v7, v167483; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7484; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v16.h, v7.h, s77485; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v16.h7486; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v7.l, v7.h, s87487; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v31, v317488; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v57489; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7490; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.h, v6.h, v16.h, s77491; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v7.l7492; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v6.l, v14.l, s87493; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v16.l7494; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7495; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s7, 0, v167496; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v14.l, v6.h, s97497; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v6.h7498; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7499; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v7.l, v14.h, s77500; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s8, v6, v167501; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7502; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.l, v16.h, v6.h, s87503; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v16.h7504; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v6.l, v6.h, s97505; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v31, v317506; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v47507; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7508; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.h, v5.h, v16.h, s87509; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v6.l7510; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v5.l, v13.l, s97511; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v16.l7512; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7513; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s8, 0, v167514; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v13.l, v5.h, s107515; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v5.h7516; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7517; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.l, v6.l, v13.h, s87518; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s9, v5, v167519; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7520; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v16.h, v5.h, s97521; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v16.h7522; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v5.l, v5.h, s107523; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v31, v317524; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v37525; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7526; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v4.h, v16.h, s97527; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v5.l7528; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v12.l, s107529; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v16.l7530; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7531; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s9, 0, v167532; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v12.l, v4.h, s117533; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s11, 0x8000, v4.h7534; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7535; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v5.l, v12.h, s97536; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s10, v4, v167537; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7538; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v16.h, v4.h, s107539; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v16.h7540; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v4.l, v4.h, s117541; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v31, v317542; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v27543; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7544; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.h, v3.h, v16.h, s107545; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v4.l7546; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v3.l, v11.l, s117547; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v16.l7548; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7549; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s10, 0, v167550; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v11.l, v3.h, s127551; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s12, 0x8000, v3.h7552; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7553; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.l, v11.h, s107554; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s11, v3, v167555; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7556; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v16.h, v3.h, s117557; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s11, 0x8000, v16.h7558; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v3.l, v3.h, s127559; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v31, v317560; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v17561; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7562; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.h, v2.h, v16.h, s117563; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v3.l7564; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v2.l, v10.l, s127565; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v16.l7566; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7567; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s11, 0, v167568; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v10.l, v2.h, s137569; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v2.h7570; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7571; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, v10.h, s117572; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s12, v2, v167573; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)7574; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v16.h, v2.h, s127575; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s12, 0x8000, v16.h7576; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v2.l, v2.h, s137577; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v31, v317578; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v07579; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)7580; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v1.h, v16.h, s127581; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v2.l7582; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.l, v9.l, s137583; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v16.l7584; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)7585; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s12, 0, v167586; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v9.l, v1.h, s147587; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v31, v317588; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s15, 0x8000, v1.h7589; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v87590; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v9.h, s127591; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s13, v1, v167592; GFX11-TRUE16-NEXT:    v_cndmask_b16 v32.h, v0.l, v8.l, s147593; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v16.h7594; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v31, v317595; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)7596; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v16.h, v1.h, s137597; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v17.h7598; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v1.h, s157599; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)7600; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v19.l, v17.h, s137601; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v18.h7602; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v20.h, v25.h, s177603; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s15, 0x8000, v32.h7604; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v16.h, s167605; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v1.l7606; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v17.l, v0.h, vcc_lo7607; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v19.h, v18.h, s137608; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26.h7609; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v20.l, v1.h, s17610; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s13, 0, v167611; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v8.l, v32.h, s147612; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v18.l, v0.h, s07613; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v21.h, v26.h, vcc_lo7614; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v28.h7615; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27.h7616; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v32, v167617; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v0.l, s137618; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v21.l, v0.h, s27619; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v29.h7620; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v23.h, v28.h, s17621; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.l, v16.h, v32.h, s07622; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v16.h7623; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v22.h, v27.h, vcc_lo7624; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v24.h, v29.h, s27625; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30.h7626; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.l, v8.l, v32.h, s157627; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v23.l, v1.h, s47628; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v22.l, v0.h, s37629; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v24.l, v8.h, s57630; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v25.l, v30.h, vcc_lo7631; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v9.l, v16.h, s07632; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v8.l7633; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)7634; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v15.h, v0.h, s67635; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v167636; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)7637; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v8.l, v8.h, vcc_lo7638; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]7639;7640; GFX11-FAKE16-LABEL: v_minimumnum_v16bf16:7641; GFX11-FAKE16:       ; %bb.0:7642; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7643; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 16, v147644; GFX11-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v77645; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v157646; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v77647; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v67648; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 16, v127649; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v167650; GFX11-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v157651; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v47652; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v17653; GFX11-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v67654; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v17, vcc_lo7655; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v197656; GFX11-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v137657; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)7658; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v167659; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v16, vcc_lo7660; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v177661; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)7662; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v18, v197663; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v17, v16, vcc_lo7664; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v207665; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v147666; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v167667; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc_lo7668; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)7669; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v197670; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v21, v20, vcc_lo7671; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v177672; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v207673; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)7674; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v197675; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v187676; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v177677; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)7678; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc_lo7679; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v21, v227680; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 16, v137681; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v57682; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v57683; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v207684; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)7685; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v17, v20, vcc_lo7686; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v187687; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v22, v21, vcc_lo7688; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237689; GFX11-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v47690; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7691; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v187692; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v21, v18, vcc_lo7693; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v227694; GFX11-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v127695; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7696; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v217697; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v197698; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc_lo7699; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v267700; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)7701; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v24, v22, vcc_lo7702; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v257703; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v177704; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v227705; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v207706; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v187707; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)7708; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v23, v18, vcc_lo7709; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v247710; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v19, vcc_lo7711; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v267712; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v117713; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v37714; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v20, v22, vcc_lo7715; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v217716; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)7717; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v197718; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v237719; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v227720; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v19, v22, vcc_lo7721; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v217722; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v23, v18, vcc_lo7723; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v207724; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)7725; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v27726; GFX11-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v37727; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247728; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 16, v107729; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v117730; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v27731; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)7732; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v227733; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v25, v21, vcc_lo7734; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237735; GFX11-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v107736; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v26, v24, vcc_lo7737; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v277738; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v97739; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo7740; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v257741; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v17742; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)7743; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v247744; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v217745; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v227746; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v20, v267747; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v22, v21, vcc_lo7748; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v257749; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v28, v27, vcc_lo7750; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v237751; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v217752; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v20, v21, vcc_lo7753; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)7754; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v26, v297755; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v207756; GFX11-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v97757; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v287758; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v27, v25, vcc_lo7759; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v227760; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)7761; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v277762; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v237763; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v257764; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v247765; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v24, vcc_lo7766; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)7767; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v287768; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v267769; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v297770; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo7771; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v247772; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v07773; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v257774; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v07775; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v23, v25, vcc_lo7776; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v277777; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v87778; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)7779; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v27, vcc_lo7780; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v77781; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247782; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v26, v25, vcc_lo7783; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)7784; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v277785; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v237786; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v87787; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v77788; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v157789; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7790; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v267791; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v25, v24, vcc_lo7792; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v287793; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v247794; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v277795; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)7796; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v257797; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v67798; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237799; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo7800; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v157801; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v26, v277802; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v147803; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)7804; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v29, v287805; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v15, v7, vcc_lo7806; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v237807; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v6, vcc_lo7808; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v247809; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v26, v24, vcc_lo7810; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v77811; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)7812; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v147813; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v257814; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v23, v25, vcc_lo7815; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v157816; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v267817; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v67818; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)7819; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v28, v247820; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v277821; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v257822; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v137823; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v26, v23, vcc_lo7824; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v67825; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc_lo7826; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v247827; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v57828; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v147829; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7830; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v16, v7, 0x50401007831; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo7832; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247833; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v47834; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v157835; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)7836; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v147837; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc_lo7838; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v257839; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v37840; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v57841; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v17, v6, 0x50401007842; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v127843; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v247844; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7845; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v137846; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo7847; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v147848; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)7849; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v4, vcc_lo7850; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v157851; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo7852; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v247853; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v127854; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v117855; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)7856; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v147857; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc_lo7858; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v47859; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v57860; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v15, v5, vcc_lo7861; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v247862; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v37863; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v117864; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v12, v4, vcc_lo7865; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v137866; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo7867; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v47868; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)7869; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v14, v4 :: v_dual_lshlrev_b32 v13, 16, v157870; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v247871; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v11, v3, vcc_lo7872; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v137873; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v147874; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v15, v5, vcc_lo7875; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v127876; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)7877; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v18, v5, 0x50401007878; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo7879; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v37880; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo7881; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v117882; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v27883; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v107884; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)7885; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v127886; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v247887; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v157888; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo7889; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v117890; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v07891; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)7892; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v20, v3, 0x50401007893; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc_lo7894; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v17895; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v127896; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo7897; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v157898; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)7899; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v17900; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v97901; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v117902; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v87903; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v107904; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7905; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v127906; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v27907; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v97908; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)7909; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v117910; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v10, v2, vcc_lo7911; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v24, v127912; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v9, v1, vcc_lo7913; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27914; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)7915; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v87916; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v07917; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v157918; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v8, v0, vcc_lo7919; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v17920; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc_lo7921; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v107922; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc_lo7923; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v07924; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc_lo7925; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v97926; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo7927; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v127928; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v87929; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo7930; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)7931; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v97932; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v157933; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v117934; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v107935; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)7936; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v22, v1, 0x50401007937; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc_lo7938; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v87939; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)7940; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v23, v0, 0x50401007941; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc_lo7942; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v137943; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v21, v2, 0x50401007944; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v14, v4, vcc_lo7945; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)7946; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v19, v4, 0x50401007947; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]7948;7949; GFX12-TRUE16-LABEL: v_minimumnum_v16bf16:7950; GFX12-TRUE16:       ; %bb.0:7951; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x07952; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x07953; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x07954; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x07955; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x07956; GFX12-TRUE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v77957; GFX12-TRUE16-NEXT:    v_and_b32_e32 v17, 0xffff0000, v157958; GFX12-TRUE16-NEXT:    v_and_b32_e32 v18, 0xffff0000, v67959; GFX12-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v147960; GFX12-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v137961; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v167962; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.l, 07963; GFX12-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v127964; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v20, v207965; GFX12-TRUE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v57966; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)7967; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v7.h, v15.h, vcc_lo7968; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v17, v177969; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v17.l, v16.l7970; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v21, v217971; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v25.l, v16.l7972; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v16.h7973; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)7974; GFX12-TRUE16-NEXT:    v_cndmask_b16 v17.h, v15.h, v16.h, vcc_lo7975; GFX12-TRUE16-NEXT:    v_and_b32_e32 v21, 0xffff0000, v47976; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v22, v227977; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v26.l, v16.l7978; GFX12-TRUE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v37979; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v16, v177980; GFX12-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v117981; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v27.l, v16.l7982; GFX12-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v107983; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v28.l, v16.l7984; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)7985; GFX12-TRUE16-NEXT:    v_cndmask_b16 v17.l, v17.h, v16.h, vcc_lo7986; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v23, v237987; GFX12-TRUE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v27988; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v24, v247989; GFX12-TRUE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v17990; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)7991; GFX12-TRUE16-NEXT:    v_cndmask_b16 v19.l, v17.l, v16.h, s07992; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v17.l7993; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v18, v187994; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v18.l, v16.l7995; GFX12-TRUE16-NEXT:    v_and_b32_e32 v29, 0xffff0000, v97996; GFX12-TRUE16-NEXT:    v_and_b32_e32 v30, 0xffff0000, v07997; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v167998; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)7999; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v6.h, v14.h, s08000; GFX12-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v88001; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v29, v298002; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v29.l, v16.l8003; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v158004; GFX12-TRUE16-NEXT:    v_cndmask_b16 v18.h, v14.h, v16.h, s18005; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v16.h8006; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v31, v318007; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v78008; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v32, v328009; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v16, v188010; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v148011; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8012; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8013; GFX12-TRUE16-NEXT:    v_cndmask_b16 v18.l, v18.h, v16.h, s08014; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v32, v328015; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v138016; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)8017; GFX12-TRUE16-NEXT:    v_cndmask_b16 v19.h, v18.l, v16.h, s18018; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v18.l8019; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v20, v208020; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v32, v328021; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v128022; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)8023; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v168024; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8025; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v5.h, v13.h, s18026; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v32, v328027; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v118028; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)8029; GFX12-TRUE16-NEXT:    v_cndmask_b16 v25.h, v13.h, v16.h, s28030; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v16.h8031; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v32, v328032; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v108033; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)8034; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v16, v258035; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v25.h8036; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v32, v328037; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8038; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)8039; GFX12-TRUE16-NEXT:    v_cndmask_b16 v20.l, v25.h, v16.h, s18040; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v98041; GFX12-TRUE16-NEXT:    v_cndmask_b16 v20.h, v20.l, v16.h, s28042; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v20.l8043; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v21, v218044; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)8045; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v32, v328046; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v32.l, v16.l8047; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v168048; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8049; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v4.h, v12.h, s28050; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8051; GFX12-TRUE16-NEXT:    v_cndmask_b16 v26.h, v12.h, v16.h, s38052; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v16.h8053; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v16, v268054; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8055; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8056; GFX12-TRUE16-NEXT:    v_cndmask_b16 v21.l, v26.h, v16.h, s28057; GFX12-TRUE16-NEXT:    v_cndmask_b16 v21.h, v21.l, v16.h, s38058; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v21.l8059; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v22, v228060; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8061; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v168062; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8063; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v3.h, v11.h, s38064; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8065; GFX12-TRUE16-NEXT:    v_cndmask_b16 v27.h, v11.h, v16.h, s48066; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v16.h8067; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s3, v16, v278068; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8069; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8070; GFX12-TRUE16-NEXT:    v_cndmask_b16 v22.l, v27.h, v16.h, s38071; GFX12-TRUE16-NEXT:    v_cndmask_b16 v22.h, v22.l, v16.h, s48072; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v22.l8073; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v23, v238074; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8075; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v168076; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8077; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v2.h, v10.h, s48078; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8079; GFX12-TRUE16-NEXT:    v_cndmask_b16 v28.h, v10.h, v16.h, s58080; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v16.h8081; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v16, v288082; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8083; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8084; GFX12-TRUE16-NEXT:    v_cndmask_b16 v23.l, v28.h, v16.h, s48085; GFX12-TRUE16-NEXT:    v_cndmask_b16 v23.h, v23.l, v16.h, s58086; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v23.l8087; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v24, v248088; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8089; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v168090; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8091; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v1.h, v9.h, s58092; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8093; GFX12-TRUE16-NEXT:    v_cndmask_b16 v29.h, v9.h, v16.h, s68094; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v16.h8095; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s5, v16, v298096; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8097; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8098; GFX12-TRUE16-NEXT:    v_cndmask_b16 v24.l, v29.h, v16.h, s58099; GFX12-TRUE16-NEXT:    v_cndmask_b16 v24.h, v24.l, v16.h, s68100; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v24.l8101; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v30, v308102; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v30.l, v16.l8103; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)8104; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s5, 0, v168105; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8106; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v0.h, v8.h, s68107; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8108; GFX12-TRUE16-NEXT:    v_cndmask_b16 v30.h, v8.h, v16.h, s78109; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v16.h8110; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s6, v16, v308111; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8112; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)8113; GFX12-TRUE16-NEXT:    v_cndmask_b16 v15.h, v30.h, v16.h, s68114; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v31, v318115; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v68116; GFX12-TRUE16-NEXT:    v_cndmask_b16 v25.l, v15.h, v16.h, s78117; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v15.h8118; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8119; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v7.l, v15.l, s68120; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v16.l8121; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8122; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s6, 0, v168123; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v15.l, v7.h, s88124; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v7.h8125; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)8126; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s7, v7, v168127; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8128; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.l, v16.h, v7.h, s78129; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v16.h8130; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)8131; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v7.l, v7.h, s88132; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v31, v318133; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v58134; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8135; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.h, v6.h, v16.h, s78136; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v7.l8137; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v6.l, v14.l, s88138; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v16.l8139; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8140; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s7, 0, v168141; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v14.l, v6.h, s98142; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v6.h8143; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8144; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8145; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.l, v7.l, v14.h, s78146; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s8, v6, v168147; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8148; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8149; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.l, v16.h, v6.h, s88150; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v16.h8151; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v6.l, v6.h, s98152; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v31, v318153; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v48154; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8155; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)8156; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.h, v5.h, v16.h, s88157; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v6.l8158; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v5.l, v13.l, s98159; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v16.l8160; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s8, 0, v168161; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8162; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v13.l, v5.h, s108163; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v5.h8164; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8165; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.l, v6.l, v13.h, s88166; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)8167; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s9, v5, v168168; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8169; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v16.h, v5.h, s98170; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v16.h8171; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)8172; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v5.l, v5.h, s108173; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v31, v318174; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v38175; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8176; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v4.h, v16.h, s98177; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v5.l8178; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v12.l, s108179; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v16.l8180; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8181; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s9, 0, v168182; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v12.l, v4.h, s118183; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s11, 0x8000, v4.h8184; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8185; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8186; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v5.l, v12.h, s98187; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s10, v4, v168188; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8189; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8190; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v16.h, v4.h, s108191; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v16.h8192; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v4.l, v4.h, s118193; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v31, v318194; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v28195; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8196; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)8197; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.h, v3.h, v16.h, s108198; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v4.l8199; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v3.l, v11.l, s118200; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v16.l8201; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s10, 0, v168202; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8203; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v11.l, v3.h, s128204; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s12, 0x8000, v3.h8205; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8206; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.l, v11.h, s108207; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)8208; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s11, v3, v168209; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8210; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v16.h, v3.h, s118211; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s11, 0x8000, v16.h8212; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)8213; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v3.l, v3.h, s128214; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v31, v318215; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v18216; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8217; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.h, v2.h, v16.h, s118218; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v3.l8219; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v2.l, v10.l, s128220; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v16.l8221; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8222; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s11, 0, v168223; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v10.l, v2.h, s138224; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v2.h8225; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8226; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)8227; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, v10.h, s118228; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s12, v2, v168229; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8230; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8231; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v16.h, v2.h, s128232; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s12, 0x8000, v16.h8233; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v2.l, v2.h, s138234; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v31, v318235; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v08236; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8237; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)8238; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v1.h, v16.h, s128239; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v2.l8240; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v1.l, v9.l, s138241; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v16.l8242; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s12, 0, v168243; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8244; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v9.l, v1.h, s148245; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v31, v318246; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s15, 0x8000, v1.h8247; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v31, 16, v88248; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8249; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.l, v9.h, s128250; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s13, v1, v168251; GFX12-TRUE16-NEXT:    v_cndmask_b16 v32.h, v0.l, v8.l, s148252; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v16.h8253; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v31, v318254; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8255; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v16.h, v1.h, s138256; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v17.h8257; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8258; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v1.l, v1.h, s158259; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8260; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v19.l, v17.h, s138261; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v18.h8262; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v20.h, v25.h, s178263; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s15, 0x8000, v32.h8264; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v16.h, s168265; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v1.l8266; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)8267; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v17.l, v0.h, vcc_lo8268; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8269; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v19.h, v18.h, s138270; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v26.h8271; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v20.l, v1.h, s18272; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s13, 0, v168273; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v8.l, v32.h, s148274; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v18.l, v0.h, s08275; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)8276; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v21.h, v26.h, vcc_lo8277; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v28.h8278; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v27.h8279; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v32, v168280; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8281; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v0.l, s138282; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v21.l, v0.h, s28283; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v29.h8284; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v23.h, v28.h, s18285; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.l, v16.h, v32.h, s08286; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v16.h8287; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)8288; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v22.h, v27.h, vcc_lo8289; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)8290; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v24.h, v29.h, s28291; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v30.h8292; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.l, v8.l, v32.h, s158293; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v23.l, v1.h, s48294; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v22.l, v0.h, s38295; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v24.l, v8.h, s58296; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)8297; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v25.l, v30.h, vcc_lo8298; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v9.l, v16.h, s08299; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v16.h, v8.l8300; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)8301; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v15.h, v0.h, s68302; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v168303; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)8304; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v8.l, v8.h, vcc_lo8305; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]8306;8307; GFX12-FAKE16-LABEL: v_minimumnum_v16bf16:8308; GFX12-FAKE16:       ; %bb.0:8309; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x08310; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x08311; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x08312; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x08313; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x08314; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 16, v148315; GFX12-FAKE16-NEXT:    v_and_b32_e32 v16, 0xffff0000, v78316; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v17, 16, v158317; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v18, 16, v78318; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v68319; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 16, v128320; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v16, v168321; GFX12-FAKE16-NEXT:    v_and_b32_e32 v19, 0xffff0000, v158322; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v48323; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v28, 16, v18324; GFX12-FAKE16-NEXT:    v_and_b32_e32 v20, 0xffff0000, v68325; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8326; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v17, vcc_lo8327; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v198328; GFX12-FAKE16-NEXT:    v_and_b32_e32 v23, 0xffff0000, v138329; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)8330; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v168331; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8332; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v16, vcc_lo8333; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v178334; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8335; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v18, v198336; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8337; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v17, v16, vcc_lo8338; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v208339; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8340; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v20, v22, v21 :: v_dual_and_b32 v19, 0xffff0000, v148341; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v168342; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8343; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc_lo8344; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)8345; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v198346; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8347; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v21, v20, vcc_lo8348; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v178349; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v208350; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v198351; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8352; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v17 :: v_dual_lshlrev_b32 v17, 16, v188353; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)8354; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v178355; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8356; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v16, v18, v16, vcc_lo8357; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v21, v228358; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v21, 16, v138359; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v22, 16, v58360; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8361; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v19, v20 :: v_dual_and_b32 v18, 0xffff0000, v58362; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v208363; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8364; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)8365; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v17, v20, vcc_lo8366; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v18, v188367; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8368; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v22, v21, vcc_lo8369; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v238370; GFX12-FAKE16-NEXT:    v_and_b32_e32 v22, 0xffff0000, v48371; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8372; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v188373; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8374; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v21, v18, vcc_lo8375; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v228376; GFX12-FAKE16-NEXT:    v_and_b32_e32 v26, 0xffff0000, v128377; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8378; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8379; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v25, v24 :: v_dual_lshlrev_b32 v25, 16, v218380; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v198381; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8382; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v20, v19, vcc_lo8383; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v268384; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8385; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v24, v22, vcc_lo8386; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v258387; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v178388; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v228389; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8390; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v21, v18 :: v_dual_lshlrev_b32 v26, 16, v208391; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v188392; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8393; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8394; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v23, v18, vcc_lo8395; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v248396; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8397; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v17, v17, v19, vcc_lo8398; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v268399; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v118400; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v38401; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8402; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v20, v22, vcc_lo8403; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v218404; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8405; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)8406; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v18, v18, v21 :: v_dual_lshlrev_b32 v27, 16, v198407; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v238408; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v228409; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8410; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v19, v22, vcc_lo8411; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v218412; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8413; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v23, v18, vcc_lo8414; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v208415; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8416; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v20, v22, v20 :: v_dual_and_b32 v23, 0xffff0000, v28417; GFX12-FAKE16-NEXT:    v_and_b32_e32 v24, 0xffff0000, v38418; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)8419; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v248420; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v24, 16, v108421; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8422; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v21, v26, v25 :: v_dual_and_b32 v22, 0xffff0000, v118423; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v28424; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v228425; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8426; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8427; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v25, v21, vcc_lo8428; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v238429; GFX12-FAKE16-NEXT:    v_and_b32_e32 v25, 0xffff0000, v108430; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8431; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v26, v24, vcc_lo8432; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v278433; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v27, 16, v98434; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8435; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v19, v20, vcc_lo8436; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v258437; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8438; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v24, v24, v23 :: v_dual_and_b32 v25, 0xffff0000, v18439; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)8440; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v248441; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v218442; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v228443; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v20, v268444; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8445; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v22, v21, vcc_lo8446; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v258447; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8448; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v28, v27, vcc_lo8449; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v26, 16, v238450; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v218451; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8452; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v20, v21, vcc_lo8453; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)8454; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v26, v298455; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8456; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v24, v23 :: v_dual_lshlrev_b32 v29, 16, v208457; GFX12-FAKE16-NEXT:    v_and_b32_e32 v28, 0xffff0000, v98458; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v288459; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8460; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v27, v25, vcc_lo8461; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v228462; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8463; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8464; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v21, v21, v22 :: v_dual_lshlrev_b32 v28, 16, v278465; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v238466; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8467; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v26, v23 :: v_dual_lshlrev_b32 v23, 16, v258468; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v248469; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8470; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)8471; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v24, vcc_lo8472; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v288473; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8474; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v27, v25 :: v_dual_lshlrev_b32 v24, 16, v268475; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v298476; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8477; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v20, v21, vcc_lo8478; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8479; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v248480; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8481; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v21, v26, v22 :: v_dual_and_b32 v24, 0xffff0000, v08482; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v258483; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v26, 16, v08484; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8485; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v23, v25, vcc_lo8486; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v278487; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v25, 16, v88488; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8489; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)8490; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v27, vcc_lo8491; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v78492; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v248493; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8494; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v26, v25, vcc_lo8495; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v27, v278496; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v238497; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8498; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v15 :: v_dual_and_b32 v26, 0xffff0000, v88499; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)8500; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v78501; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v158502; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v268503; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8504; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v25, v24, vcc_lo8505; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8506; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v288507; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8508; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v15, v7 :: v_dual_lshlrev_b32 v26, 16, v248509; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v278510; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8511; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v22, v23, v22 :: v_dual_lshlrev_b32 v27, 16, v258512; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v68513; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8514; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v238515; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8516; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo8517; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v158518; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v26, v278519; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8520; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v25, v24 :: v_dual_lshlrev_b32 v23, 16, v148521; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)8522; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v29, v288523; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8524; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v15, v7, vcc_lo8525; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v238526; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8527; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v14, v6, vcc_lo8528; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v248529; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8530; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v26, v24, vcc_lo8531; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v78532; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8533; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v148534; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v258535; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8536; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v23, v25, vcc_lo8537; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v158538; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v268539; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8540; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v15 :: v_dual_lshlrev_b32 v28, 16, v68541; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8542; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v28, v248543; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8544; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v14, v6 :: v_dual_lshlrev_b32 v24, 16, v278545; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v258546; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v138547; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8548; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v26, v23, vcc_lo8549; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v68550; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8551; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc_lo8552; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v248553; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8554; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v27, v7 :: v_dual_lshlrev_b32 v24, 16, v58555; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v148556; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8557; GFX12-FAKE16-NEXT:    v_perm_b32 v7, v16, v7, 0x50401008558; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8559; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo8560; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v248561; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8562; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v13 :: v_dual_lshlrev_b32 v24, 16, v48563; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v158564; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8565; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v148566; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8567; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc_lo8568; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v258569; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v38570; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v58571; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)8572; GFX12-FAKE16-NEXT:    v_perm_b32 v6, v17, v6, 0x50401008573; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8574; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v13, v13, v5 :: v_dual_lshlrev_b32 v14, 16, v128575; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v248576; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v138577; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8578; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo8579; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v148580; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8581; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8582; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v4, vcc_lo8583; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v158584; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8585; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo8586; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v248587; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8588; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v15, v13, v5 :: v_dual_lshlrev_b32 v24, 16, v128589; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v118590; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8591; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v148592; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8593; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v3, vcc_lo8594; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v48595; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v58596; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8597; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v15, v5, vcc_lo8598; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8599; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v248600; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v38601; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v118602; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8603; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v12, v4, vcc_lo8604; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v138605; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8606; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo8607; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48608; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8609; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v14, v4 :: v_dual_lshlrev_b32 v13, 16, v158610; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v248611; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8612; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v11, v3, vcc_lo8613; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)8614; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v138615; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v13, 16, v148616; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8617; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v15, v5, vcc_lo8618; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v128619; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v18, v5, 0x50401008620; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8621; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo8622; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v38623; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8624; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo8625; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v118626; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8627; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)8628; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v11 :: v_dual_lshlrev_b32 v12, 16, v28629; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v108630; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v128631; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8632; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v2, v10 :: v_dual_lshlrev_b32 v15, 16, v248633; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)8634; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v158635; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8636; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo8637; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v118638; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v08639; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v20, v3, 0x50401008640; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8641; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v2, vcc_lo8642; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v18643; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)8644; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v128645; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8646; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo8647; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v158648; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v18649; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8650; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v8 :: v_dual_lshlrev_b32 v11, 16, v98651; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)8652; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v118653; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8654; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v1 :: v_dual_lshlrev_b32 v12, 16, v88655; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v108656; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v128657; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8658; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v8, v8, v0 :: v_dual_lshlrev_b32 v15, 16, v28659; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v98660; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)8661; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v15, v118662; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8663; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v10, v2, vcc_lo8664; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v24, v128665; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8666; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v9, v1, vcc_lo8667; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v28668; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8669; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v11, v2 :: v_dual_lshlrev_b32 v15, 16, v88670; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v08671; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8672; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v158673; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8674; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v8, v0, vcc_lo8675; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v18676; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8677; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc_lo8678; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v108679; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8680; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc_lo8681; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v08682; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8683; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc_lo8684; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v98685; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8686; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo8687; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v128688; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v88689; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8690; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo8691; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)8692; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v98693; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v158694; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8695; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v12, v1 :: v_dual_lshlrev_b32 v8, 16, v118696; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v108697; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)8698; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v22, v1, 0x50401008699; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8700; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc_lo8701; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v88702; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v23, v0, 0x50401008703; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8704; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc_lo8705; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v138706; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)8707; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v21, v2, 0x50401008708; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)8709; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v14, v4, vcc_lo8710; GFX12-FAKE16-NEXT:    v_perm_b32 v4, v19, v4, 0x50401008711; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]8712  %result = call <16 x bfloat> @llvm.minimumnum.v16bf16(<16 x bfloat> %x, <16 x bfloat> %y)8713  ret <16 x bfloat> %result8714}8715 8716define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) {8717; GFX7-LABEL: v_minimumnum_v32bf16:8718; GFX7:       ; %bb.0:8719; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8720; GFX7-NEXT:    buffer_load_dword v31, off, s[0:3], s328721; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1288722; GFX7-NEXT:    v_mul_f32_e32 v30, 1.0, v308723; GFX7-NEXT:    v_and_b32_e32 v30, 0xffff0000, v308724; GFX7-NEXT:    v_mul_f32_e32 v29, 1.0, v298725; GFX7-NEXT:    v_and_b32_e32 v29, 0xffff0000, v298726; GFX7-NEXT:    v_mul_f32_e32 v28, 1.0, v288727; GFX7-NEXT:    v_and_b32_e32 v28, 0xffff0000, v288728; GFX7-NEXT:    v_mul_f32_e32 v27, 1.0, v278729; GFX7-NEXT:    v_and_b32_e32 v27, 0xffff0000, v278730; GFX7-NEXT:    v_mul_f32_e32 v26, 1.0, v268731; GFX7-NEXT:    v_and_b32_e32 v26, 0xffff0000, v268732; GFX7-NEXT:    v_mul_f32_e32 v25, 1.0, v258733; GFX7-NEXT:    v_and_b32_e32 v25, 0xffff0000, v258734; GFX7-NEXT:    v_mul_f32_e32 v24, 1.0, v248735; GFX7-NEXT:    v_and_b32_e32 v24, 0xffff0000, v248736; GFX7-NEXT:    v_mul_f32_e32 v23, 1.0, v238737; GFX7-NEXT:    v_and_b32_e32 v23, 0xffff0000, v238738; GFX7-NEXT:    v_mul_f32_e32 v22, 1.0, v228739; GFX7-NEXT:    v_and_b32_e32 v22, 0xffff0000, v228740; GFX7-NEXT:    v_mul_f32_e32 v21, 1.0, v218741; GFX7-NEXT:    v_and_b32_e32 v21, 0xffff0000, v218742; GFX7-NEXT:    v_mul_f32_e32 v20, 1.0, v208743; GFX7-NEXT:    v_and_b32_e32 v20, 0xffff0000, v208744; GFX7-NEXT:    v_mul_f32_e32 v19, 1.0, v198745; GFX7-NEXT:    v_and_b32_e32 v19, 0xffff0000, v198746; GFX7-NEXT:    v_mul_f32_e32 v18, 1.0, v188747; GFX7-NEXT:    v_and_b32_e32 v18, 0xffff0000, v188748; GFX7-NEXT:    v_mul_f32_e32 v17, 1.0, v178749; GFX7-NEXT:    v_and_b32_e32 v17, 0xffff0000, v178750; GFX7-NEXT:    v_mul_f32_e32 v16, 1.0, v168751; GFX7-NEXT:    v_and_b32_e32 v16, 0xffff0000, v168752; GFX7-NEXT:    v_mul_f32_e32 v15, 1.0, v158753; GFX7-NEXT:    v_and_b32_e32 v15, 0xffff0000, v158754; GFX7-NEXT:    v_mul_f32_e32 v14, 1.0, v148755; GFX7-NEXT:    v_and_b32_e32 v14, 0xffff0000, v148756; GFX7-NEXT:    v_mul_f32_e32 v13, 1.0, v138757; GFX7-NEXT:    v_and_b32_e32 v13, 0xffff0000, v138758; GFX7-NEXT:    v_mul_f32_e32 v12, 1.0, v128759; GFX7-NEXT:    v_and_b32_e32 v12, 0xffff0000, v128760; GFX7-NEXT:    v_mul_f32_e32 v11, 1.0, v118761; GFX7-NEXT:    v_and_b32_e32 v11, 0xffff0000, v118762; GFX7-NEXT:    v_mul_f32_e32 v10, 1.0, v108763; GFX7-NEXT:    v_and_b32_e32 v10, 0xffff0000, v108764; GFX7-NEXT:    v_mul_f32_e32 v9, 1.0, v98765; GFX7-NEXT:    v_and_b32_e32 v9, 0xffff0000, v98766; GFX7-NEXT:    v_mul_f32_e32 v8, 1.0, v88767; GFX7-NEXT:    v_and_b32_e32 v8, 0xffff0000, v88768; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v78769; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v78770; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v68771; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v68772; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v58773; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v58774; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v48775; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v48776; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v38777; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v38778; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v28779; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v28780; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v18781; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v18782; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v08783; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08784; GFX7-NEXT:    s_waitcnt vmcnt(1)8785; GFX7-NEXT:    v_mul_f32_e32 v31, 1.0, v318786; GFX7-NEXT:    s_waitcnt vmcnt(0)8787; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328788; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328789; GFX7-NEXT:    v_and_b32_e32 v31, 0xffff0000, v318790; GFX7-NEXT:    v_min_f32_e32 v31, v31, v328791; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1248792; GFX7-NEXT:    v_and_b32_e32 v31, 0xffff0000, v318793; GFX7-NEXT:    s_waitcnt vmcnt(0)8794; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328795; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328796; GFX7-NEXT:    v_min_f32_e32 v30, v30, v328797; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1208798; GFX7-NEXT:    v_and_b32_e32 v30, 0xffff0000, v308799; GFX7-NEXT:    s_waitcnt vmcnt(0)8800; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328801; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328802; GFX7-NEXT:    v_min_f32_e32 v29, v29, v328803; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1168804; GFX7-NEXT:    v_and_b32_e32 v29, 0xffff0000, v298805; GFX7-NEXT:    s_waitcnt vmcnt(0)8806; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328807; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328808; GFX7-NEXT:    v_min_f32_e32 v28, v28, v328809; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1128810; GFX7-NEXT:    v_and_b32_e32 v28, 0xffff0000, v288811; GFX7-NEXT:    s_waitcnt vmcnt(0)8812; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328813; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328814; GFX7-NEXT:    v_min_f32_e32 v27, v27, v328815; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1088816; GFX7-NEXT:    v_and_b32_e32 v27, 0xffff0000, v278817; GFX7-NEXT:    s_waitcnt vmcnt(0)8818; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328819; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328820; GFX7-NEXT:    v_min_f32_e32 v26, v26, v328821; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1048822; GFX7-NEXT:    v_and_b32_e32 v26, 0xffff0000, v268823; GFX7-NEXT:    s_waitcnt vmcnt(0)8824; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328825; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328826; GFX7-NEXT:    v_min_f32_e32 v25, v25, v328827; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:1008828; GFX7-NEXT:    v_and_b32_e32 v25, 0xffff0000, v258829; GFX7-NEXT:    s_waitcnt vmcnt(0)8830; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328831; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328832; GFX7-NEXT:    v_min_f32_e32 v24, v24, v328833; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:968834; GFX7-NEXT:    v_and_b32_e32 v24, 0xffff0000, v248835; GFX7-NEXT:    s_waitcnt vmcnt(0)8836; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328837; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328838; GFX7-NEXT:    v_min_f32_e32 v23, v23, v328839; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:928840; GFX7-NEXT:    v_and_b32_e32 v23, 0xffff0000, v238841; GFX7-NEXT:    s_waitcnt vmcnt(0)8842; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328843; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328844; GFX7-NEXT:    v_min_f32_e32 v22, v22, v328845; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:888846; GFX7-NEXT:    v_and_b32_e32 v22, 0xffff0000, v228847; GFX7-NEXT:    s_waitcnt vmcnt(0)8848; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328849; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328850; GFX7-NEXT:    v_min_f32_e32 v21, v21, v328851; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:848852; GFX7-NEXT:    v_and_b32_e32 v21, 0xffff0000, v218853; GFX7-NEXT:    s_waitcnt vmcnt(0)8854; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328855; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328856; GFX7-NEXT:    v_min_f32_e32 v20, v20, v328857; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:808858; GFX7-NEXT:    v_and_b32_e32 v20, 0xffff0000, v208859; GFX7-NEXT:    s_waitcnt vmcnt(0)8860; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328861; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328862; GFX7-NEXT:    v_min_f32_e32 v19, v19, v328863; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:768864; GFX7-NEXT:    v_and_b32_e32 v19, 0xffff0000, v198865; GFX7-NEXT:    s_waitcnt vmcnt(0)8866; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328867; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328868; GFX7-NEXT:    v_min_f32_e32 v18, v18, v328869; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:728870; GFX7-NEXT:    v_and_b32_e32 v18, 0xffff0000, v188871; GFX7-NEXT:    s_waitcnt vmcnt(0)8872; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328873; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328874; GFX7-NEXT:    v_min_f32_e32 v17, v17, v328875; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:688876; GFX7-NEXT:    v_and_b32_e32 v17, 0xffff0000, v178877; GFX7-NEXT:    s_waitcnt vmcnt(0)8878; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328879; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328880; GFX7-NEXT:    v_min_f32_e32 v16, v16, v328881; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:648882; GFX7-NEXT:    v_and_b32_e32 v16, 0xffff0000, v168883; GFX7-NEXT:    s_waitcnt vmcnt(0)8884; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328885; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328886; GFX7-NEXT:    v_min_f32_e32 v15, v15, v328887; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:608888; GFX7-NEXT:    v_and_b32_e32 v15, 0xffff0000, v158889; GFX7-NEXT:    s_waitcnt vmcnt(0)8890; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328891; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328892; GFX7-NEXT:    v_min_f32_e32 v14, v14, v328893; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:568894; GFX7-NEXT:    v_and_b32_e32 v14, 0xffff0000, v148895; GFX7-NEXT:    s_waitcnt vmcnt(0)8896; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328897; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328898; GFX7-NEXT:    v_min_f32_e32 v13, v13, v328899; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:528900; GFX7-NEXT:    v_and_b32_e32 v13, 0xffff0000, v138901; GFX7-NEXT:    s_waitcnt vmcnt(0)8902; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328903; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328904; GFX7-NEXT:    v_min_f32_e32 v12, v12, v328905; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:488906; GFX7-NEXT:    v_and_b32_e32 v12, 0xffff0000, v128907; GFX7-NEXT:    s_waitcnt vmcnt(0)8908; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328909; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328910; GFX7-NEXT:    v_min_f32_e32 v11, v11, v328911; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:448912; GFX7-NEXT:    v_and_b32_e32 v11, 0xffff0000, v118913; GFX7-NEXT:    s_waitcnt vmcnt(0)8914; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328915; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328916; GFX7-NEXT:    v_min_f32_e32 v10, v10, v328917; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:408918; GFX7-NEXT:    v_and_b32_e32 v10, 0xffff0000, v108919; GFX7-NEXT:    s_waitcnt vmcnt(0)8920; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328921; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328922; GFX7-NEXT:    v_min_f32_e32 v9, v9, v328923; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:368924; GFX7-NEXT:    v_and_b32_e32 v9, 0xffff0000, v98925; GFX7-NEXT:    s_waitcnt vmcnt(0)8926; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328927; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328928; GFX7-NEXT:    v_min_f32_e32 v8, v8, v328929; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:328930; GFX7-NEXT:    v_and_b32_e32 v8, 0xffff0000, v88931; GFX7-NEXT:    s_waitcnt vmcnt(0)8932; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328933; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328934; GFX7-NEXT:    v_min_f32_e32 v7, v7, v328935; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:288936; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v78937; GFX7-NEXT:    s_waitcnt vmcnt(0)8938; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328939; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328940; GFX7-NEXT:    v_min_f32_e32 v6, v6, v328941; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:248942; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v68943; GFX7-NEXT:    s_waitcnt vmcnt(0)8944; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328945; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328946; GFX7-NEXT:    v_min_f32_e32 v5, v5, v328947; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:208948; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v58949; GFX7-NEXT:    s_waitcnt vmcnt(0)8950; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328951; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328952; GFX7-NEXT:    v_min_f32_e32 v4, v4, v328953; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:168954; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v48955; GFX7-NEXT:    s_waitcnt vmcnt(0)8956; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328957; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328958; GFX7-NEXT:    v_min_f32_e32 v3, v3, v328959; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:128960; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v38961; GFX7-NEXT:    s_waitcnt vmcnt(0)8962; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328963; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328964; GFX7-NEXT:    v_min_f32_e32 v2, v2, v328965; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:88966; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v28967; GFX7-NEXT:    s_waitcnt vmcnt(0)8968; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328969; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328970; GFX7-NEXT:    v_min_f32_e32 v1, v1, v328971; GFX7-NEXT:    buffer_load_dword v32, off, s[0:3], s32 offset:48972; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v18973; GFX7-NEXT:    s_waitcnt vmcnt(0)8974; GFX7-NEXT:    v_mul_f32_e32 v32, 1.0, v328975; GFX7-NEXT:    v_and_b32_e32 v32, 0xffff0000, v328976; GFX7-NEXT:    v_min_f32_e32 v0, v0, v328977; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08978; GFX7-NEXT:    s_setpc_b64 s[30:31]8979;8980; GFX8-LABEL: v_minimumnum_v32bf16:8981; GFX8:       ; %bb.0:8982; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8983; GFX8-NEXT:    buffer_load_dword v55, off, s[0:3], s328984; GFX8-NEXT:    v_and_b32_e32 v31, 0xffff0000, v148985; GFX8-NEXT:    v_lshrrev_b32_e32 v34, 16, v308986; GFX8-NEXT:    v_lshrrev_b32_e32 v35, 16, v148987; GFX8-NEXT:    v_and_b32_e32 v37, 0xffff0000, v138988; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v31, v318989; GFX8-NEXT:    v_and_b32_e32 v36, 0xffff0000, v308990; GFX8-NEXT:    v_lshrrev_b32_e32 v38, 16, v298991; GFX8-NEXT:    v_lshrrev_b32_e32 v39, 16, v138992; GFX8-NEXT:    v_cndmask_b32_e32 v31, v35, v34, vcc8993; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v37, v378994; GFX8-NEXT:    v_and_b32_e32 v48, 0xffff0000, v298995; GFX8-NEXT:    v_cndmask_b32_e32 v35, v39, v38, vcc8996; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v36, v368997; GFX8-NEXT:    v_cndmask_b32_e32 v34, v34, v31, vcc8998; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v48, v488999; GFX8-NEXT:    v_lshlrev_b32_e32 v37, 16, v319000; GFX8-NEXT:    v_cndmask_b32_e32 v38, v38, v35, vcc9001; GFX8-NEXT:    v_lshlrev_b32_e32 v39, 16, v349002; GFX8-NEXT:    v_lshlrev_b32_e32 v36, 16, v359003; GFX8-NEXT:    v_lshlrev_b32_e32 v48, 16, v389004; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v37, v399005; GFX8-NEXT:    s_movk_i32 s4, 0x80009006; GFX8-NEXT:    v_cndmask_b32_e32 v37, v34, v31, vcc9007; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v36, v489008; GFX8-NEXT:    v_cndmask_b32_e32 v36, v38, v35, vcc9009; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v319010; GFX8-NEXT:    v_cndmask_b32_e32 v31, v37, v31, vcc9011; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359012; GFX8-NEXT:    v_cndmask_b32_e32 v35, v36, v35, vcc9013; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v349014; GFX8-NEXT:    v_lshlrev_b32_e32 v39, 16, v379015; GFX8-NEXT:    v_cndmask_b32_e32 v31, v31, v34, vcc9016; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v389017; GFX8-NEXT:    v_and_b32_e32 v32, 0xffff0000, v159018; GFX8-NEXT:    v_cndmask_b32_e32 v34, v35, v38, vcc9019; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v399020; GFX8-NEXT:    v_lshrrev_b32_e32 v33, 16, v159021; GFX8-NEXT:    v_cndmask_b32_e32 v31, v37, v31, vcc9022; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v32, v329023; GFX8-NEXT:    v_lshlrev_b32_e32 v48, 16, v369024; GFX8-NEXT:    v_and_b32_e32 v38, 0xffff0000, v279025; GFX8-NEXT:    v_and_b32_e32 v39, 0xffff0000, v269026; GFX8-NEXT:    v_and_b32_e32 v49, 0xffff0000, v249027; GFX8-NEXT:    v_and_b32_e32 v50, 0xffff0000, v239028; GFX8-NEXT:    v_and_b32_e32 v51, 0xffff0000, v229029; GFX8-NEXT:    v_and_b32_e32 v52, 0xffff0000, v219030; GFX8-NEXT:    v_and_b32_e32 v53, 0xffff0000, v209031; GFX8-NEXT:    v_and_b32_e32 v54, 0xffff0000, v199032; GFX8-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill9033; GFX8-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill9034; GFX8-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill9035; GFX8-NEXT:    v_and_b32_e32 v40, 0xffff0000, v189036; GFX8-NEXT:    v_and_b32_e32 v41, 0xffff0000, v179037; GFX8-NEXT:    v_and_b32_e32 v42, 0xffff0000, v169038; GFX8-NEXT:    s_waitcnt vmcnt(3)9039; GFX8-NEXT:    v_lshrrev_b32_e32 v35, 16, v559040; GFX8-NEXT:    v_and_b32_e32 v37, 0xffff0000, v559041; GFX8-NEXT:    v_cndmask_b32_e32 v32, v33, v35, vcc9042; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379043; GFX8-NEXT:    v_cndmask_b32_e32 v35, v35, v32, vcc9044; GFX8-NEXT:    v_lshlrev_b32_e32 v33, 16, v329045; GFX8-NEXT:    v_lshlrev_b32_e32 v37, 16, v359046; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v33, v379047; GFX8-NEXT:    v_cndmask_b32_e32 v33, v35, v32, vcc9048; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v329049; GFX8-NEXT:    v_cndmask_b32_e32 v32, v33, v32, vcc9050; GFX8-NEXT:    v_lshlrev_b32_e32 v37, 16, v339051; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359052; GFX8-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc9053; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v379054; GFX8-NEXT:    v_cndmask_b32_e32 v32, v33, v32, vcc9055; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v489056; GFX8-NEXT:    v_cndmask_b32_e32 v33, v36, v34, vcc9057; GFX8-NEXT:    v_and_b32_e32 v34, 0xffff0000, v129058; GFX8-NEXT:    v_lshrrev_b32_e32 v35, 16, v289059; GFX8-NEXT:    v_lshrrev_b32_e32 v36, 16, v129060; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v34, v349061; GFX8-NEXT:    v_and_b32_e32 v37, 0xffff0000, v289062; GFX8-NEXT:    v_cndmask_b32_e32 v34, v36, v35, vcc9063; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379064; GFX8-NEXT:    v_cndmask_b32_e32 v35, v35, v34, vcc9065; GFX8-NEXT:    v_lshlrev_b32_e32 v36, 16, v349066; GFX8-NEXT:    v_lshlrev_b32_e32 v37, 16, v359067; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v36, v379068; GFX8-NEXT:    v_cndmask_b32_e32 v36, v35, v34, vcc9069; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v349070; GFX8-NEXT:    v_cndmask_b32_e32 v34, v36, v34, vcc9071; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359072; GFX8-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc9073; GFX8-NEXT:    v_lshlrev_b32_e32 v35, 16, v369074; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v359075; GFX8-NEXT:    v_and_b32_e32 v35, 0xffff0000, v119076; GFX8-NEXT:    v_cndmask_b32_e32 v34, v36, v34, vcc9077; GFX8-NEXT:    v_lshrrev_b32_e32 v36, 16, v279078; GFX8-NEXT:    v_lshrrev_b32_e32 v37, 16, v119079; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v35, v359080; GFX8-NEXT:    v_cndmask_b32_e32 v35, v37, v36, vcc9081; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v38, v389082; GFX8-NEXT:    v_cndmask_b32_e32 v36, v36, v35, vcc9083; GFX8-NEXT:    v_lshlrev_b32_e32 v37, 16, v359084; GFX8-NEXT:    v_lshlrev_b32_e32 v38, 16, v369085; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v37, v389086; GFX8-NEXT:    v_cndmask_b32_e32 v37, v36, v35, vcc9087; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359088; GFX8-NEXT:    v_cndmask_b32_e32 v35, v37, v35, vcc9089; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v369090; GFX8-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc9091; GFX8-NEXT:    v_lshlrev_b32_e32 v36, 16, v379092; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v369093; GFX8-NEXT:    v_and_b32_e32 v36, 0xffff0000, v109094; GFX8-NEXT:    v_cndmask_b32_e32 v35, v37, v35, vcc9095; GFX8-NEXT:    v_lshrrev_b32_e32 v37, 16, v269096; GFX8-NEXT:    v_lshrrev_b32_e32 v38, 16, v109097; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v36, v369098; GFX8-NEXT:    v_cndmask_b32_e32 v36, v38, v37, vcc9099; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v39, v399100; GFX8-NEXT:    v_cndmask_b32_e32 v37, v37, v36, vcc9101; GFX8-NEXT:    v_lshlrev_b32_e32 v38, 16, v369102; GFX8-NEXT:    v_lshlrev_b32_e32 v39, 16, v379103; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v38, v399104; GFX8-NEXT:    v_cndmask_b32_e32 v38, v37, v36, vcc9105; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v369106; GFX8-NEXT:    v_cndmask_b32_e32 v36, v38, v36, vcc9107; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v379108; GFX8-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc9109; GFX8-NEXT:    v_lshlrev_b32_e32 v37, 16, v389110; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v379111; GFX8-NEXT:    v_and_b32_e32 v37, 0xffff0000, v99112; GFX8-NEXT:    v_cndmask_b32_e32 v36, v38, v36, vcc9113; GFX8-NEXT:    v_lshrrev_b32_e32 v38, 16, v259114; GFX8-NEXT:    v_lshrrev_b32_e32 v39, 16, v99115; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379116; GFX8-NEXT:    v_and_b32_e32 v48, 0xffff0000, v259117; GFX8-NEXT:    v_cndmask_b32_e32 v37, v39, v38, vcc9118; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v48, v489119; GFX8-NEXT:    v_cndmask_b32_e32 v38, v38, v37, vcc9120; GFX8-NEXT:    v_lshlrev_b32_e32 v39, 16, v379121; GFX8-NEXT:    v_lshlrev_b32_e32 v48, 16, v389122; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v39, v489123; GFX8-NEXT:    v_cndmask_b32_e32 v39, v38, v37, vcc9124; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v379125; GFX8-NEXT:    v_cndmask_b32_e32 v37, v39, v37, vcc9126; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v389127; GFX8-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc9128; GFX8-NEXT:    v_lshlrev_b32_e32 v38, 16, v399129; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v389130; GFX8-NEXT:    v_and_b32_e32 v38, 0xffff0000, v89131; GFX8-NEXT:    v_cndmask_b32_e32 v37, v39, v37, vcc9132; GFX8-NEXT:    v_lshrrev_b32_e32 v39, 16, v249133; GFX8-NEXT:    v_lshrrev_b32_e32 v48, 16, v89134; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v38, v389135; GFX8-NEXT:    v_cndmask_b32_e32 v38, v48, v39, vcc9136; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v49, v499137; GFX8-NEXT:    v_cndmask_b32_e32 v39, v39, v38, vcc9138; GFX8-NEXT:    v_lshlrev_b32_e32 v48, 16, v389139; GFX8-NEXT:    v_lshlrev_b32_e32 v49, 16, v399140; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v48, v499141; GFX8-NEXT:    v_cndmask_b32_e32 v48, v39, v38, vcc9142; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v389143; GFX8-NEXT:    v_cndmask_b32_e32 v38, v48, v38, vcc9144; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v399145; GFX8-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc9146; GFX8-NEXT:    v_lshlrev_b32_e32 v39, 16, v489147; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v399148; GFX8-NEXT:    v_and_b32_e32 v39, 0xffff0000, v79149; GFX8-NEXT:    v_cndmask_b32_e32 v38, v48, v38, vcc9150; GFX8-NEXT:    v_lshrrev_b32_e32 v48, 16, v239151; GFX8-NEXT:    v_lshrrev_b32_e32 v49, 16, v79152; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v39, v399153; GFX8-NEXT:    v_cndmask_b32_e32 v39, v49, v48, vcc9154; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v50, v509155; GFX8-NEXT:    v_cndmask_b32_e32 v48, v48, v39, vcc9156; GFX8-NEXT:    v_lshlrev_b32_e32 v49, 16, v399157; GFX8-NEXT:    v_lshlrev_b32_e32 v50, 16, v489158; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v49, v509159; GFX8-NEXT:    v_cndmask_b32_e32 v49, v48, v39, vcc9160; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v399161; GFX8-NEXT:    v_cndmask_b32_e32 v39, v49, v39, vcc9162; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v489163; GFX8-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc9164; GFX8-NEXT:    v_lshlrev_b32_e32 v48, 16, v499165; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v489166; GFX8-NEXT:    v_and_b32_e32 v48, 0xffff0000, v69167; GFX8-NEXT:    v_cndmask_b32_e32 v39, v49, v39, vcc9168; GFX8-NEXT:    v_lshrrev_b32_e32 v49, 16, v229169; GFX8-NEXT:    v_lshrrev_b32_e32 v50, 16, v69170; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v48, v489171; GFX8-NEXT:    v_cndmask_b32_e32 v48, v50, v49, vcc9172; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v51, v519173; GFX8-NEXT:    v_cndmask_b32_e32 v49, v49, v48, vcc9174; GFX8-NEXT:    v_lshlrev_b32_e32 v50, 16, v489175; GFX8-NEXT:    v_lshlrev_b32_e32 v51, 16, v499176; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v50, v519177; GFX8-NEXT:    v_cndmask_b32_e32 v50, v49, v48, vcc9178; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v489179; GFX8-NEXT:    v_cndmask_b32_e32 v48, v50, v48, vcc9180; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v499181; GFX8-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc9182; GFX8-NEXT:    v_lshlrev_b32_e32 v49, 16, v509183; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v499184; GFX8-NEXT:    v_and_b32_e32 v49, 0xffff0000, v59185; GFX8-NEXT:    v_cndmask_b32_e32 v48, v50, v48, vcc9186; GFX8-NEXT:    v_lshrrev_b32_e32 v50, 16, v219187; GFX8-NEXT:    v_lshrrev_b32_e32 v51, 16, v59188; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v49, v499189; GFX8-NEXT:    v_cndmask_b32_e32 v49, v51, v50, vcc9190; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v52, v529191; GFX8-NEXT:    v_cndmask_b32_e32 v50, v50, v49, vcc9192; GFX8-NEXT:    v_lshlrev_b32_e32 v51, 16, v499193; GFX8-NEXT:    v_lshlrev_b32_e32 v52, 16, v509194; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v51, v529195; GFX8-NEXT:    v_cndmask_b32_e32 v51, v50, v49, vcc9196; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v499197; GFX8-NEXT:    v_cndmask_b32_e32 v49, v51, v49, vcc9198; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v509199; GFX8-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc9200; GFX8-NEXT:    v_lshlrev_b32_e32 v50, 16, v519201; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v509202; GFX8-NEXT:    v_and_b32_e32 v50, 0xffff0000, v49203; GFX8-NEXT:    v_cndmask_b32_e32 v49, v51, v49, vcc9204; GFX8-NEXT:    v_lshrrev_b32_e32 v51, 16, v209205; GFX8-NEXT:    v_lshrrev_b32_e32 v52, 16, v49206; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v50, v509207; GFX8-NEXT:    v_cndmask_b32_e32 v50, v52, v51, vcc9208; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v53, v539209; GFX8-NEXT:    v_cndmask_b32_e32 v51, v51, v50, vcc9210; GFX8-NEXT:    v_lshlrev_b32_e32 v52, 16, v509211; GFX8-NEXT:    v_lshlrev_b32_e32 v53, 16, v519212; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v52, v539213; GFX8-NEXT:    v_cndmask_b32_e32 v52, v51, v50, vcc9214; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v509215; GFX8-NEXT:    v_cndmask_b32_e32 v50, v52, v50, vcc9216; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v519217; GFX8-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc9218; GFX8-NEXT:    v_lshlrev_b32_e32 v51, 16, v529219; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v519220; GFX8-NEXT:    v_and_b32_e32 v51, 0xffff0000, v39221; GFX8-NEXT:    v_cndmask_b32_e32 v50, v52, v50, vcc9222; GFX8-NEXT:    v_lshrrev_b32_e32 v52, 16, v199223; GFX8-NEXT:    v_lshrrev_b32_e32 v53, 16, v39224; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v51, v519225; GFX8-NEXT:    v_cndmask_b32_e32 v51, v53, v52, vcc9226; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v54, v549227; GFX8-NEXT:    v_cndmask_b32_e32 v52, v52, v51, vcc9228; GFX8-NEXT:    v_lshlrev_b32_e32 v53, 16, v519229; GFX8-NEXT:    v_lshlrev_b32_e32 v54, 16, v529230; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v53, v549231; GFX8-NEXT:    v_cndmask_b32_e32 v53, v52, v51, vcc9232; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v519233; GFX8-NEXT:    v_cndmask_b32_e32 v51, v53, v51, vcc9234; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v529235; GFX8-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc9236; GFX8-NEXT:    v_lshlrev_b32_e32 v52, 16, v539237; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v529238; GFX8-NEXT:    v_and_b32_e32 v52, 0xffff0000, v29239; GFX8-NEXT:    v_cndmask_b32_e32 v51, v53, v51, vcc9240; GFX8-NEXT:    v_lshrrev_b32_e32 v53, 16, v189241; GFX8-NEXT:    v_lshrrev_b32_e32 v54, 16, v29242; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v52, v529243; GFX8-NEXT:    v_cndmask_b32_e32 v52, v54, v53, vcc9244; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v40, v409245; GFX8-NEXT:    v_cndmask_b32_e32 v53, v53, v52, vcc9246; GFX8-NEXT:    v_lshlrev_b32_e32 v54, 16, v529247; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v539248; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v54, v409249; GFX8-NEXT:    v_cndmask_b32_e32 v54, v53, v52, vcc9250; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v529251; GFX8-NEXT:    v_cndmask_b32_e32 v52, v54, v52, vcc9252; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v539253; GFX8-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc9254; GFX8-NEXT:    v_lshlrev_b32_e32 v53, 16, v549255; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v539256; GFX8-NEXT:    v_and_b32_e32 v53, 0xffff0000, v19257; GFX8-NEXT:    v_cndmask_b32_e32 v52, v54, v52, vcc9258; GFX8-NEXT:    v_lshrrev_b32_e32 v54, 16, v179259; GFX8-NEXT:    v_lshrrev_b32_e32 v40, 16, v19260; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v53, v539261; GFX8-NEXT:    v_cndmask_b32_e32 v53, v40, v54, vcc9262; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v41, v419263; GFX8-NEXT:    v_cndmask_b32_e32 v54, v54, v53, vcc9264; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v539265; GFX8-NEXT:    v_lshlrev_b32_e32 v41, 16, v549266; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v40, v419267; GFX8-NEXT:    v_cndmask_b32_e32 v40, v54, v53, vcc9268; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v539269; GFX8-NEXT:    v_cndmask_b32_e32 v53, v40, v53, vcc9270; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v549271; GFX8-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc9272; GFX8-NEXT:    v_lshlrev_b32_e32 v54, 16, v409273; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v549274; GFX8-NEXT:    v_and_b32_e32 v54, 0xffff0000, v09275; GFX8-NEXT:    v_cndmask_b32_e32 v53, v40, v53, vcc9276; GFX8-NEXT:    v_lshrrev_b32_e32 v40, 16, v169277; GFX8-NEXT:    v_lshrrev_b32_e32 v41, 16, v09278; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v54, v549279; GFX8-NEXT:    v_cndmask_b32_e32 v54, v41, v40, vcc9280; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v42, v429281; GFX8-NEXT:    v_cndmask_b32_e32 v40, v40, v54, vcc9282; GFX8-NEXT:    v_lshlrev_b32_e32 v41, 16, v549283; GFX8-NEXT:    v_lshlrev_b32_e32 v42, 16, v409284; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v41, v429285; GFX8-NEXT:    v_cndmask_b32_e32 v41, v40, v54, vcc9286; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v549287; GFX8-NEXT:    v_cndmask_b32_e32 v54, v41, v54, vcc9288; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v409289; GFX8-NEXT:    v_cndmask_b32_e32 v54, v54, v40, vcc9290; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v419291; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v409292; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v159293; GFX8-NEXT:    v_cndmask_b32_e32 v54, v41, v54, vcc9294; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v40, v409295; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v559296; GFX8-NEXT:    v_cndmask_b32_e32 v15, v15, v55, vcc9297; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v40, v409298; GFX8-NEXT:    v_cndmask_b32_e32 v55, v55, v15, vcc9299; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v559300; GFX8-NEXT:    v_lshlrev_b32_e32 v41, 16, v159301; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v41, v409302; GFX8-NEXT:    v_cndmask_b32_e32 v40, v55, v15, vcc9303; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v159304; GFX8-NEXT:    v_cndmask_b32_e32 v15, v40, v15, vcc9305; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v559306; GFX8-NEXT:    v_cndmask_b32_e32 v15, v15, v55, vcc9307; GFX8-NEXT:    v_lshlrev_b32_e32 v55, 16, v409308; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v559309; GFX8-NEXT:    v_lshlrev_b32_e32 v55, 16, v149310; GFX8-NEXT:    v_cndmask_b32_e32 v15, v40, v15, vcc9311; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v55, v559312; GFX8-NEXT:    v_lshlrev_b32_e32 v55, 16, v309313; GFX8-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc9314; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v55, v559315; GFX8-NEXT:    v_cndmask_b32_e32 v30, v30, v14, vcc9316; GFX8-NEXT:    v_lshlrev_b32_e32 v55, 16, v309317; GFX8-NEXT:    v_lshlrev_b32_e32 v40, 16, v149318; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v40, v559319; GFX8-NEXT:    v_cndmask_b32_e32 v55, v30, v14, vcc9320; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v149321; GFX8-NEXT:    v_cndmask_b32_e32 v14, v55, v14, vcc9322; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v309323; GFX8-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc9324; GFX8-NEXT:    v_lshlrev_b32_e32 v30, 16, v559325; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v309326; GFX8-NEXT:    v_lshlrev_b32_e32 v30, 16, v139327; GFX8-NEXT:    v_cndmask_b32_e32 v14, v55, v14, vcc9328; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v30, v309329; GFX8-NEXT:    v_lshlrev_b32_e32 v30, 16, v299330; GFX8-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc9331; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v30, v309332; GFX8-NEXT:    v_cndmask_b32_e32 v29, v29, v13, vcc9333; GFX8-NEXT:    v_lshlrev_b32_e32 v30, 16, v299334; GFX8-NEXT:    v_lshlrev_b32_e32 v55, 16, v139335; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v55, v309336; GFX8-NEXT:    v_cndmask_b32_e32 v30, v29, v13, vcc9337; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v139338; GFX8-NEXT:    v_cndmask_b32_e32 v13, v30, v13, vcc9339; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v299340; GFX8-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc9341; GFX8-NEXT:    v_lshlrev_b32_e32 v29, 16, v309342; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v299343; GFX8-NEXT:    v_lshlrev_b32_e32 v29, 16, v129344; GFX8-NEXT:    v_cndmask_b32_e32 v13, v30, v13, vcc9345; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v29, v299346; GFX8-NEXT:    v_lshlrev_b32_e32 v29, 16, v289347; GFX8-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc9348; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v29, v299349; GFX8-NEXT:    v_cndmask_b32_e32 v28, v28, v12, vcc9350; GFX8-NEXT:    v_lshlrev_b32_e32 v29, 16, v289351; GFX8-NEXT:    v_lshlrev_b32_e32 v30, 16, v129352; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v30, v299353; GFX8-NEXT:    v_cndmask_b32_e32 v29, v28, v12, vcc9354; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v129355; GFX8-NEXT:    v_cndmask_b32_e32 v12, v29, v12, vcc9356; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v289357; GFX8-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc9358; GFX8-NEXT:    v_lshlrev_b32_e32 v28, 16, v299359; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v289360; GFX8-NEXT:    v_lshlrev_b32_e32 v28, 16, v119361; GFX8-NEXT:    v_cndmask_b32_e32 v12, v29, v12, vcc9362; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v28, v289363; GFX8-NEXT:    v_lshlrev_b32_e32 v28, 16, v279364; GFX8-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc9365; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v28, v289366; GFX8-NEXT:    v_cndmask_b32_e32 v27, v27, v11, vcc9367; GFX8-NEXT:    v_lshlrev_b32_e32 v28, 16, v279368; GFX8-NEXT:    v_lshlrev_b32_e32 v29, 16, v119369; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v29, v289370; GFX8-NEXT:    v_cndmask_b32_e32 v28, v27, v11, vcc9371; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v119372; GFX8-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc9373; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v279374; GFX8-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc9375; GFX8-NEXT:    v_lshlrev_b32_e32 v27, 16, v289376; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v279377; GFX8-NEXT:    v_lshlrev_b32_e32 v27, 16, v109378; GFX8-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc9379; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v27, v279380; GFX8-NEXT:    v_lshlrev_b32_e32 v27, 16, v269381; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc9382; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v27, v279383; GFX8-NEXT:    v_cndmask_b32_e32 v26, v26, v10, vcc9384; GFX8-NEXT:    v_lshlrev_b32_e32 v27, 16, v269385; GFX8-NEXT:    v_lshlrev_b32_e32 v28, 16, v109386; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v28, v279387; GFX8-NEXT:    v_cndmask_b32_e32 v27, v26, v10, vcc9388; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v109389; GFX8-NEXT:    v_cndmask_b32_e32 v10, v27, v10, vcc9390; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v269391; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc9392; GFX8-NEXT:    v_lshlrev_b32_e32 v26, 16, v279393; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v269394; GFX8-NEXT:    v_lshlrev_b32_e32 v26, 16, v99395; GFX8-NEXT:    v_cndmask_b32_e32 v10, v27, v10, vcc9396; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v26, v269397; GFX8-NEXT:    v_lshlrev_b32_e32 v26, 16, v259398; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc9399; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v26, v269400; GFX8-NEXT:    v_cndmask_b32_e32 v25, v25, v9, vcc9401; GFX8-NEXT:    v_lshlrev_b32_e32 v26, 16, v259402; GFX8-NEXT:    v_lshlrev_b32_e32 v27, 16, v99403; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v27, v269404; GFX8-NEXT:    v_cndmask_b32_e32 v26, v25, v9, vcc9405; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v99406; GFX8-NEXT:    v_cndmask_b32_e32 v9, v26, v9, vcc9407; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v259408; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc9409; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v269410; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v259411; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v89412; GFX8-NEXT:    v_cndmask_b32_e32 v9, v26, v9, vcc9413; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v25, v259414; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v249415; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc9416; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v25, v259417; GFX8-NEXT:    v_cndmask_b32_e32 v24, v24, v8, vcc9418; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v249419; GFX8-NEXT:    v_lshlrev_b32_e32 v26, 16, v89420; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v26, v259421; GFX8-NEXT:    v_cndmask_b32_e32 v25, v24, v8, vcc9422; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v89423; GFX8-NEXT:    v_cndmask_b32_e32 v8, v25, v8, vcc9424; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v249425; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc9426; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v259427; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v249428; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v79429; GFX8-NEXT:    v_cndmask_b32_e32 v8, v25, v8, vcc9430; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v24, v249431; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v239432; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc9433; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v24, v249434; GFX8-NEXT:    v_cndmask_b32_e32 v23, v23, v7, vcc9435; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v239436; GFX8-NEXT:    v_lshlrev_b32_e32 v25, 16, v79437; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v249438; GFX8-NEXT:    v_cndmask_b32_e32 v24, v23, v7, vcc9439; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v79440; GFX8-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc9441; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v239442; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc9443; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v249444; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v239445; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v69446; GFX8-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload9447; GFX8-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload9448; GFX8-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload9449; GFX8-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc9450; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v23, v239451; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v229452; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc9453; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v23, v239454; GFX8-NEXT:    v_cndmask_b32_e32 v22, v22, v6, vcc9455; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v229456; GFX8-NEXT:    v_lshlrev_b32_e32 v24, 16, v69457; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v239458; GFX8-NEXT:    v_cndmask_b32_e32 v23, v22, v6, vcc9459; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v69460; GFX8-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc9461; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v229462; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc9463; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v239464; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v229465; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v59466; GFX8-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc9467; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v22, v229468; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v219469; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc9470; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v22, v229471; GFX8-NEXT:    v_cndmask_b32_e32 v21, v21, v5, vcc9472; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v219473; GFX8-NEXT:    v_lshlrev_b32_e32 v23, 16, v59474; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v23, v229475; GFX8-NEXT:    v_cndmask_b32_e32 v22, v21, v5, vcc9476; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v59477; GFX8-NEXT:    v_cndmask_b32_e32 v5, v22, v5, vcc9478; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v219479; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc9480; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v229481; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v219482; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v49483; GFX8-NEXT:    v_cndmask_b32_e32 v5, v22, v5, vcc9484; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v21, v219485; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v209486; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc9487; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v21, v219488; GFX8-NEXT:    v_cndmask_b32_e32 v20, v20, v4, vcc9489; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v209490; GFX8-NEXT:    v_lshlrev_b32_e32 v22, 16, v49491; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v22, v219492; GFX8-NEXT:    v_cndmask_b32_e32 v21, v20, v4, vcc9493; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v49494; GFX8-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc9495; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v209496; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc9497; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v219498; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v209499; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v39500; GFX8-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc9501; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v20, v209502; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v199503; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc9504; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v20, v209505; GFX8-NEXT:    v_cndmask_b32_e32 v19, v19, v3, vcc9506; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v199507; GFX8-NEXT:    v_lshlrev_b32_e32 v21, 16, v39508; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v21, v209509; GFX8-NEXT:    v_cndmask_b32_e32 v20, v19, v3, vcc9510; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v39511; GFX8-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc9512; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v199513; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc9514; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v209515; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v199516; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v29517; GFX8-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc9518; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v19, v199519; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v189520; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc9521; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v19, v199522; GFX8-NEXT:    v_cndmask_b32_e32 v18, v18, v2, vcc9523; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v189524; GFX8-NEXT:    v_lshlrev_b32_e32 v20, 16, v29525; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v20, v199526; GFX8-NEXT:    v_cndmask_b32_e32 v19, v18, v2, vcc9527; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v29528; GFX8-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc9529; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v189530; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc9531; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v199532; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v189533; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v19534; GFX8-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc9535; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v18, v189536; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v179537; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc9538; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v18, v189539; GFX8-NEXT:    v_cndmask_b32_e32 v17, v17, v1, vcc9540; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v179541; GFX8-NEXT:    v_lshlrev_b32_e32 v19, 16, v19542; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v19, v189543; GFX8-NEXT:    v_cndmask_b32_e32 v18, v17, v1, vcc9544; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v19545; GFX8-NEXT:    v_cndmask_b32_e32 v1, v18, v1, vcc9546; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v179547; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc9548; GFX8-NEXT:    v_lshlrev_b32_e32 v17, 16, v189549; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v179550; GFX8-NEXT:    v_lshlrev_b32_e32 v17, 16, v09551; GFX8-NEXT:    v_cndmask_b32_e32 v1, v18, v1, vcc9552; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v17, v179553; GFX8-NEXT:    v_lshlrev_b32_e32 v17, 16, v169554; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc9555; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v17, v179556; GFX8-NEXT:    v_cndmask_b32_e32 v16, v16, v0, vcc9557; GFX8-NEXT:    v_lshlrev_b32_e32 v17, 16, v169558; GFX8-NEXT:    v_lshlrev_b32_e32 v18, 16, v09559; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v18, v179560; GFX8-NEXT:    v_cndmask_b32_e32 v17, v16, v0, vcc9561; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v09562; GFX8-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc9563; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v169564; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc9565; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v179566; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v169567; GFX8-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc9568; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v549569; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9570; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v539571; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9572; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v529573; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9574; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v519575; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9576; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v509577; GFX8-NEXT:    v_or_b32_sdwa v4, v4, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9578; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v499579; GFX8-NEXT:    v_or_b32_sdwa v5, v5, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9580; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v489581; GFX8-NEXT:    v_or_b32_sdwa v6, v6, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9582; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v399583; GFX8-NEXT:    v_or_b32_sdwa v7, v7, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9584; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v389585; GFX8-NEXT:    v_or_b32_sdwa v8, v8, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9586; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v379587; GFX8-NEXT:    v_or_b32_sdwa v9, v9, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9588; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v369589; GFX8-NEXT:    v_or_b32_sdwa v10, v10, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9590; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v359591; GFX8-NEXT:    v_or_b32_sdwa v11, v11, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9592; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v349593; GFX8-NEXT:    v_or_b32_sdwa v12, v12, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9594; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v339595; GFX8-NEXT:    v_or_b32_sdwa v13, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9596; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v319597; GFX8-NEXT:    v_or_b32_sdwa v14, v14, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9598; GFX8-NEXT:    v_lshlrev_b32_e32 v16, 16, v329599; GFX8-NEXT:    v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9600; GFX8-NEXT:    s_waitcnt vmcnt(0)9601; GFX8-NEXT:    s_setpc_b64 s[30:31]9602;9603; GFX900-LABEL: v_minimumnum_v32bf16:9604; GFX900:       ; %bb.0:9605; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9606; GFX900-NEXT:    buffer_load_dword v55, off, s[0:3], s329607; GFX900-NEXT:    v_and_b32_e32 v31, 0xffff0000, v149608; GFX900-NEXT:    v_lshrrev_b32_e32 v34, 16, v309609; GFX900-NEXT:    v_lshrrev_b32_e32 v35, 16, v149610; GFX900-NEXT:    v_and_b32_e32 v37, 0xffff0000, v139611; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v31, v319612; GFX900-NEXT:    v_and_b32_e32 v36, 0xffff0000, v309613; GFX900-NEXT:    v_lshrrev_b32_e32 v38, 16, v299614; GFX900-NEXT:    v_lshrrev_b32_e32 v39, 16, v139615; GFX900-NEXT:    v_cndmask_b32_e32 v31, v35, v34, vcc9616; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379617; GFX900-NEXT:    v_and_b32_e32 v48, 0xffff0000, v299618; GFX900-NEXT:    v_cndmask_b32_e32 v35, v39, v38, vcc9619; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v36, v369620; GFX900-NEXT:    v_cndmask_b32_e32 v34, v34, v31, vcc9621; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v48, v489622; GFX900-NEXT:    v_lshlrev_b32_e32 v37, 16, v319623; GFX900-NEXT:    v_cndmask_b32_e32 v38, v38, v35, vcc9624; GFX900-NEXT:    v_lshlrev_b32_e32 v39, 16, v349625; GFX900-NEXT:    v_lshlrev_b32_e32 v36, 16, v359626; GFX900-NEXT:    v_lshlrev_b32_e32 v48, 16, v389627; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v37, v399628; GFX900-NEXT:    s_movk_i32 s4, 0x80009629; GFX900-NEXT:    v_cndmask_b32_e32 v37, v34, v31, vcc9630; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v36, v489631; GFX900-NEXT:    v_cndmask_b32_e32 v36, v38, v35, vcc9632; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v319633; GFX900-NEXT:    v_cndmask_b32_e32 v31, v37, v31, vcc9634; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359635; GFX900-NEXT:    v_cndmask_b32_e32 v35, v36, v35, vcc9636; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v349637; GFX900-NEXT:    v_lshlrev_b32_e32 v39, 16, v379638; GFX900-NEXT:    v_cndmask_b32_e32 v31, v31, v34, vcc9639; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v389640; GFX900-NEXT:    v_and_b32_e32 v32, 0xffff0000, v159641; GFX900-NEXT:    v_cndmask_b32_e32 v34, v35, v38, vcc9642; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v399643; GFX900-NEXT:    v_lshrrev_b32_e32 v33, 16, v159644; GFX900-NEXT:    v_cndmask_b32_e32 v31, v37, v31, vcc9645; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v32, v329646; GFX900-NEXT:    v_lshlrev_b32_e32 v48, 16, v369647; GFX900-NEXT:    v_and_b32_e32 v38, 0xffff0000, v279648; GFX900-NEXT:    v_and_b32_e32 v39, 0xffff0000, v269649; GFX900-NEXT:    v_and_b32_e32 v49, 0xffff0000, v249650; GFX900-NEXT:    v_and_b32_e32 v50, 0xffff0000, v239651; GFX900-NEXT:    v_and_b32_e32 v51, 0xffff0000, v229652; GFX900-NEXT:    v_and_b32_e32 v52, 0xffff0000, v219653; GFX900-NEXT:    v_and_b32_e32 v53, 0xffff0000, v209654; GFX900-NEXT:    v_and_b32_e32 v54, 0xffff0000, v199655; GFX900-NEXT:    buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill9656; GFX900-NEXT:    buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill9657; GFX900-NEXT:    buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill9658; GFX900-NEXT:    v_and_b32_e32 v40, 0xffff0000, v189659; GFX900-NEXT:    v_and_b32_e32 v41, 0xffff0000, v179660; GFX900-NEXT:    v_and_b32_e32 v42, 0xffff0000, v169661; GFX900-NEXT:    s_waitcnt vmcnt(3)9662; GFX900-NEXT:    v_lshrrev_b32_e32 v35, 16, v559663; GFX900-NEXT:    v_and_b32_e32 v37, 0xffff0000, v559664; GFX900-NEXT:    v_cndmask_b32_e32 v32, v33, v35, vcc9665; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379666; GFX900-NEXT:    v_cndmask_b32_e32 v35, v35, v32, vcc9667; GFX900-NEXT:    v_lshlrev_b32_e32 v33, 16, v329668; GFX900-NEXT:    v_lshlrev_b32_e32 v37, 16, v359669; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v33, v379670; GFX900-NEXT:    v_cndmask_b32_e32 v33, v35, v32, vcc9671; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v329672; GFX900-NEXT:    v_cndmask_b32_e32 v32, v33, v32, vcc9673; GFX900-NEXT:    v_lshlrev_b32_e32 v37, 16, v339674; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359675; GFX900-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc9676; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v379677; GFX900-NEXT:    v_cndmask_b32_e32 v32, v33, v32, vcc9678; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v489679; GFX900-NEXT:    v_cndmask_b32_e32 v33, v36, v34, vcc9680; GFX900-NEXT:    v_and_b32_e32 v34, 0xffff0000, v129681; GFX900-NEXT:    v_lshrrev_b32_e32 v35, 16, v289682; GFX900-NEXT:    v_lshrrev_b32_e32 v36, 16, v129683; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v34, v349684; GFX900-NEXT:    v_and_b32_e32 v37, 0xffff0000, v289685; GFX900-NEXT:    v_cndmask_b32_e32 v34, v36, v35, vcc9686; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379687; GFX900-NEXT:    v_cndmask_b32_e32 v35, v35, v34, vcc9688; GFX900-NEXT:    v_lshlrev_b32_e32 v36, 16, v349689; GFX900-NEXT:    v_lshlrev_b32_e32 v37, 16, v359690; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v36, v379691; GFX900-NEXT:    v_cndmask_b32_e32 v36, v35, v34, vcc9692; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v349693; GFX900-NEXT:    v_cndmask_b32_e32 v34, v36, v34, vcc9694; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359695; GFX900-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc9696; GFX900-NEXT:    v_lshlrev_b32_e32 v35, 16, v369697; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v359698; GFX900-NEXT:    v_and_b32_e32 v35, 0xffff0000, v119699; GFX900-NEXT:    v_cndmask_b32_e32 v34, v36, v34, vcc9700; GFX900-NEXT:    v_lshrrev_b32_e32 v36, 16, v279701; GFX900-NEXT:    v_lshrrev_b32_e32 v37, 16, v119702; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v35, v359703; GFX900-NEXT:    v_cndmask_b32_e32 v35, v37, v36, vcc9704; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v38, v389705; GFX900-NEXT:    v_cndmask_b32_e32 v36, v36, v35, vcc9706; GFX900-NEXT:    v_lshlrev_b32_e32 v37, 16, v359707; GFX900-NEXT:    v_lshlrev_b32_e32 v38, 16, v369708; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v37, v389709; GFX900-NEXT:    v_cndmask_b32_e32 v37, v36, v35, vcc9710; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v359711; GFX900-NEXT:    v_cndmask_b32_e32 v35, v37, v35, vcc9712; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v369713; GFX900-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc9714; GFX900-NEXT:    v_lshlrev_b32_e32 v36, 16, v379715; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v369716; GFX900-NEXT:    v_and_b32_e32 v36, 0xffff0000, v109717; GFX900-NEXT:    v_cndmask_b32_e32 v35, v37, v35, vcc9718; GFX900-NEXT:    v_lshrrev_b32_e32 v37, 16, v269719; GFX900-NEXT:    v_lshrrev_b32_e32 v38, 16, v109720; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v36, v369721; GFX900-NEXT:    v_cndmask_b32_e32 v36, v38, v37, vcc9722; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v39, v399723; GFX900-NEXT:    v_cndmask_b32_e32 v37, v37, v36, vcc9724; GFX900-NEXT:    v_lshlrev_b32_e32 v38, 16, v369725; GFX900-NEXT:    v_lshlrev_b32_e32 v39, 16, v379726; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v38, v399727; GFX900-NEXT:    v_cndmask_b32_e32 v38, v37, v36, vcc9728; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v369729; GFX900-NEXT:    v_cndmask_b32_e32 v36, v38, v36, vcc9730; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v379731; GFX900-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc9732; GFX900-NEXT:    v_lshlrev_b32_e32 v37, 16, v389733; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v379734; GFX900-NEXT:    v_and_b32_e32 v37, 0xffff0000, v99735; GFX900-NEXT:    v_cndmask_b32_e32 v36, v38, v36, vcc9736; GFX900-NEXT:    v_lshrrev_b32_e32 v38, 16, v259737; GFX900-NEXT:    v_lshrrev_b32_e32 v39, 16, v99738; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v37, v379739; GFX900-NEXT:    v_and_b32_e32 v48, 0xffff0000, v259740; GFX900-NEXT:    v_cndmask_b32_e32 v37, v39, v38, vcc9741; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v48, v489742; GFX900-NEXT:    v_cndmask_b32_e32 v38, v38, v37, vcc9743; GFX900-NEXT:    v_lshlrev_b32_e32 v39, 16, v379744; GFX900-NEXT:    v_lshlrev_b32_e32 v48, 16, v389745; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v39, v489746; GFX900-NEXT:    v_cndmask_b32_e32 v39, v38, v37, vcc9747; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v379748; GFX900-NEXT:    v_cndmask_b32_e32 v37, v39, v37, vcc9749; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v389750; GFX900-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc9751; GFX900-NEXT:    v_lshlrev_b32_e32 v38, 16, v399752; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v389753; GFX900-NEXT:    v_and_b32_e32 v38, 0xffff0000, v89754; GFX900-NEXT:    v_cndmask_b32_e32 v37, v39, v37, vcc9755; GFX900-NEXT:    v_lshrrev_b32_e32 v39, 16, v249756; GFX900-NEXT:    v_lshrrev_b32_e32 v48, 16, v89757; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v38, v389758; GFX900-NEXT:    v_cndmask_b32_e32 v38, v48, v39, vcc9759; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v49, v499760; GFX900-NEXT:    v_cndmask_b32_e32 v39, v39, v38, vcc9761; GFX900-NEXT:    v_lshlrev_b32_e32 v48, 16, v389762; GFX900-NEXT:    v_lshlrev_b32_e32 v49, 16, v399763; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v48, v499764; GFX900-NEXT:    v_cndmask_b32_e32 v48, v39, v38, vcc9765; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v389766; GFX900-NEXT:    v_cndmask_b32_e32 v38, v48, v38, vcc9767; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v399768; GFX900-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc9769; GFX900-NEXT:    v_lshlrev_b32_e32 v39, 16, v489770; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v399771; GFX900-NEXT:    v_and_b32_e32 v39, 0xffff0000, v79772; GFX900-NEXT:    v_cndmask_b32_e32 v38, v48, v38, vcc9773; GFX900-NEXT:    v_lshrrev_b32_e32 v48, 16, v239774; GFX900-NEXT:    v_lshrrev_b32_e32 v49, 16, v79775; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v39, v399776; GFX900-NEXT:    v_cndmask_b32_e32 v39, v49, v48, vcc9777; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v50, v509778; GFX900-NEXT:    v_cndmask_b32_e32 v48, v48, v39, vcc9779; GFX900-NEXT:    v_lshlrev_b32_e32 v49, 16, v399780; GFX900-NEXT:    v_lshlrev_b32_e32 v50, 16, v489781; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v49, v509782; GFX900-NEXT:    v_cndmask_b32_e32 v49, v48, v39, vcc9783; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v399784; GFX900-NEXT:    v_cndmask_b32_e32 v39, v49, v39, vcc9785; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v489786; GFX900-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc9787; GFX900-NEXT:    v_lshlrev_b32_e32 v48, 16, v499788; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v489789; GFX900-NEXT:    v_and_b32_e32 v48, 0xffff0000, v69790; GFX900-NEXT:    v_cndmask_b32_e32 v39, v49, v39, vcc9791; GFX900-NEXT:    v_lshrrev_b32_e32 v49, 16, v229792; GFX900-NEXT:    v_lshrrev_b32_e32 v50, 16, v69793; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v48, v489794; GFX900-NEXT:    v_cndmask_b32_e32 v48, v50, v49, vcc9795; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v51, v519796; GFX900-NEXT:    v_cndmask_b32_e32 v49, v49, v48, vcc9797; GFX900-NEXT:    v_lshlrev_b32_e32 v50, 16, v489798; GFX900-NEXT:    v_lshlrev_b32_e32 v51, 16, v499799; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v50, v519800; GFX900-NEXT:    v_cndmask_b32_e32 v50, v49, v48, vcc9801; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v489802; GFX900-NEXT:    v_cndmask_b32_e32 v48, v50, v48, vcc9803; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v499804; GFX900-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc9805; GFX900-NEXT:    v_lshlrev_b32_e32 v49, 16, v509806; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v499807; GFX900-NEXT:    v_and_b32_e32 v49, 0xffff0000, v59808; GFX900-NEXT:    v_cndmask_b32_e32 v48, v50, v48, vcc9809; GFX900-NEXT:    v_lshrrev_b32_e32 v50, 16, v219810; GFX900-NEXT:    v_lshrrev_b32_e32 v51, 16, v59811; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v49, v499812; GFX900-NEXT:    v_cndmask_b32_e32 v49, v51, v50, vcc9813; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v52, v529814; GFX900-NEXT:    v_cndmask_b32_e32 v50, v50, v49, vcc9815; GFX900-NEXT:    v_lshlrev_b32_e32 v51, 16, v499816; GFX900-NEXT:    v_lshlrev_b32_e32 v52, 16, v509817; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v51, v529818; GFX900-NEXT:    v_cndmask_b32_e32 v51, v50, v49, vcc9819; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v499820; GFX900-NEXT:    v_cndmask_b32_e32 v49, v51, v49, vcc9821; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v509822; GFX900-NEXT:    v_cndmask_b32_e32 v49, v49, v50, vcc9823; GFX900-NEXT:    v_lshlrev_b32_e32 v50, 16, v519824; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v509825; GFX900-NEXT:    v_and_b32_e32 v50, 0xffff0000, v49826; GFX900-NEXT:    v_cndmask_b32_e32 v49, v51, v49, vcc9827; GFX900-NEXT:    v_lshrrev_b32_e32 v51, 16, v209828; GFX900-NEXT:    v_lshrrev_b32_e32 v52, 16, v49829; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v50, v509830; GFX900-NEXT:    v_cndmask_b32_e32 v50, v52, v51, vcc9831; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v53, v539832; GFX900-NEXT:    v_cndmask_b32_e32 v51, v51, v50, vcc9833; GFX900-NEXT:    v_lshlrev_b32_e32 v52, 16, v509834; GFX900-NEXT:    v_lshlrev_b32_e32 v53, 16, v519835; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v52, v539836; GFX900-NEXT:    v_cndmask_b32_e32 v52, v51, v50, vcc9837; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v509838; GFX900-NEXT:    v_cndmask_b32_e32 v50, v52, v50, vcc9839; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v519840; GFX900-NEXT:    v_cndmask_b32_e32 v50, v50, v51, vcc9841; GFX900-NEXT:    v_lshlrev_b32_e32 v51, 16, v529842; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v519843; GFX900-NEXT:    v_and_b32_e32 v51, 0xffff0000, v39844; GFX900-NEXT:    v_cndmask_b32_e32 v50, v52, v50, vcc9845; GFX900-NEXT:    v_lshrrev_b32_e32 v52, 16, v199846; GFX900-NEXT:    v_lshrrev_b32_e32 v53, 16, v39847; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v51, v519848; GFX900-NEXT:    v_cndmask_b32_e32 v51, v53, v52, vcc9849; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v54, v549850; GFX900-NEXT:    v_cndmask_b32_e32 v52, v52, v51, vcc9851; GFX900-NEXT:    v_lshlrev_b32_e32 v53, 16, v519852; GFX900-NEXT:    v_lshlrev_b32_e32 v54, 16, v529853; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v53, v549854; GFX900-NEXT:    v_cndmask_b32_e32 v53, v52, v51, vcc9855; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v519856; GFX900-NEXT:    v_cndmask_b32_e32 v51, v53, v51, vcc9857; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v529858; GFX900-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc9859; GFX900-NEXT:    v_lshlrev_b32_e32 v52, 16, v539860; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v529861; GFX900-NEXT:    v_and_b32_e32 v52, 0xffff0000, v29862; GFX900-NEXT:    v_cndmask_b32_e32 v51, v53, v51, vcc9863; GFX900-NEXT:    v_lshrrev_b32_e32 v53, 16, v189864; GFX900-NEXT:    v_lshrrev_b32_e32 v54, 16, v29865; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v52, v529866; GFX900-NEXT:    v_cndmask_b32_e32 v52, v54, v53, vcc9867; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v40, v409868; GFX900-NEXT:    v_cndmask_b32_e32 v53, v53, v52, vcc9869; GFX900-NEXT:    v_lshlrev_b32_e32 v54, 16, v529870; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v539871; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v54, v409872; GFX900-NEXT:    v_cndmask_b32_e32 v54, v53, v52, vcc9873; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v529874; GFX900-NEXT:    v_cndmask_b32_e32 v52, v54, v52, vcc9875; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v539876; GFX900-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc9877; GFX900-NEXT:    v_lshlrev_b32_e32 v53, 16, v549878; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v539879; GFX900-NEXT:    v_and_b32_e32 v53, 0xffff0000, v19880; GFX900-NEXT:    v_cndmask_b32_e32 v52, v54, v52, vcc9881; GFX900-NEXT:    v_lshrrev_b32_e32 v54, 16, v179882; GFX900-NEXT:    v_lshrrev_b32_e32 v40, 16, v19883; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v53, v539884; GFX900-NEXT:    v_cndmask_b32_e32 v53, v40, v54, vcc9885; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v41, v419886; GFX900-NEXT:    v_cndmask_b32_e32 v54, v54, v53, vcc9887; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v539888; GFX900-NEXT:    v_lshlrev_b32_e32 v41, 16, v549889; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v40, v419890; GFX900-NEXT:    v_cndmask_b32_e32 v40, v54, v53, vcc9891; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v539892; GFX900-NEXT:    v_cndmask_b32_e32 v53, v40, v53, vcc9893; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v549894; GFX900-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc9895; GFX900-NEXT:    v_lshlrev_b32_e32 v54, 16, v409896; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v549897; GFX900-NEXT:    v_and_b32_e32 v54, 0xffff0000, v09898; GFX900-NEXT:    v_cndmask_b32_e32 v53, v40, v53, vcc9899; GFX900-NEXT:    v_lshrrev_b32_e32 v40, 16, v169900; GFX900-NEXT:    v_lshrrev_b32_e32 v41, 16, v09901; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v54, v549902; GFX900-NEXT:    v_cndmask_b32_e32 v54, v41, v40, vcc9903; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v42, v429904; GFX900-NEXT:    v_cndmask_b32_e32 v40, v40, v54, vcc9905; GFX900-NEXT:    v_lshlrev_b32_e32 v41, 16, v549906; GFX900-NEXT:    v_lshlrev_b32_e32 v42, 16, v409907; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v41, v429908; GFX900-NEXT:    v_cndmask_b32_e32 v41, v40, v54, vcc9909; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v549910; GFX900-NEXT:    v_cndmask_b32_e32 v54, v41, v54, vcc9911; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v409912; GFX900-NEXT:    v_cndmask_b32_e32 v54, v54, v40, vcc9913; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v419914; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v409915; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v159916; GFX900-NEXT:    v_cndmask_b32_e32 v54, v41, v54, vcc9917; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v40, v409918; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v559919; GFX900-NEXT:    v_cndmask_b32_e32 v15, v15, v55, vcc9920; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v40, v409921; GFX900-NEXT:    v_cndmask_b32_e32 v55, v55, v15, vcc9922; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v559923; GFX900-NEXT:    v_lshlrev_b32_e32 v41, 16, v159924; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v41, v409925; GFX900-NEXT:    v_cndmask_b32_e32 v40, v55, v15, vcc9926; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v159927; GFX900-NEXT:    v_cndmask_b32_e32 v15, v40, v15, vcc9928; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v559929; GFX900-NEXT:    v_cndmask_b32_e32 v15, v15, v55, vcc9930; GFX900-NEXT:    v_lshlrev_b32_e32 v55, 16, v409931; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v559932; GFX900-NEXT:    v_lshlrev_b32_e32 v55, 16, v149933; GFX900-NEXT:    v_cndmask_b32_e32 v15, v40, v15, vcc9934; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v55, v559935; GFX900-NEXT:    v_lshlrev_b32_e32 v55, 16, v309936; GFX900-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc9937; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v55, v559938; GFX900-NEXT:    v_cndmask_b32_e32 v30, v30, v14, vcc9939; GFX900-NEXT:    v_lshlrev_b32_e32 v55, 16, v309940; GFX900-NEXT:    v_lshlrev_b32_e32 v40, 16, v149941; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v40, v559942; GFX900-NEXT:    v_cndmask_b32_e32 v55, v30, v14, vcc9943; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v149944; GFX900-NEXT:    v_cndmask_b32_e32 v14, v55, v14, vcc9945; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v309946; GFX900-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc9947; GFX900-NEXT:    v_lshlrev_b32_e32 v30, 16, v559948; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v309949; GFX900-NEXT:    v_lshlrev_b32_e32 v30, 16, v139950; GFX900-NEXT:    v_cndmask_b32_e32 v14, v55, v14, vcc9951; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v30, v309952; GFX900-NEXT:    v_lshlrev_b32_e32 v30, 16, v299953; GFX900-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc9954; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v30, v309955; GFX900-NEXT:    v_cndmask_b32_e32 v29, v29, v13, vcc9956; GFX900-NEXT:    v_lshlrev_b32_e32 v30, 16, v299957; GFX900-NEXT:    v_lshlrev_b32_e32 v55, 16, v139958; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v55, v309959; GFX900-NEXT:    v_cndmask_b32_e32 v30, v29, v13, vcc9960; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v139961; GFX900-NEXT:    v_cndmask_b32_e32 v13, v30, v13, vcc9962; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v299963; GFX900-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc9964; GFX900-NEXT:    v_lshlrev_b32_e32 v29, 16, v309965; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v299966; GFX900-NEXT:    v_lshlrev_b32_e32 v29, 16, v129967; GFX900-NEXT:    v_cndmask_b32_e32 v13, v30, v13, vcc9968; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v29, v299969; GFX900-NEXT:    v_lshlrev_b32_e32 v29, 16, v289970; GFX900-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc9971; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v29, v299972; GFX900-NEXT:    v_cndmask_b32_e32 v28, v28, v12, vcc9973; GFX900-NEXT:    v_lshlrev_b32_e32 v29, 16, v289974; GFX900-NEXT:    v_lshlrev_b32_e32 v30, 16, v129975; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v30, v299976; GFX900-NEXT:    v_cndmask_b32_e32 v29, v28, v12, vcc9977; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v129978; GFX900-NEXT:    v_cndmask_b32_e32 v12, v29, v12, vcc9979; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v289980; GFX900-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc9981; GFX900-NEXT:    v_lshlrev_b32_e32 v28, 16, v299982; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v289983; GFX900-NEXT:    v_lshlrev_b32_e32 v28, 16, v119984; GFX900-NEXT:    v_cndmask_b32_e32 v12, v29, v12, vcc9985; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v28, v289986; GFX900-NEXT:    v_lshlrev_b32_e32 v28, 16, v279987; GFX900-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc9988; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v28, v289989; GFX900-NEXT:    v_cndmask_b32_e32 v27, v27, v11, vcc9990; GFX900-NEXT:    v_lshlrev_b32_e32 v28, 16, v279991; GFX900-NEXT:    v_lshlrev_b32_e32 v29, 16, v119992; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v29, v289993; GFX900-NEXT:    v_cndmask_b32_e32 v28, v27, v11, vcc9994; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v119995; GFX900-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc9996; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v279997; GFX900-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc9998; GFX900-NEXT:    v_lshlrev_b32_e32 v27, 16, v289999; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2710000; GFX900-NEXT:    v_lshlrev_b32_e32 v27, 16, v1010001; GFX900-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc10002; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v27, v2710003; GFX900-NEXT:    v_lshlrev_b32_e32 v27, 16, v2610004; GFX900-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc10005; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v27, v2710006; GFX900-NEXT:    v_cndmask_b32_e32 v26, v26, v10, vcc10007; GFX900-NEXT:    v_lshlrev_b32_e32 v27, 16, v2610008; GFX900-NEXT:    v_lshlrev_b32_e32 v28, 16, v1010009; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v28, v2710010; GFX900-NEXT:    v_cndmask_b32_e32 v27, v26, v10, vcc10011; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1010012; GFX900-NEXT:    v_cndmask_b32_e32 v10, v27, v10, vcc10013; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2610014; GFX900-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc10015; GFX900-NEXT:    v_lshlrev_b32_e32 v26, 16, v2710016; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2610017; GFX900-NEXT:    v_lshlrev_b32_e32 v26, 16, v910018; GFX900-NEXT:    v_cndmask_b32_e32 v10, v27, v10, vcc10019; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v26, v2610020; GFX900-NEXT:    v_lshlrev_b32_e32 v26, 16, v2510021; GFX900-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc10022; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v26, v2610023; GFX900-NEXT:    v_cndmask_b32_e32 v25, v25, v9, vcc10024; GFX900-NEXT:    v_lshlrev_b32_e32 v26, 16, v2510025; GFX900-NEXT:    v_lshlrev_b32_e32 v27, 16, v910026; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v27, v2610027; GFX900-NEXT:    v_cndmask_b32_e32 v26, v25, v9, vcc10028; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v910029; GFX900-NEXT:    v_cndmask_b32_e32 v9, v26, v9, vcc10030; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2510031; GFX900-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc10032; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v2610033; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2510034; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v810035; GFX900-NEXT:    v_cndmask_b32_e32 v9, v26, v9, vcc10036; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v25, v2510037; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v2410038; GFX900-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc10039; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v25, v2510040; GFX900-NEXT:    v_cndmask_b32_e32 v24, v24, v8, vcc10041; GFX900-NEXT:    buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload10042; GFX900-NEXT:    buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload10043; GFX900-NEXT:    buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload10044; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v2410045; GFX900-NEXT:    v_lshlrev_b32_e32 v26, 16, v810046; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v26, v2510047; GFX900-NEXT:    v_cndmask_b32_e32 v25, v24, v8, vcc10048; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v810049; GFX900-NEXT:    v_cndmask_b32_e32 v8, v25, v8, vcc10050; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2410051; GFX900-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc10052; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v2510053; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2410054; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v710055; GFX900-NEXT:    v_cndmask_b32_e32 v8, v25, v8, vcc10056; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v24, v2410057; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v2310058; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc10059; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v24, v2410060; GFX900-NEXT:    v_cndmask_b32_e32 v23, v23, v7, vcc10061; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v2310062; GFX900-NEXT:    v_lshlrev_b32_e32 v25, 16, v710063; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v2410064; GFX900-NEXT:    v_cndmask_b32_e32 v24, v23, v7, vcc10065; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v710066; GFX900-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc10067; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2310068; GFX900-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc10069; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v2410070; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2310071; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v610072; GFX900-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc10073; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v23, v2310074; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v2210075; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc10076; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v23, v2310077; GFX900-NEXT:    v_cndmask_b32_e32 v22, v22, v6, vcc10078; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v2210079; GFX900-NEXT:    v_lshlrev_b32_e32 v24, 16, v610080; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v2310081; GFX900-NEXT:    v_cndmask_b32_e32 v23, v22, v6, vcc10082; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v610083; GFX900-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc10084; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2210085; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc10086; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v2310087; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2210088; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v510089; GFX900-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc10090; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v22, v2210091; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v2110092; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc10093; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v22, v2210094; GFX900-NEXT:    v_cndmask_b32_e32 v21, v21, v5, vcc10095; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v2110096; GFX900-NEXT:    v_lshlrev_b32_e32 v23, 16, v510097; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v23, v2210098; GFX900-NEXT:    v_cndmask_b32_e32 v22, v21, v5, vcc10099; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v510100; GFX900-NEXT:    v_cndmask_b32_e32 v5, v22, v5, vcc10101; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2110102; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc10103; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v2210104; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2110105; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v410106; GFX900-NEXT:    v_cndmask_b32_e32 v5, v22, v5, vcc10107; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v21, v2110108; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v2010109; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc10110; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v21, v2110111; GFX900-NEXT:    v_cndmask_b32_e32 v20, v20, v4, vcc10112; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v2010113; GFX900-NEXT:    v_lshlrev_b32_e32 v22, 16, v410114; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v22, v2110115; GFX900-NEXT:    v_cndmask_b32_e32 v21, v20, v4, vcc10116; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v410117; GFX900-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc10118; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v2010119; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc10120; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v2110121; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2010122; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v310123; GFX900-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc10124; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v20, v2010125; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v1910126; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc10127; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v20, v2010128; GFX900-NEXT:    v_cndmask_b32_e32 v19, v19, v3, vcc10129; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v1910130; GFX900-NEXT:    v_lshlrev_b32_e32 v21, 16, v310131; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v21, v2010132; GFX900-NEXT:    v_cndmask_b32_e32 v20, v19, v3, vcc10133; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v310134; GFX900-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc10135; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1910136; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc10137; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v2010138; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1910139; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v210140; GFX900-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc10141; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v19, v1910142; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v1810143; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc10144; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v19, v1910145; GFX900-NEXT:    v_cndmask_b32_e32 v18, v18, v2, vcc10146; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v1810147; GFX900-NEXT:    v_lshlrev_b32_e32 v20, 16, v210148; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v20, v1910149; GFX900-NEXT:    v_cndmask_b32_e32 v19, v18, v2, vcc10150; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v210151; GFX900-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc10152; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1810153; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc10154; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v1910155; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1810156; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v110157; GFX900-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc10158; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v18, v1810159; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v1710160; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc10161; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v18, v1810162; GFX900-NEXT:    v_cndmask_b32_e32 v17, v17, v1, vcc10163; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v1710164; GFX900-NEXT:    v_lshlrev_b32_e32 v19, 16, v110165; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v19, v1810166; GFX900-NEXT:    v_cndmask_b32_e32 v18, v17, v1, vcc10167; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v110168; GFX900-NEXT:    v_cndmask_b32_e32 v1, v18, v1, vcc10169; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1710170; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc10171; GFX900-NEXT:    v_lshlrev_b32_e32 v17, 16, v1810172; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1710173; GFX900-NEXT:    v_lshlrev_b32_e32 v17, 16, v010174; GFX900-NEXT:    v_cndmask_b32_e32 v1, v18, v1, vcc10175; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v17, v1710176; GFX900-NEXT:    v_lshlrev_b32_e32 v17, 16, v1610177; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc10178; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v17, v1710179; GFX900-NEXT:    v_cndmask_b32_e32 v16, v16, v0, vcc10180; GFX900-NEXT:    v_lshlrev_b32_e32 v17, 16, v1610181; GFX900-NEXT:    v_lshlrev_b32_e32 v18, 16, v010182; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v18, v1710183; GFX900-NEXT:    v_cndmask_b32_e32 v17, v16, v0, vcc10184; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v010185; GFX900-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc10186; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v1610187; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc10188; GFX900-NEXT:    v_lshlrev_b32_e32 v16, 16, v1710189; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1610190; GFX900-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc10191; GFX900-NEXT:    s_mov_b32 s4, 0x504010010192; GFX900-NEXT:    v_perm_b32 v0, v54, v0, s410193; GFX900-NEXT:    v_perm_b32 v1, v53, v1, s410194; GFX900-NEXT:    v_perm_b32 v2, v52, v2, s410195; GFX900-NEXT:    v_perm_b32 v3, v51, v3, s410196; GFX900-NEXT:    v_perm_b32 v4, v50, v4, s410197; GFX900-NEXT:    v_perm_b32 v5, v49, v5, s410198; GFX900-NEXT:    v_perm_b32 v6, v48, v6, s410199; GFX900-NEXT:    v_perm_b32 v7, v39, v7, s410200; GFX900-NEXT:    v_perm_b32 v8, v38, v8, s410201; GFX900-NEXT:    v_perm_b32 v9, v37, v9, s410202; GFX900-NEXT:    v_perm_b32 v10, v36, v10, s410203; GFX900-NEXT:    v_perm_b32 v11, v35, v11, s410204; GFX900-NEXT:    v_perm_b32 v12, v34, v12, s410205; GFX900-NEXT:    v_perm_b32 v13, v33, v13, s410206; GFX900-NEXT:    v_perm_b32 v14, v31, v14, s410207; GFX900-NEXT:    v_perm_b32 v15, v32, v15, s410208; GFX900-NEXT:    s_waitcnt vmcnt(0)10209; GFX900-NEXT:    s_setpc_b64 s[30:31]10210;10211; GFX950-LABEL: v_minimumnum_v32bf16:10212; GFX950:       ; %bb.0:10213; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10214; GFX950-NEXT:    scratch_load_dword v50, off, s3210215; GFX950-NEXT:    v_and_b32_e32 v31, 0xffff0000, v1410216; GFX950-NEXT:    v_lshrrev_b32_e32 v34, 16, v3010217; GFX950-NEXT:    v_lshrrev_b32_e32 v35, 16, v1410218; GFX950-NEXT:    v_and_b32_e32 v37, 0xffff0000, v1310219; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v31, v3110220; GFX950-NEXT:    v_and_b32_e32 v36, 0xffff0000, v3010221; GFX950-NEXT:    v_lshrrev_b32_e32 v38, 16, v2910222; GFX950-NEXT:    v_lshrrev_b32_e32 v39, 16, v1310223; GFX950-NEXT:    v_cndmask_b32_e32 v31, v35, v34, vcc10224; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v37, v3710225; GFX950-NEXT:    v_and_b32_e32 v48, 0xffff0000, v2910226; GFX950-NEXT:    v_lshlrev_b32_e32 v37, 16, v3110227; GFX950-NEXT:    v_cndmask_b32_e32 v35, v39, v38, vcc10228; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v36, v3610229; GFX950-NEXT:    v_lshlrev_b32_e32 v36, 16, v3510230; GFX950-NEXT:    s_movk_i32 s0, 0x800010231; GFX950-NEXT:    v_cndmask_b32_e32 v34, v34, v31, vcc10232; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v48, v4810233; GFX950-NEXT:    v_lshlrev_b32_e32 v39, 16, v3410234; GFX950-NEXT:    v_and_b32_e32 v32, 0xffff0000, v1510235; GFX950-NEXT:    v_cndmask_b32_e32 v38, v38, v35, vcc10236; GFX950-NEXT:    v_lshlrev_b32_e32 v48, 16, v3810237; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v37, v3910238; GFX950-NEXT:    v_lshrrev_b32_e32 v33, 16, v1510239; GFX950-NEXT:    v_and_b32_e32 v49, 0xffff0000, v2410240; GFX950-NEXT:    v_cndmask_b32_e32 v37, v34, v31, vcc10241; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v36, v4810242; GFX950-NEXT:    v_lshlrev_b32_e32 v39, 16, v3710243; GFX950-NEXT:    v_and_b32_e32 v51, 0xffff0000, v2310244; GFX950-NEXT:    v_cndmask_b32_e32 v36, v38, v35, vcc10245; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3110246; GFX950-NEXT:    v_lshlrev_b32_e32 v48, 16, v3610247; GFX950-NEXT:    v_and_b32_e32 v52, 0xffff0000, v2210248; GFX950-NEXT:    v_cndmask_b32_e32 v31, v37, v31, vcc10249; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3510250; GFX950-NEXT:    v_and_b32_e32 v53, 0xffff0000, v2110251; GFX950-NEXT:    v_and_b32_e32 v54, 0xffff0000, v2010252; GFX950-NEXT:    v_cndmask_b32_e32 v35, v36, v35, vcc10253; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3410254; GFX950-NEXT:    v_and_b32_e32 v55, 0xffff0000, v1910255; GFX950-NEXT:    v_accvgpr_write_b32 a0, v40 ; Reload Reuse10256; GFX950-NEXT:    v_cndmask_b32_e32 v31, v31, v34, vcc10257; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3810258; GFX950-NEXT:    v_and_b32_e32 v40, 0xffff0000, v1810259; GFX950-NEXT:    v_accvgpr_write_b32 a1, v41 ; Reload Reuse10260; GFX950-NEXT:    v_cndmask_b32_e32 v34, v35, v38, vcc10261; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3910262; GFX950-NEXT:    v_and_b32_e32 v38, 0xffff0000, v2710263; GFX950-NEXT:    v_and_b32_e32 v39, 0xffff0000, v2610264; GFX950-NEXT:    v_cndmask_b32_e32 v31, v37, v31, vcc10265; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v32, v3210266; GFX950-NEXT:    v_and_b32_e32 v41, 0xffff0000, v1710267; GFX950-NEXT:    v_accvgpr_write_b32 a2, v42 ; Reload Reuse10268; GFX950-NEXT:    v_and_b32_e32 v42, 0xffff0000, v1610269; GFX950-NEXT:    s_waitcnt vmcnt(0)10270; GFX950-NEXT:    v_lshrrev_b32_e32 v35, 16, v5010271; GFX950-NEXT:    v_and_b32_e32 v37, 0xffff0000, v5010272; GFX950-NEXT:    v_cndmask_b32_e32 v32, v33, v35, vcc10273; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v37, v3710274; GFX950-NEXT:    v_lshlrev_b32_e32 v33, 16, v3210275; GFX950-NEXT:    s_nop 010276; GFX950-NEXT:    v_cndmask_b32_e32 v35, v35, v32, vcc10277; GFX950-NEXT:    v_lshlrev_b32_e32 v37, 16, v3510278; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v33, v3710279; GFX950-NEXT:    s_nop 110280; GFX950-NEXT:    v_cndmask_b32_e32 v33, v35, v32, vcc10281; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3210282; GFX950-NEXT:    v_lshlrev_b32_e32 v37, 16, v3310283; GFX950-NEXT:    s_nop 010284; GFX950-NEXT:    v_cndmask_b32_e32 v32, v33, v32, vcc10285; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3510286; GFX950-NEXT:    s_nop 110287; GFX950-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc10288; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3710289; GFX950-NEXT:    v_lshrrev_b32_e32 v35, 16, v2810290; GFX950-NEXT:    v_and_b32_e32 v37, 0xffff0000, v2810291; GFX950-NEXT:    v_cndmask_b32_e32 v32, v33, v32, vcc10292; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4810293; GFX950-NEXT:    v_and_b32_e32 v48, 0xffff0000, v2510294; GFX950-NEXT:    s_nop 010295; GFX950-NEXT:    v_cndmask_b32_e32 v33, v36, v34, vcc10296; GFX950-NEXT:    v_and_b32_e32 v34, 0xffff0000, v1210297; GFX950-NEXT:    v_lshrrev_b32_e32 v36, 16, v1210298; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v34, v3410299; GFX950-NEXT:    s_nop 110300; GFX950-NEXT:    v_cndmask_b32_e32 v34, v36, v35, vcc10301; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v37, v3710302; GFX950-NEXT:    v_lshlrev_b32_e32 v36, 16, v3410303; GFX950-NEXT:    s_nop 010304; GFX950-NEXT:    v_cndmask_b32_e32 v35, v35, v34, vcc10305; GFX950-NEXT:    v_lshlrev_b32_e32 v37, 16, v3510306; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v36, v3710307; GFX950-NEXT:    v_lshrrev_b32_e32 v37, 16, v1110308; GFX950-NEXT:    s_nop 010309; GFX950-NEXT:    v_cndmask_b32_e32 v36, v35, v34, vcc10310; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3410311; GFX950-NEXT:    s_nop 110312; GFX950-NEXT:    v_cndmask_b32_e32 v34, v36, v34, vcc10313; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3510314; GFX950-NEXT:    s_nop 110315; GFX950-NEXT:    v_cndmask_b32_e32 v34, v34, v35, vcc10316; GFX950-NEXT:    v_lshlrev_b32_e32 v35, 16, v3610317; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3510318; GFX950-NEXT:    v_and_b32_e32 v35, 0xffff0000, v1110319; GFX950-NEXT:    s_nop 010320; GFX950-NEXT:    v_cndmask_b32_e32 v34, v36, v34, vcc10321; GFX950-NEXT:    v_lshrrev_b32_e32 v36, 16, v2710322; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v35, v3510323; GFX950-NEXT:    s_nop 110324; GFX950-NEXT:    v_cndmask_b32_e32 v35, v37, v36, vcc10325; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v38, v3810326; GFX950-NEXT:    v_lshlrev_b32_e32 v37, 16, v3510327; GFX950-NEXT:    s_nop 010328; GFX950-NEXT:    v_cndmask_b32_e32 v36, v36, v35, vcc10329; GFX950-NEXT:    v_lshlrev_b32_e32 v38, 16, v3610330; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v37, v3810331; GFX950-NEXT:    v_lshrrev_b32_e32 v38, 16, v1010332; GFX950-NEXT:    s_nop 010333; GFX950-NEXT:    v_cndmask_b32_e32 v37, v36, v35, vcc10334; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3510335; GFX950-NEXT:    s_nop 110336; GFX950-NEXT:    v_cndmask_b32_e32 v35, v37, v35, vcc10337; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3610338; GFX950-NEXT:    s_nop 110339; GFX950-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc10340; GFX950-NEXT:    v_lshlrev_b32_e32 v36, 16, v3710341; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3610342; GFX950-NEXT:    v_and_b32_e32 v36, 0xffff0000, v1010343; GFX950-NEXT:    s_nop 010344; GFX950-NEXT:    v_cndmask_b32_e32 v35, v37, v35, vcc10345; GFX950-NEXT:    v_lshrrev_b32_e32 v37, 16, v2610346; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v36, v3610347; GFX950-NEXT:    s_nop 110348; GFX950-NEXT:    v_cndmask_b32_e32 v36, v38, v37, vcc10349; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v39, v3910350; GFX950-NEXT:    v_lshlrev_b32_e32 v38, 16, v3610351; GFX950-NEXT:    s_nop 010352; GFX950-NEXT:    v_cndmask_b32_e32 v37, v37, v36, vcc10353; GFX950-NEXT:    v_lshlrev_b32_e32 v39, 16, v3710354; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v38, v3910355; GFX950-NEXT:    v_lshrrev_b32_e32 v39, 16, v910356; GFX950-NEXT:    s_nop 010357; GFX950-NEXT:    v_cndmask_b32_e32 v38, v37, v36, vcc10358; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3610359; GFX950-NEXT:    s_nop 110360; GFX950-NEXT:    v_cndmask_b32_e32 v36, v38, v36, vcc10361; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3710362; GFX950-NEXT:    s_nop 110363; GFX950-NEXT:    v_cndmask_b32_e32 v36, v36, v37, vcc10364; GFX950-NEXT:    v_lshlrev_b32_e32 v37, 16, v3810365; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3710366; GFX950-NEXT:    v_and_b32_e32 v37, 0xffff0000, v910367; GFX950-NEXT:    s_nop 010368; GFX950-NEXT:    v_cndmask_b32_e32 v36, v38, v36, vcc10369; GFX950-NEXT:    v_lshrrev_b32_e32 v38, 16, v2510370; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v37, v3710371; GFX950-NEXT:    s_nop 110372; GFX950-NEXT:    v_cndmask_b32_e32 v37, v39, v38, vcc10373; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v48, v4810374; GFX950-NEXT:    v_lshlrev_b32_e32 v39, 16, v3710375; GFX950-NEXT:    s_nop 010376; GFX950-NEXT:    v_cndmask_b32_e32 v38, v38, v37, vcc10377; GFX950-NEXT:    v_lshlrev_b32_e32 v48, 16, v3810378; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v39, v4810379; GFX950-NEXT:    v_lshrrev_b32_e32 v48, 16, v810380; GFX950-NEXT:    s_nop 010381; GFX950-NEXT:    v_cndmask_b32_e32 v39, v38, v37, vcc10382; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3710383; GFX950-NEXT:    s_nop 110384; GFX950-NEXT:    v_cndmask_b32_e32 v37, v39, v37, vcc10385; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3810386; GFX950-NEXT:    s_nop 110387; GFX950-NEXT:    v_cndmask_b32_e32 v37, v37, v38, vcc10388; GFX950-NEXT:    v_lshlrev_b32_e32 v38, 16, v3910389; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3810390; GFX950-NEXT:    v_and_b32_e32 v38, 0xffff0000, v810391; GFX950-NEXT:    s_nop 010392; GFX950-NEXT:    v_cndmask_b32_e32 v37, v39, v37, vcc10393; GFX950-NEXT:    v_lshrrev_b32_e32 v39, 16, v2410394; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v38, v3810395; GFX950-NEXT:    s_nop 110396; GFX950-NEXT:    v_cndmask_b32_e32 v38, v48, v39, vcc10397; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v49, v4910398; GFX950-NEXT:    v_lshlrev_b32_e32 v48, 16, v3810399; GFX950-NEXT:    s_nop 010400; GFX950-NEXT:    v_cndmask_b32_e32 v39, v39, v38, vcc10401; GFX950-NEXT:    v_lshlrev_b32_e32 v49, 16, v3910402; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v48, v4910403; GFX950-NEXT:    v_lshrrev_b32_e32 v49, 16, v710404; GFX950-NEXT:    s_nop 010405; GFX950-NEXT:    v_cndmask_b32_e32 v48, v39, v38, vcc10406; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3810407; GFX950-NEXT:    s_nop 110408; GFX950-NEXT:    v_cndmask_b32_e32 v38, v48, v38, vcc10409; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3910410; GFX950-NEXT:    s_nop 110411; GFX950-NEXT:    v_cndmask_b32_e32 v38, v38, v39, vcc10412; GFX950-NEXT:    v_lshlrev_b32_e32 v39, 16, v4810413; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3910414; GFX950-NEXT:    v_and_b32_e32 v39, 0xffff0000, v710415; GFX950-NEXT:    s_nop 010416; GFX950-NEXT:    v_cndmask_b32_e32 v38, v48, v38, vcc10417; GFX950-NEXT:    v_lshrrev_b32_e32 v48, 16, v2310418; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v39, v3910419; GFX950-NEXT:    s_nop 110420; GFX950-NEXT:    v_cndmask_b32_e32 v39, v49, v48, vcc10421; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v51, v5110422; GFX950-NEXT:    v_lshlrev_b32_e32 v49, 16, v3910423; GFX950-NEXT:    s_nop 010424; GFX950-NEXT:    v_cndmask_b32_e32 v48, v48, v39, vcc10425; GFX950-NEXT:    v_lshlrev_b32_e32 v51, 16, v4810426; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v49, v5110427; GFX950-NEXT:    v_lshrrev_b32_e32 v51, 16, v610428; GFX950-NEXT:    s_nop 010429; GFX950-NEXT:    v_cndmask_b32_e32 v49, v48, v39, vcc10430; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3910431; GFX950-NEXT:    s_nop 110432; GFX950-NEXT:    v_cndmask_b32_e32 v39, v49, v39, vcc10433; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v4810434; GFX950-NEXT:    s_nop 110435; GFX950-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc10436; GFX950-NEXT:    v_lshlrev_b32_e32 v48, 16, v4910437; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4810438; GFX950-NEXT:    v_and_b32_e32 v48, 0xffff0000, v610439; GFX950-NEXT:    s_nop 010440; GFX950-NEXT:    v_cndmask_b32_e32 v39, v49, v39, vcc10441; GFX950-NEXT:    v_lshrrev_b32_e32 v49, 16, v2210442; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v48, v4810443; GFX950-NEXT:    s_nop 110444; GFX950-NEXT:    v_cndmask_b32_e32 v48, v51, v49, vcc10445; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v52, v5210446; GFX950-NEXT:    v_lshlrev_b32_e32 v51, 16, v4810447; GFX950-NEXT:    s_nop 010448; GFX950-NEXT:    v_cndmask_b32_e32 v49, v49, v48, vcc10449; GFX950-NEXT:    v_lshlrev_b32_e32 v52, 16, v4910450; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v51, v5210451; GFX950-NEXT:    v_lshrrev_b32_e32 v52, 16, v510452; GFX950-NEXT:    s_nop 010453; GFX950-NEXT:    v_cndmask_b32_e32 v51, v49, v48, vcc10454; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v4810455; GFX950-NEXT:    s_nop 110456; GFX950-NEXT:    v_cndmask_b32_e32 v48, v51, v48, vcc10457; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v4910458; GFX950-NEXT:    s_nop 110459; GFX950-NEXT:    v_cndmask_b32_e32 v48, v48, v49, vcc10460; GFX950-NEXT:    v_lshlrev_b32_e32 v49, 16, v5110461; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4910462; GFX950-NEXT:    v_and_b32_e32 v49, 0xffff0000, v510463; GFX950-NEXT:    s_nop 010464; GFX950-NEXT:    v_cndmask_b32_e32 v48, v51, v48, vcc10465; GFX950-NEXT:    v_lshrrev_b32_e32 v51, 16, v2110466; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v49, v4910467; GFX950-NEXT:    s_nop 110468; GFX950-NEXT:    v_cndmask_b32_e32 v49, v52, v51, vcc10469; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v53, v5310470; GFX950-NEXT:    v_lshlrev_b32_e32 v52, 16, v4910471; GFX950-NEXT:    s_nop 010472; GFX950-NEXT:    v_cndmask_b32_e32 v51, v51, v49, vcc10473; GFX950-NEXT:    v_lshlrev_b32_e32 v53, 16, v5110474; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v52, v5310475; GFX950-NEXT:    v_lshrrev_b32_e32 v53, 16, v410476; GFX950-NEXT:    s_nop 010477; GFX950-NEXT:    v_cndmask_b32_e32 v52, v51, v49, vcc10478; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v4910479; GFX950-NEXT:    s_nop 110480; GFX950-NEXT:    v_cndmask_b32_e32 v49, v52, v49, vcc10481; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5110482; GFX950-NEXT:    s_nop 110483; GFX950-NEXT:    v_cndmask_b32_e32 v49, v49, v51, vcc10484; GFX950-NEXT:    v_lshlrev_b32_e32 v51, 16, v5210485; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v5110486; GFX950-NEXT:    v_and_b32_e32 v51, 0xffff0000, v410487; GFX950-NEXT:    s_nop 010488; GFX950-NEXT:    v_cndmask_b32_e32 v49, v52, v49, vcc10489; GFX950-NEXT:    v_lshrrev_b32_e32 v52, 16, v2010490; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v51, v5110491; GFX950-NEXT:    s_nop 110492; GFX950-NEXT:    v_cndmask_b32_e32 v51, v53, v52, vcc10493; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v54, v5410494; GFX950-NEXT:    v_lshlrev_b32_e32 v53, 16, v5110495; GFX950-NEXT:    s_nop 010496; GFX950-NEXT:    v_cndmask_b32_e32 v52, v52, v51, vcc10497; GFX950-NEXT:    v_lshlrev_b32_e32 v54, 16, v5210498; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v53, v5410499; GFX950-NEXT:    v_lshrrev_b32_e32 v54, 16, v310500; GFX950-NEXT:    s_nop 010501; GFX950-NEXT:    v_cndmask_b32_e32 v53, v52, v51, vcc10502; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5110503; GFX950-NEXT:    s_nop 110504; GFX950-NEXT:    v_cndmask_b32_e32 v51, v53, v51, vcc10505; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5210506; GFX950-NEXT:    s_nop 110507; GFX950-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc10508; GFX950-NEXT:    v_lshlrev_b32_e32 v52, 16, v5310509; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v5210510; GFX950-NEXT:    v_and_b32_e32 v52, 0xffff0000, v310511; GFX950-NEXT:    s_nop 010512; GFX950-NEXT:    v_cndmask_b32_e32 v51, v53, v51, vcc10513; GFX950-NEXT:    v_lshrrev_b32_e32 v53, 16, v1910514; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v52, v5210515; GFX950-NEXT:    s_nop 110516; GFX950-NEXT:    v_cndmask_b32_e32 v52, v54, v53, vcc10517; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v55, v5510518; GFX950-NEXT:    v_lshlrev_b32_e32 v54, 16, v5210519; GFX950-NEXT:    s_nop 010520; GFX950-NEXT:    v_cndmask_b32_e32 v53, v53, v52, vcc10521; GFX950-NEXT:    v_lshlrev_b32_e32 v55, 16, v5310522; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v54, v5510523; GFX950-NEXT:    v_lshrrev_b32_e32 v55, 16, v210524; GFX950-NEXT:    s_nop 010525; GFX950-NEXT:    v_cndmask_b32_e32 v54, v53, v52, vcc10526; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5210527; GFX950-NEXT:    s_nop 110528; GFX950-NEXT:    v_cndmask_b32_e32 v52, v54, v52, vcc10529; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5310530; GFX950-NEXT:    s_nop 110531; GFX950-NEXT:    v_cndmask_b32_e32 v52, v52, v53, vcc10532; GFX950-NEXT:    v_lshlrev_b32_e32 v53, 16, v5410533; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v5310534; GFX950-NEXT:    v_and_b32_e32 v53, 0xffff0000, v210535; GFX950-NEXT:    s_nop 010536; GFX950-NEXT:    v_cndmask_b32_e32 v52, v54, v52, vcc10537; GFX950-NEXT:    v_lshrrev_b32_e32 v54, 16, v1810538; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v53, v5310539; GFX950-NEXT:    s_nop 110540; GFX950-NEXT:    v_cndmask_b32_e32 v53, v55, v54, vcc10541; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v40, v4010542; GFX950-NEXT:    v_lshlrev_b32_e32 v55, 16, v5310543; GFX950-NEXT:    s_nop 010544; GFX950-NEXT:    v_cndmask_b32_e32 v54, v54, v53, vcc10545; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v5410546; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v55, v4010547; GFX950-NEXT:    v_lshrrev_b32_e32 v40, 16, v110548; GFX950-NEXT:    s_nop 010549; GFX950-NEXT:    v_cndmask_b32_e32 v55, v54, v53, vcc10550; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5310551; GFX950-NEXT:    s_nop 110552; GFX950-NEXT:    v_cndmask_b32_e32 v53, v55, v53, vcc10553; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5410554; GFX950-NEXT:    s_nop 110555; GFX950-NEXT:    v_cndmask_b32_e32 v53, v53, v54, vcc10556; GFX950-NEXT:    v_lshlrev_b32_e32 v54, 16, v5510557; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v5410558; GFX950-NEXT:    v_and_b32_e32 v54, 0xffff0000, v110559; GFX950-NEXT:    s_nop 010560; GFX950-NEXT:    v_cndmask_b32_e32 v53, v55, v53, vcc10561; GFX950-NEXT:    v_lshrrev_b32_e32 v55, 16, v1710562; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v54, v5410563; GFX950-NEXT:    s_nop 110564; GFX950-NEXT:    v_cndmask_b32_e32 v54, v40, v55, vcc10565; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v41, v4110566; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v5410567; GFX950-NEXT:    s_nop 010568; GFX950-NEXT:    v_cndmask_b32_e32 v55, v55, v54, vcc10569; GFX950-NEXT:    v_lshlrev_b32_e32 v41, 16, v5510570; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v40, v4110571; GFX950-NEXT:    v_lshrrev_b32_e32 v41, 16, v010572; GFX950-NEXT:    s_nop 010573; GFX950-NEXT:    v_cndmask_b32_e32 v40, v55, v54, vcc10574; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5410575; GFX950-NEXT:    s_nop 110576; GFX950-NEXT:    v_cndmask_b32_e32 v54, v40, v54, vcc10577; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5510578; GFX950-NEXT:    s_nop 110579; GFX950-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc10580; GFX950-NEXT:    v_lshlrev_b32_e32 v55, 16, v4010581; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v5510582; GFX950-NEXT:    v_and_b32_e32 v55, 0xffff0000, v010583; GFX950-NEXT:    s_nop 010584; GFX950-NEXT:    v_cndmask_b32_e32 v54, v40, v54, vcc10585; GFX950-NEXT:    v_lshrrev_b32_e32 v40, 16, v1610586; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v55, v5510587; GFX950-NEXT:    s_nop 110588; GFX950-NEXT:    v_cndmask_b32_e32 v55, v41, v40, vcc10589; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v42, v4210590; GFX950-NEXT:    v_lshlrev_b32_e32 v41, 16, v5510591; GFX950-NEXT:    s_nop 010592; GFX950-NEXT:    v_cndmask_b32_e32 v40, v40, v55, vcc10593; GFX950-NEXT:    v_lshlrev_b32_e32 v42, 16, v4010594; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v41, v4210595; GFX950-NEXT:    v_accvgpr_read_b32 v42, a2 ; Reload Reuse10596; GFX950-NEXT:    s_nop 010597; GFX950-NEXT:    v_cndmask_b32_e32 v41, v40, v55, vcc10598; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5510599; GFX950-NEXT:    s_nop 110600; GFX950-NEXT:    v_cndmask_b32_e32 v55, v41, v55, vcc10601; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v4010602; GFX950-NEXT:    s_nop 110603; GFX950-NEXT:    v_cndmask_b32_e32 v55, v55, v40, vcc10604; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v4110605; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4010606; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v1510607; GFX950-NEXT:    s_nop 010608; GFX950-NEXT:    v_cndmask_b32_e32 v55, v41, v55, vcc10609; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v40, v4010610; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v5010611; GFX950-NEXT:    s_nop 010612; GFX950-NEXT:    v_cndmask_b32_e32 v15, v15, v50, vcc10613; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v40, v4010614; GFX950-NEXT:    v_lshlrev_b32_e32 v41, 16, v1510615; GFX950-NEXT:    s_nop 010616; GFX950-NEXT:    v_cndmask_b32_e32 v50, v50, v15, vcc10617; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v5010618; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v41, v4010619; GFX950-NEXT:    v_accvgpr_read_b32 v41, a1 ; Reload Reuse10620; GFX950-NEXT:    s_nop 010621; GFX950-NEXT:    v_cndmask_b32_e32 v40, v50, v15, vcc10622; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1510623; GFX950-NEXT:    s_nop 110624; GFX950-NEXT:    v_cndmask_b32_e32 v15, v40, v15, vcc10625; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v5010626; GFX950-NEXT:    s_nop 110627; GFX950-NEXT:    v_cndmask_b32_e32 v15, v15, v50, vcc10628; GFX950-NEXT:    v_lshlrev_b32_e32 v50, 16, v4010629; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v5010630; GFX950-NEXT:    v_lshlrev_b32_e32 v50, 16, v1410631; GFX950-NEXT:    s_nop 010632; GFX950-NEXT:    v_cndmask_b32_e32 v15, v40, v15, vcc10633; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v50, v5010634; GFX950-NEXT:    v_lshlrev_b32_e32 v50, 16, v3010635; GFX950-NEXT:    s_nop 010636; GFX950-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc10637; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v50, v5010638; GFX950-NEXT:    v_lshlrev_b32_e32 v40, 16, v1410639; GFX950-NEXT:    s_nop 010640; GFX950-NEXT:    v_cndmask_b32_e32 v30, v30, v14, vcc10641; GFX950-NEXT:    v_lshlrev_b32_e32 v50, 16, v3010642; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v40, v5010643; GFX950-NEXT:    v_accvgpr_read_b32 v40, a0 ; Reload Reuse10644; GFX950-NEXT:    s_nop 010645; GFX950-NEXT:    v_cndmask_b32_e32 v50, v30, v14, vcc10646; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1410647; GFX950-NEXT:    s_nop 110648; GFX950-NEXT:    v_cndmask_b32_e32 v14, v50, v14, vcc10649; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v3010650; GFX950-NEXT:    s_nop 110651; GFX950-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc10652; GFX950-NEXT:    v_lshlrev_b32_e32 v30, 16, v5010653; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3010654; GFX950-NEXT:    v_lshlrev_b32_e32 v30, 16, v1310655; GFX950-NEXT:    s_nop 010656; GFX950-NEXT:    v_cndmask_b32_e32 v14, v50, v14, vcc10657; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v30, v3010658; GFX950-NEXT:    v_lshlrev_b32_e32 v30, 16, v2910659; GFX950-NEXT:    s_nop 010660; GFX950-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc10661; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v30, v3010662; GFX950-NEXT:    v_lshlrev_b32_e32 v50, 16, v1310663; GFX950-NEXT:    s_nop 010664; GFX950-NEXT:    v_cndmask_b32_e32 v29, v29, v13, vcc10665; GFX950-NEXT:    v_lshlrev_b32_e32 v30, 16, v2910666; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v50, v3010667; GFX950-NEXT:    s_nop 110668; GFX950-NEXT:    v_cndmask_b32_e32 v30, v29, v13, vcc10669; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1310670; GFX950-NEXT:    s_nop 110671; GFX950-NEXT:    v_cndmask_b32_e32 v13, v30, v13, vcc10672; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2910673; GFX950-NEXT:    s_nop 110674; GFX950-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc10675; GFX950-NEXT:    v_lshlrev_b32_e32 v29, 16, v3010676; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2910677; GFX950-NEXT:    v_lshlrev_b32_e32 v29, 16, v1210678; GFX950-NEXT:    s_nop 010679; GFX950-NEXT:    v_cndmask_b32_e32 v13, v30, v13, vcc10680; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v29, v2910681; GFX950-NEXT:    v_lshlrev_b32_e32 v29, 16, v2810682; GFX950-NEXT:    s_nop 010683; GFX950-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc10684; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v29, v2910685; GFX950-NEXT:    v_lshlrev_b32_e32 v30, 16, v1210686; GFX950-NEXT:    s_nop 010687; GFX950-NEXT:    v_cndmask_b32_e32 v28, v28, v12, vcc10688; GFX950-NEXT:    v_lshlrev_b32_e32 v29, 16, v2810689; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v30, v2910690; GFX950-NEXT:    s_nop 110691; GFX950-NEXT:    v_cndmask_b32_e32 v29, v28, v12, vcc10692; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1210693; GFX950-NEXT:    s_nop 110694; GFX950-NEXT:    v_cndmask_b32_e32 v12, v29, v12, vcc10695; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2810696; GFX950-NEXT:    s_nop 110697; GFX950-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc10698; GFX950-NEXT:    v_lshlrev_b32_e32 v28, 16, v2910699; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2810700; GFX950-NEXT:    v_lshlrev_b32_e32 v28, 16, v1110701; GFX950-NEXT:    s_nop 010702; GFX950-NEXT:    v_cndmask_b32_e32 v12, v29, v12, vcc10703; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v28, v2810704; GFX950-NEXT:    v_lshlrev_b32_e32 v28, 16, v2710705; GFX950-NEXT:    s_nop 010706; GFX950-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc10707; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v28, v2810708; GFX950-NEXT:    v_lshlrev_b32_e32 v29, 16, v1110709; GFX950-NEXT:    s_nop 010710; GFX950-NEXT:    v_cndmask_b32_e32 v27, v27, v11, vcc10711; GFX950-NEXT:    v_lshlrev_b32_e32 v28, 16, v2710712; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v29, v2810713; GFX950-NEXT:    s_nop 110714; GFX950-NEXT:    v_cndmask_b32_e32 v28, v27, v11, vcc10715; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1110716; GFX950-NEXT:    s_nop 110717; GFX950-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc10718; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2710719; GFX950-NEXT:    s_nop 110720; GFX950-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc10721; GFX950-NEXT:    v_lshlrev_b32_e32 v27, 16, v2810722; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2710723; GFX950-NEXT:    v_lshlrev_b32_e32 v27, 16, v1010724; GFX950-NEXT:    s_nop 010725; GFX950-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc10726; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v27, v2710727; GFX950-NEXT:    v_lshlrev_b32_e32 v27, 16, v2610728; GFX950-NEXT:    s_nop 010729; GFX950-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc10730; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v27, v2710731; GFX950-NEXT:    v_lshlrev_b32_e32 v28, 16, v1010732; GFX950-NEXT:    s_nop 010733; GFX950-NEXT:    v_cndmask_b32_e32 v26, v26, v10, vcc10734; GFX950-NEXT:    v_lshlrev_b32_e32 v27, 16, v2610735; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v28, v2710736; GFX950-NEXT:    s_nop 110737; GFX950-NEXT:    v_cndmask_b32_e32 v27, v26, v10, vcc10738; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1010739; GFX950-NEXT:    s_nop 110740; GFX950-NEXT:    v_cndmask_b32_e32 v10, v27, v10, vcc10741; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2610742; GFX950-NEXT:    s_nop 110743; GFX950-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc10744; GFX950-NEXT:    v_lshlrev_b32_e32 v26, 16, v2710745; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2610746; GFX950-NEXT:    v_lshlrev_b32_e32 v26, 16, v910747; GFX950-NEXT:    s_nop 010748; GFX950-NEXT:    v_cndmask_b32_e32 v10, v27, v10, vcc10749; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v26, v2610750; GFX950-NEXT:    v_lshlrev_b32_e32 v26, 16, v2510751; GFX950-NEXT:    s_nop 010752; GFX950-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc10753; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v26, v2610754; GFX950-NEXT:    v_lshlrev_b32_e32 v27, 16, v910755; GFX950-NEXT:    s_nop 010756; GFX950-NEXT:    v_cndmask_b32_e32 v25, v25, v9, vcc10757; GFX950-NEXT:    v_lshlrev_b32_e32 v26, 16, v2510758; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v27, v2610759; GFX950-NEXT:    s_nop 110760; GFX950-NEXT:    v_cndmask_b32_e32 v26, v25, v9, vcc10761; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v910762; GFX950-NEXT:    s_nop 110763; GFX950-NEXT:    v_cndmask_b32_e32 v9, v26, v9, vcc10764; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2510765; GFX950-NEXT:    s_nop 110766; GFX950-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc10767; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v2610768; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2510769; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v810770; GFX950-NEXT:    s_nop 010771; GFX950-NEXT:    v_cndmask_b32_e32 v9, v26, v9, vcc10772; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v25, v2510773; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v2410774; GFX950-NEXT:    s_nop 010775; GFX950-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc10776; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v25, v2510777; GFX950-NEXT:    v_lshlrev_b32_e32 v26, 16, v810778; GFX950-NEXT:    s_nop 010779; GFX950-NEXT:    v_cndmask_b32_e32 v24, v24, v8, vcc10780; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v2410781; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v26, v2510782; GFX950-NEXT:    s_nop 110783; GFX950-NEXT:    v_cndmask_b32_e32 v25, v24, v8, vcc10784; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v810785; GFX950-NEXT:    s_nop 110786; GFX950-NEXT:    v_cndmask_b32_e32 v8, v25, v8, vcc10787; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2410788; GFX950-NEXT:    s_nop 110789; GFX950-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc10790; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v2510791; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2410792; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v710793; GFX950-NEXT:    s_nop 010794; GFX950-NEXT:    v_cndmask_b32_e32 v8, v25, v8, vcc10795; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v24, v2410796; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v2310797; GFX950-NEXT:    s_nop 010798; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc10799; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v24, v2410800; GFX950-NEXT:    v_lshlrev_b32_e32 v25, 16, v710801; GFX950-NEXT:    s_nop 010802; GFX950-NEXT:    v_cndmask_b32_e32 v23, v23, v7, vcc10803; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v2310804; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v25, v2410805; GFX950-NEXT:    s_nop 110806; GFX950-NEXT:    v_cndmask_b32_e32 v24, v23, v7, vcc10807; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v710808; GFX950-NEXT:    s_nop 110809; GFX950-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc10810; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2310811; GFX950-NEXT:    s_nop 110812; GFX950-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc10813; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v2410814; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2310815; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v610816; GFX950-NEXT:    s_nop 010817; GFX950-NEXT:    v_cndmask_b32_e32 v7, v24, v7, vcc10818; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v23, v2310819; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v2210820; GFX950-NEXT:    s_nop 010821; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc10822; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v23, v2310823; GFX950-NEXT:    v_lshlrev_b32_e32 v24, 16, v610824; GFX950-NEXT:    s_nop 010825; GFX950-NEXT:    v_cndmask_b32_e32 v22, v22, v6, vcc10826; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v2210827; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v24, v2310828; GFX950-NEXT:    s_nop 110829; GFX950-NEXT:    v_cndmask_b32_e32 v23, v22, v6, vcc10830; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v610831; GFX950-NEXT:    s_nop 110832; GFX950-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc10833; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2210834; GFX950-NEXT:    s_nop 110835; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc10836; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v2310837; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2210838; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v510839; GFX950-NEXT:    s_nop 010840; GFX950-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc10841; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v22, v2210842; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v2110843; GFX950-NEXT:    s_nop 010844; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc10845; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v22, v2210846; GFX950-NEXT:    v_lshlrev_b32_e32 v23, 16, v510847; GFX950-NEXT:    s_nop 010848; GFX950-NEXT:    v_cndmask_b32_e32 v21, v21, v5, vcc10849; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v2110850; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v23, v2210851; GFX950-NEXT:    s_nop 110852; GFX950-NEXT:    v_cndmask_b32_e32 v22, v21, v5, vcc10853; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v510854; GFX950-NEXT:    s_nop 110855; GFX950-NEXT:    v_cndmask_b32_e32 v5, v22, v5, vcc10856; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2110857; GFX950-NEXT:    s_nop 110858; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc10859; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v2210860; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2110861; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v410862; GFX950-NEXT:    s_nop 010863; GFX950-NEXT:    v_cndmask_b32_e32 v5, v22, v5, vcc10864; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v21, v2110865; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v2010866; GFX950-NEXT:    s_nop 010867; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc10868; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v21, v2110869; GFX950-NEXT:    v_lshlrev_b32_e32 v22, 16, v410870; GFX950-NEXT:    s_nop 010871; GFX950-NEXT:    v_cndmask_b32_e32 v20, v20, v4, vcc10872; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v2010873; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v22, v2110874; GFX950-NEXT:    s_nop 110875; GFX950-NEXT:    v_cndmask_b32_e32 v21, v20, v4, vcc10876; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v410877; GFX950-NEXT:    s_nop 110878; GFX950-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc10879; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v2010880; GFX950-NEXT:    s_nop 110881; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc10882; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v2110883; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2010884; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v310885; GFX950-NEXT:    s_nop 010886; GFX950-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc10887; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v20, v2010888; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v1910889; GFX950-NEXT:    s_nop 010890; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc10891; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v20, v2010892; GFX950-NEXT:    v_lshlrev_b32_e32 v21, 16, v310893; GFX950-NEXT:    s_nop 010894; GFX950-NEXT:    v_cndmask_b32_e32 v19, v19, v3, vcc10895; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v1910896; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v21, v2010897; GFX950-NEXT:    s_nop 110898; GFX950-NEXT:    v_cndmask_b32_e32 v20, v19, v3, vcc10899; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v310900; GFX950-NEXT:    s_nop 110901; GFX950-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc10902; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1910903; GFX950-NEXT:    s_nop 110904; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc10905; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v2010906; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1910907; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v210908; GFX950-NEXT:    s_nop 010909; GFX950-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc10910; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v19, v1910911; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v1810912; GFX950-NEXT:    s_nop 010913; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc10914; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v19, v1910915; GFX950-NEXT:    v_lshlrev_b32_e32 v20, 16, v210916; GFX950-NEXT:    s_nop 010917; GFX950-NEXT:    v_cndmask_b32_e32 v18, v18, v2, vcc10918; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v1810919; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v20, v1910920; GFX950-NEXT:    s_nop 110921; GFX950-NEXT:    v_cndmask_b32_e32 v19, v18, v2, vcc10922; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v210923; GFX950-NEXT:    s_nop 110924; GFX950-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc10925; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1810926; GFX950-NEXT:    s_nop 110927; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc10928; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v1910929; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1810930; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v110931; GFX950-NEXT:    s_nop 010932; GFX950-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc10933; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v18, v1810934; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v1710935; GFX950-NEXT:    s_nop 010936; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc10937; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v18, v1810938; GFX950-NEXT:    v_lshlrev_b32_e32 v19, 16, v110939; GFX950-NEXT:    s_nop 010940; GFX950-NEXT:    v_cndmask_b32_e32 v17, v17, v1, vcc10941; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v1710942; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v19, v1810943; GFX950-NEXT:    s_nop 110944; GFX950-NEXT:    v_cndmask_b32_e32 v18, v17, v1, vcc10945; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v110946; GFX950-NEXT:    s_nop 110947; GFX950-NEXT:    v_cndmask_b32_e32 v1, v18, v1, vcc10948; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1710949; GFX950-NEXT:    s_nop 110950; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc10951; GFX950-NEXT:    v_lshlrev_b32_e32 v17, 16, v1810952; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1710953; GFX950-NEXT:    v_lshlrev_b32_e32 v17, 16, v010954; GFX950-NEXT:    s_nop 010955; GFX950-NEXT:    v_cndmask_b32_e32 v1, v18, v1, vcc10956; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v17, v1710957; GFX950-NEXT:    v_lshlrev_b32_e32 v17, 16, v1610958; GFX950-NEXT:    s_nop 010959; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc10960; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v17, v1710961; GFX950-NEXT:    v_lshlrev_b32_e32 v18, 16, v010962; GFX950-NEXT:    s_nop 010963; GFX950-NEXT:    v_cndmask_b32_e32 v16, v16, v0, vcc10964; GFX950-NEXT:    v_lshlrev_b32_e32 v17, 16, v1610965; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v18, v1710966; GFX950-NEXT:    s_nop 110967; GFX950-NEXT:    v_cndmask_b32_e32 v17, v16, v0, vcc10968; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v010969; GFX950-NEXT:    s_nop 110970; GFX950-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc10971; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v1610972; GFX950-NEXT:    s_mov_b32 s0, 0x504010010973; GFX950-NEXT:    v_perm_b32 v1, v54, v1, s010974; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc10975; GFX950-NEXT:    v_lshlrev_b32_e32 v16, 16, v1710976; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1610977; GFX950-NEXT:    v_perm_b32 v2, v53, v2, s010978; GFX950-NEXT:    v_perm_b32 v3, v52, v3, s010979; GFX950-NEXT:    v_cndmask_b32_e32 v0, v17, v0, vcc10980; GFX950-NEXT:    v_perm_b32 v0, v55, v0, s010981; GFX950-NEXT:    v_perm_b32 v4, v51, v4, s010982; GFX950-NEXT:    v_perm_b32 v5, v49, v5, s010983; GFX950-NEXT:    v_perm_b32 v6, v48, v6, s010984; GFX950-NEXT:    v_perm_b32 v7, v39, v7, s010985; GFX950-NEXT:    v_perm_b32 v8, v38, v8, s010986; GFX950-NEXT:    v_perm_b32 v9, v37, v9, s010987; GFX950-NEXT:    v_perm_b32 v10, v36, v10, s010988; GFX950-NEXT:    v_perm_b32 v11, v35, v11, s010989; GFX950-NEXT:    v_perm_b32 v12, v34, v12, s010990; GFX950-NEXT:    v_perm_b32 v13, v33, v13, s010991; GFX950-NEXT:    v_perm_b32 v14, v31, v14, s010992; GFX950-NEXT:    v_perm_b32 v15, v32, v15, s010993; GFX950-NEXT:    s_setpc_b64 s[30:31]10994;10995; GFX10-LABEL: v_minimumnum_v32bf16:10996; GFX10:       ; %bb.0:10997; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10998; GFX10-NEXT:    v_and_b32_e32 v31, 0xffff0000, v1310999; GFX10-NEXT:    v_lshrrev_b32_e32 v35, 16, v2911000; GFX10-NEXT:    v_lshrrev_b32_e32 v32, 16, v1311001; GFX10-NEXT:    v_and_b32_e32 v33, 0xffff0000, v1211002; GFX10-NEXT:    v_lshrrev_b32_e32 v38, 16, v2811003; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v3111004; GFX10-NEXT:    v_lshrrev_b32_e32 v34, 16, v1211005; GFX10-NEXT:    v_and_b32_e32 v37, 0xffff0000, v1111006; GFX10-NEXT:    v_and_b32_e32 v36, 0xffff0000, v2911007; GFX10-NEXT:    v_lshrrev_b32_e32 v39, 16, v2711008; GFX10-NEXT:    v_cndmask_b32_e32 v32, v32, v35, vcc_lo11009; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v33, v3311010; GFX10-NEXT:    v_lshrrev_b32_e32 v48, 16, v1111011; GFX10-NEXT:    v_and_b32_e32 v49, 0xffff0000, v2811012; GFX10-NEXT:    v_and_b32_e32 v51, 0xffff0000, v1011013; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v3211014; GFX10-NEXT:    v_cndmask_b32_e32 v34, v34, v38, vcc_lo11015; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v3711016; GFX10-NEXT:    v_lshrrev_b32_e32 v52, 16, v2611017; GFX10-NEXT:    v_lshrrev_b32_e32 v53, 16, v1011018; GFX10-NEXT:    v_cmp_u_f32_e64 s6, v51, v5111019; GFX10-NEXT:    v_lshrrev_b32_e32 v54, 16, v811020; GFX10-NEXT:    v_cndmask_b32_e32 v33, v48, v39, vcc_lo11021; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v36, v3611022; GFX10-NEXT:    v_and_b32_e32 v48, 0xffff0000, v2711023; GFX10-NEXT:    v_lshrrev_b32_e32 v64, 16, v2311024; GFX10-NEXT:    v_lshrrev_b32_e32 v65, 16, v711025; GFX10-NEXT:    v_lshrrev_b32_e32 v66, 16, v2211026; GFX10-NEXT:    v_cndmask_b32_e32 v37, v35, v32, vcc_lo11027; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v4911028; GFX10-NEXT:    v_lshlrev_b32_e32 v49, 16, v3311029; GFX10-NEXT:    v_lshrrev_b32_e32 v67, 16, v611030; GFX10-NEXT:    v_lshrrev_b32_e32 v70, 16, v411031; GFX10-NEXT:    v_and_b32_e32 v71, 0xffff0000, v2011032; GFX10-NEXT:    v_cndmask_b32_e32 v36, v38, v34, vcc_lo11033; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v48, v4811034; GFX10-NEXT:    v_lshlrev_b32_e32 v38, 16, v3711035; GFX10-NEXT:    v_lshrrev_b32_e32 v80, 16, v311036; GFX10-NEXT:    v_lshrrev_b32_e32 v85, 16, v1411037; GFX10-NEXT:    v_lshlrev_b32_e32 v48, 16, v3611038; GFX10-NEXT:    v_cndmask_b32_e32 v35, v39, v33, vcc_lo11039; GFX10-NEXT:    v_lshlrev_b32_e32 v39, 16, v3411040; GFX10-NEXT:    v_cmp_lt_f32_e64 s5, v31, v3811041; GFX10-NEXT:    v_and_b32_e32 v31, 0xffff0000, v2611042; GFX10-NEXT:    v_cndmask_b32_e64 v38, v53, v52, s611043; GFX10-NEXT:    v_lshlrev_b32_e32 v50, 16, v3511044; GFX10-NEXT:    v_cmp_lt_f32_e64 s4, v39, v4811045; GFX10-NEXT:    v_and_b32_e32 v39, 0xffff0000, v911046; GFX10-NEXT:    v_cmp_u_f32_e64 s6, v31, v3111047; GFX10-NEXT:    v_and_b32_e32 v31, 0xffff0000, v2511048; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v49, v5011049; GFX10-NEXT:    v_lshrrev_b32_e32 v49, 16, v2511050; GFX10-NEXT:    v_lshrrev_b32_e32 v50, 16, v911051; GFX10-NEXT:    v_cndmask_b32_e64 v48, v52, v38, s611052; GFX10-NEXT:    v_cmp_u_f32_e64 s6, v39, v3911053; GFX10-NEXT:    v_and_b32_e32 v52, 0xffff0000, v811054; GFX10-NEXT:    v_lshlrev_b32_e32 v51, 16, v3811055; GFX10-NEXT:    v_lshrrev_b32_e32 v53, 16, v2411056; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v4811057; GFX10-NEXT:    v_cndmask_b32_e64 v39, v50, v49, s611058; GFX10-NEXT:    v_cmp_u_f32_e64 s6, v31, v3111059; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v3911060; GFX10-NEXT:    v_cndmask_b32_e64 v50, v49, v39, s611061; GFX10-NEXT:    v_cmp_u_f32_e64 s6, v52, v5211062; GFX10-NEXT:    v_and_b32_e32 v52, 0xffff0000, v2411063; GFX10-NEXT:    v_cndmask_b32_e64 v49, v54, v53, s611064; GFX10-NEXT:    v_cmp_lt_f32_e64 s6, v51, v5511065; GFX10-NEXT:    v_and_b32_e32 v55, 0xffff0000, v711066; GFX10-NEXT:    v_cmp_u_f32_e64 s7, v52, v5211067; GFX10-NEXT:    v_lshlrev_b32_e32 v51, 16, v5011068; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v4911069; GFX10-NEXT:    v_cndmask_b32_e64 v52, v53, v49, s711070; GFX10-NEXT:    v_and_b32_e32 v53, 0xffff0000, v2311071; GFX10-NEXT:    v_cmp_u_f32_e64 s7, v55, v5511072; GFX10-NEXT:    v_cmp_lt_f32_e64 s8, v31, v5111073; GFX10-NEXT:    v_cndmask_b32_e64 v55, v65, v64, s711074; GFX10-NEXT:    v_and_b32_e32 v65, 0xffff0000, v611075; GFX10-NEXT:    v_cmp_u_f32_e64 s7, v53, v5311076; GFX10-NEXT:    v_lshlrev_b32_e32 v68, 16, v5511077; GFX10-NEXT:    v_cndmask_b32_e64 v53, v64, v55, s711078; GFX10-NEXT:    v_cmp_u_f32_e64 s7, v65, v6511079; GFX10-NEXT:    v_and_b32_e32 v64, 0xffff0000, v2211080; GFX10-NEXT:    v_lshlrev_b32_e32 v69, 16, v5311081; GFX10-NEXT:    v_cndmask_b32_e64 v65, v67, v66, s711082; GFX10-NEXT:    v_lshlrev_b32_e32 v67, 16, v5211083; GFX10-NEXT:    v_cmp_u_f32_e64 s7, v64, v6411084; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v6511085; GFX10-NEXT:    v_cmp_lt_f32_e64 s9, v54, v6711086; GFX10-NEXT:    v_and_b32_e32 v54, 0xffff0000, v511087; GFX10-NEXT:    v_cndmask_b32_e64 v64, v66, v65, s711088; GFX10-NEXT:    v_cmp_lt_f32_e64 s7, v68, v6911089; GFX10-NEXT:    v_lshrrev_b32_e32 v66, 16, v2111090; GFX10-NEXT:    v_lshrrev_b32_e32 v67, 16, v511091; GFX10-NEXT:    v_and_b32_e32 v68, 0xffff0000, v411092; GFX10-NEXT:    v_cmp_u_f32_e64 s10, v54, v5411093; GFX10-NEXT:    v_lshrrev_b32_e32 v69, 16, v2011094; GFX10-NEXT:    v_lshlrev_b32_e32 v51, 16, v6411095; GFX10-NEXT:    v_cndmask_b32_e64 v54, v67, v66, s1011096; GFX10-NEXT:    v_and_b32_e32 v67, 0xffff0000, v2111097; GFX10-NEXT:    v_cmp_u_f32_e64 s10, v68, v6811098; GFX10-NEXT:    v_cndmask_b32_e64 v68, v70, v69, s1011099; GFX10-NEXT:    v_cmp_u_f32_e64 s10, v67, v6711100; GFX10-NEXT:    v_lshlrev_b32_e32 v70, 16, v5411101; GFX10-NEXT:    v_lshlrev_b32_e32 v82, 16, v6811102; GFX10-NEXT:    v_cndmask_b32_e64 v66, v66, v54, s1011103; GFX10-NEXT:    v_cmp_u_f32_e64 s10, v71, v7111104; GFX10-NEXT:    v_lshrrev_b32_e32 v71, 16, v1911105; GFX10-NEXT:    v_lshlrev_b32_e32 v81, 16, v6611106; GFX10-NEXT:    v_cndmask_b32_e64 v67, v69, v68, s1011107; GFX10-NEXT:    v_and_b32_e32 v69, 0xffff0000, v311108; GFX10-NEXT:    v_cmp_lt_f32_e64 s11, v70, v8111109; GFX10-NEXT:    v_lshlrev_b32_e32 v83, 16, v6711110; GFX10-NEXT:    v_cmp_u_f32_e64 s10, v69, v6911111; GFX10-NEXT:    v_and_b32_e32 v70, 0xffff0000, v211112; GFX10-NEXT:    v_lshrrev_b32_e32 v81, 16, v211113; GFX10-NEXT:    v_cmp_lt_f32_e64 s12, v82, v8311114; GFX10-NEXT:    v_cndmask_b32_e64 v69, v80, v71, s1011115; GFX10-NEXT:    v_cmp_lt_f32_e64 s10, v31, v5111116; GFX10-NEXT:    v_and_b32_e32 v51, 0xffff0000, v1911117; GFX10-NEXT:    v_lshrrev_b32_e32 v80, 16, v1811118; GFX10-NEXT:    v_and_b32_e32 v82, 0xffff0000, v1811119; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v6911120; GFX10-NEXT:    v_cmp_u_f32_e64 s13, v51, v5111121; GFX10-NEXT:    v_cndmask_b32_e64 v51, v71, v69, s1311122; GFX10-NEXT:    v_cmp_u_f32_e64 s13, v70, v7011123; GFX10-NEXT:    v_and_b32_e32 v71, 0xffff0000, v111124; GFX10-NEXT:    v_lshlrev_b32_e32 v83, 16, v5111125; GFX10-NEXT:    v_cndmask_b32_e64 v70, v81, v80, s1311126; GFX10-NEXT:    v_cmp_u_f32_e64 s13, v82, v8211127; GFX10-NEXT:    v_lshrrev_b32_e32 v81, 16, v1711128; GFX10-NEXT:    v_lshrrev_b32_e32 v82, 16, v111129; GFX10-NEXT:    v_cndmask_b32_e64 v80, v80, v70, s1311130; GFX10-NEXT:    v_cmp_u_f32_e64 s13, v71, v7111131; GFX10-NEXT:    v_and_b32_e32 v71, 0xffff0000, v1711132; GFX10-NEXT:    v_cndmask_b32_e64 v82, v82, v81, s1311133; GFX10-NEXT:    v_cmp_u_f32_e64 s14, v71, v7111134; GFX10-NEXT:    v_cmp_lt_f32_e64 s13, v31, v8311135; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v7011136; GFX10-NEXT:    v_lshlrev_b32_e32 v83, 16, v8011137; GFX10-NEXT:    v_cndmask_b32_e64 v71, v81, v82, s1411138; GFX10-NEXT:    v_cmp_lt_f32_e64 s14, v31, v8311139; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v8211140; GFX10-NEXT:    v_lshlrev_b32_e32 v81, 16, v7111141; GFX10-NEXT:    v_lshrrev_b32_e32 v83, 16, v011142; GFX10-NEXT:    v_cmp_lt_f32_e64 s15, v31, v8111143; GFX10-NEXT:    v_and_b32_e32 v31, 0xffff0000, v011144; GFX10-NEXT:    v_lshrrev_b32_e32 v81, 16, v1611145; GFX10-NEXT:    v_cmp_u_f32_e64 s16, v31, v3111146; GFX10-NEXT:    v_and_b32_e32 v31, 0xffff0000, v1611147; GFX10-NEXT:    v_cndmask_b32_e64 v83, v83, v81, s1611148; GFX10-NEXT:    v_cmp_u_f32_e64 s16, v31, v3111149; GFX10-NEXT:    v_lshlrev_b32_e32 v31, 16, v8311150; GFX10-NEXT:    v_cndmask_b32_e64 v81, v81, v83, s1611151; GFX10-NEXT:    v_lshlrev_b32_e32 v84, 16, v8111152; GFX10-NEXT:    v_cmp_lt_f32_e64 s16, v31, v8411153; GFX10-NEXT:    v_and_b32_e32 v31, 0xffff0000, v1411154; GFX10-NEXT:    v_lshrrev_b32_e32 v84, 16, v3011155; GFX10-NEXT:    v_cmp_u_f32_e64 s17, v31, v3111156; GFX10-NEXT:    v_cndmask_b32_e64 v31, v85, v84, s1711157; GFX10-NEXT:    v_and_b32_e32 v85, 0xffff0000, v3011158; GFX10-NEXT:    v_cmp_u_f32_e64 s17, v85, v8511159; GFX10-NEXT:    v_lshlrev_b32_e32 v85, 16, v3111160; GFX10-NEXT:    v_cndmask_b32_e64 v84, v84, v31, s1711161; GFX10-NEXT:    v_lshlrev_b32_e32 v86, 16, v8411162; GFX10-NEXT:    v_cmp_lt_f32_e64 s17, v85, v8611163; GFX10-NEXT:    v_lshrrev_b32_e32 v86, 16, v1511164; GFX10-NEXT:    v_cndmask_b32_e64 v85, v84, v31, s1711165; GFX10-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v3111166; GFX10-NEXT:    v_cndmask_b32_e64 v31, v85, v31, s1711167; GFX10-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v8411168; GFX10-NEXT:    v_cndmask_b32_e64 v31, v31, v84, s1711169; GFX10-NEXT:    v_lshlrev_b32_e32 v84, 16, v8511170; GFX10-NEXT:    v_cmp_eq_f32_e64 s17, 0, v8411171; GFX10-NEXT:    v_cndmask_b32_e64 v84, v37, v32, s511172; GFX10-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v3211173; GFX10-NEXT:    v_cndmask_b32_e64 v31, v85, v31, s1711174; GFX10-NEXT:    v_lshlrev_b32_e32 v85, 16, v1511175; GFX10-NEXT:    v_cndmask_b32_e64 v32, v84, v32, s511176; GFX10-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v3711177; GFX10-NEXT:    v_cndmask_b32_e64 v32, v32, v37, s511178; GFX10-NEXT:    v_cndmask_b32_e64 v37, v36, v34, s411179; GFX10-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v3411180; GFX10-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v3911181; GFX10-NEXT:    v_cndmask_b32_e64 v34, v37, v34, s411182; GFX10-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v3611183; GFX10-NEXT:    v_cndmask_b32_e64 v34, v34, v36, s411184; GFX10-NEXT:    v_cndmask_b32_e32 v36, v35, v33, vcc_lo11185; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3311186; GFX10-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v3811187; GFX10-NEXT:    v_cndmask_b32_e32 v33, v36, v33, vcc_lo11188; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3511189; GFX10-NEXT:    v_cndmask_b32_e32 v33, v33, v35, vcc_lo11190; GFX10-NEXT:    v_lshlrev_b32_e32 v35, 16, v3611191; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3511192; GFX10-NEXT:    v_cndmask_b32_e64 v35, v48, v38, s611193; GFX10-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v4911194; GFX10-NEXT:    v_cndmask_b32_e32 v33, v36, v33, vcc_lo11195; GFX10-NEXT:    v_cndmask_b32_e64 v38, v35, v38, s411196; GFX10-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v4811197; GFX10-NEXT:    v_cndmask_b32_e64 v38, v38, v48, s411198; GFX10-NEXT:    v_lshlrev_b32_e32 v48, 16, v3511199; GFX10-NEXT:    v_cmp_eq_f32_e64 s4, 0, v4811200; GFX10-NEXT:    v_cndmask_b32_e64 v48, v50, v39, s811201; GFX10-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v6511202; GFX10-NEXT:    v_cndmask_b32_e64 v39, v48, v39, s511203; GFX10-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v5011204; GFX10-NEXT:    v_cndmask_b32_e64 v39, v39, v50, s511205; GFX10-NEXT:    v_lshlrev_b32_e32 v50, 16, v4811206; GFX10-NEXT:    v_cmp_eq_f32_e64 s5, 0, v5011207; GFX10-NEXT:    v_cndmask_b32_e64 v50, v52, v49, s911208; GFX10-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v6811209; GFX10-NEXT:    v_cndmask_b32_e64 v49, v50, v49, s611210; GFX10-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v5211211; GFX10-NEXT:    v_cndmask_b32_e64 v49, v49, v52, s611212; GFX10-NEXT:    v_lshlrev_b32_e32 v52, 16, v5011213; GFX10-NEXT:    v_cmp_eq_f32_e64 s6, 0, v5211214; GFX10-NEXT:    v_cndmask_b32_e64 v52, v53, v55, s711215; GFX10-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v5511216; GFX10-NEXT:    v_cndmask_b32_e64 v55, v52, v55, s711217; GFX10-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v5311218; GFX10-NEXT:    v_cndmask_b32_e64 v53, v55, v53, s711219; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v5211220; GFX10-NEXT:    v_cmp_eq_f32_e64 s7, 0, v5511221; GFX10-NEXT:    v_cndmask_b32_e64 v55, v64, v65, s1011222; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v6911223; GFX10-NEXT:    v_cndmask_b32_e64 v36, v52, v53, s711224; GFX10-NEXT:    v_cndmask_b32_e64 v65, v55, v65, s811225; GFX10-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v6411226; GFX10-NEXT:    v_cndmask_b32_e64 v64, v65, v64, s811227; GFX10-NEXT:    v_cndmask_b32_e64 v65, v66, v54, s1111228; GFX10-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v5411229; GFX10-NEXT:    v_cndmask_b32_e64 v54, v65, v54, s811230; GFX10-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v6611231; GFX10-NEXT:    v_cndmask_b32_e64 v54, v54, v66, s811232; GFX10-NEXT:    v_lshlrev_b32_e32 v66, 16, v6511233; GFX10-NEXT:    v_cmp_eq_f32_e64 s8, 0, v6611234; GFX10-NEXT:    v_cndmask_b32_e64 v66, v67, v68, s1211235; GFX10-NEXT:    v_cndmask_b32_e64 v68, v66, v68, s911236; GFX10-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v6711237; GFX10-NEXT:    v_cndmask_b32_e64 v67, v68, v67, s911238; GFX10-NEXT:    v_lshlrev_b32_e32 v68, 16, v6611239; GFX10-NEXT:    v_cmp_eq_f32_e64 s9, 0, v6811240; GFX10-NEXT:    v_cndmask_b32_e64 v68, v51, v69, s1311241; GFX10-NEXT:    v_cndmask_b32_e64 v69, v68, v69, s1011242; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v5111243; GFX10-NEXT:    v_cndmask_b32_e64 v51, v69, v51, s1011244; GFX10-NEXT:    v_cndmask_b32_e64 v69, v80, v70, s1411245; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v7011246; GFX10-NEXT:    v_cndmask_b32_e64 v70, v69, v70, s1011247; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v8011248; GFX10-NEXT:    v_cndmask_b32_e64 v70, v70, v80, s1011249; GFX10-NEXT:    v_cndmask_b32_e64 v80, v71, v82, s1511250; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v8211251; GFX10-NEXT:    v_cndmask_b32_e64 v82, v80, v82, s1011252; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v7111253; GFX10-NEXT:    v_cndmask_b32_e64 v71, v82, v71, s1011254; GFX10-NEXT:    v_cndmask_b32_e64 v82, v81, v83, s1611255; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v8311256; GFX10-NEXT:    v_lshlrev_b32_e32 v52, 16, v8211257; GFX10-NEXT:    v_cndmask_b32_e64 v83, v82, v83, s1011258; GFX10-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v8111259; GFX10-NEXT:    v_cndmask_b32_e64 v81, v83, v81, s1011260; GFX10-NEXT:    buffer_load_dword v83, off, s[0:3], s3211261; GFX10-NEXT:    v_cmp_u_f32_e64 s10, v85, v8511262; GFX10-NEXT:    v_lshlrev_b32_e32 v85, 16, v1411263; GFX10-NEXT:    v_cmp_u_f32_e64 s11, v85, v8511264; GFX10-NEXT:    v_cndmask_b32_e64 v85, v14, v30, s1111265; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v3011266; GFX10-NEXT:    v_cmp_u_f32_e64 s11, v14, v1411267; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v8411268; GFX10-NEXT:    v_cndmask_b32_e64 v87, v30, v85, s1111269; GFX10-NEXT:    v_cmp_eq_f32_e64 s12, 0, v1411270; GFX10-NEXT:    v_cndmask_b32_e64 v30, v35, v38, s411271; GFX10-NEXT:    v_cndmask_b32_e64 v35, v50, v49, s611272; GFX10-NEXT:    v_cndmask_b32_e64 v38, v65, v54, s811273; GFX10-NEXT:    v_lshlrev_b32_e32 v49, 16, v8011274; GFX10-NEXT:    v_cndmask_b32_e64 v14, v84, v32, s1211275; GFX10-NEXT:    v_lshlrev_b32_e32 v32, 16, v3711276; GFX10-NEXT:    v_and_b32_e32 v84, 0xffff0000, v1511277; GFX10-NEXT:    v_cmp_eq_f32_e64 s12, 0, v3211278; GFX10-NEXT:    v_cndmask_b32_e64 v32, v37, v34, s1211279; GFX10-NEXT:    v_lshlrev_b32_e32 v37, 16, v5511280; GFX10-NEXT:    v_cndmask_b32_e64 v34, v48, v39, s511281; GFX10-NEXT:    v_lshlrev_b32_e32 v39, 16, v6811282; GFX10-NEXT:    v_lshlrev_b32_e32 v48, 16, v6911283; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3711284; GFX10-NEXT:    v_cndmask_b32_e32 v37, v55, v64, vcc_lo11285; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v84, v8411286; GFX10-NEXT:    s_waitcnt vmcnt(0)11287; GFX10-NEXT:    v_lshrrev_b32_e32 v50, 16, v8311288; GFX10-NEXT:    v_and_b32_e32 v53, 0xffff0000, v8311289; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v8311290; GFX10-NEXT:    v_cndmask_b32_e64 v64, v15, v83, s1011291; GFX10-NEXT:    v_cndmask_b32_e64 v15, v66, v67, s911292; GFX10-NEXT:    v_cndmask_b32_e32 v54, v86, v50, vcc_lo11293; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v5311294; GFX10-NEXT:    v_lshlrev_b32_e32 v65, 16, v6411295; GFX10-NEXT:    v_cndmask_b32_e32 v53, v50, v54, vcc_lo11296; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5511297; GFX10-NEXT:    v_lshlrev_b32_e32 v50, 16, v5411298; GFX10-NEXT:    v_cndmask_b32_e32 v55, v83, v64, vcc_lo11299; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3911300; GFX10-NEXT:    v_lshlrev_b32_e32 v66, 16, v5511301; GFX10-NEXT:    v_cndmask_b32_e32 v39, v68, v51, vcc_lo11302; GFX10-NEXT:    v_lshlrev_b32_e32 v51, 16, v5311303; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4811304; GFX10-NEXT:    v_cndmask_b32_e32 v48, v69, v70, vcc_lo11305; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v50, v5111306; GFX10-NEXT:    v_cndmask_b32_e32 v51, v53, v54, vcc_lo11307; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v6611308; GFX10-NEXT:    v_cndmask_b32_e32 v65, v55, v64, vcc_lo11309; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4911310; GFX10-NEXT:    v_cndmask_b32_e32 v50, v80, v71, vcc_lo11311; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5411312; GFX10-NEXT:    v_cndmask_b32_e32 v49, v51, v54, vcc_lo11313; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6411314; GFX10-NEXT:    v_cndmask_b32_e32 v54, v65, v64, vcc_lo11315; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5311316; GFX10-NEXT:    v_lshlrev_b32_e32 v64, 16, v5111317; GFX10-NEXT:    v_cndmask_b32_e32 v49, v49, v53, vcc_lo11318; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5511319; GFX10-NEXT:    v_lshlrev_b32_e32 v53, 16, v6511320; GFX10-NEXT:    v_cndmask_b32_e32 v54, v54, v55, vcc_lo11321; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6411322; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v1311323; GFX10-NEXT:    v_lshlrev_b32_e32 v64, 16, v2911324; GFX10-NEXT:    v_cndmask_b32_e32 v49, v51, v49, vcc_lo11325; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5211326; GFX10-NEXT:    v_cndmask_b32_e32 v52, v82, v81, vcc_lo11327; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5311328; GFX10-NEXT:    v_lshlrev_b32_e32 v53, 16, v8711329; GFX10-NEXT:    v_cndmask_b32_e32 v51, v65, v54, vcc_lo11330; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v8511331; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5511332; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v1211333; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc_lo11334; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v54, v5311335; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v2811336; GFX10-NEXT:    v_lshlrev_b32_e32 v65, 16, v1311337; GFX10-NEXT:    v_cndmask_b32_e32 v53, v87, v85, vcc_lo11338; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v64, v6411339; GFX10-NEXT:    v_cndmask_b32_e32 v29, v29, v13, vcc_lo11340; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5511341; GFX10-NEXT:    v_lshlrev_b32_e32 v64, 16, v2911342; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo11343; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8511344; GFX10-NEXT:    v_lshlrev_b32_e32 v66, 16, v1211345; GFX10-NEXT:    v_cndmask_b32_e32 v55, v53, v85, vcc_lo11346; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v5411347; GFX10-NEXT:    v_cndmask_b32_e32 v54, v28, v12, vcc_lo11348; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8711349; GFX10-NEXT:    v_cndmask_b32_e32 v28, v55, v87, vcc_lo11350; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v6411351; GFX10-NEXT:    v_lshlrev_b32_e32 v64, 16, v5311352; GFX10-NEXT:    v_lshlrev_b32_e32 v65, 16, v5411353; GFX10-NEXT:    v_cndmask_b32_e32 v55, v29, v13, vcc_lo11354; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1311355; GFX10-NEXT:    v_cndmask_b32_e32 v13, v55, v13, vcc_lo11356; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6411357; GFX10-NEXT:    v_lshlrev_b32_e32 v64, 16, v5511358; GFX10-NEXT:    v_cndmask_b32_e32 v28, v53, v28, vcc_lo11359; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v66, v6511360; GFX10-NEXT:    v_lshlrev_b32_e32 v65, 16, v2711361; GFX10-NEXT:    v_cndmask_b32_e32 v53, v54, v12, vcc_lo11362; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2911363; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc_lo11364; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v1111365; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1211366; GFX10-NEXT:    v_cndmask_b32_e32 v12, v53, v12, vcc_lo11367; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2911368; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v5311369; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo11370; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5411371; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v54, vcc_lo11372; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6511373; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v1011374; GFX10-NEXT:    v_cndmask_b32_e32 v27, v27, v11, vcc_lo11375; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6411376; GFX10-NEXT:    v_cndmask_b32_e32 v13, v55, v13, vcc_lo11377; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2911378; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v2711379; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v2611380; GFX10-NEXT:    v_perm_b32 v13, v14, v13, 0x504010011381; GFX10-NEXT:    v_cndmask_b32_e32 v12, v53, v12, vcc_lo11382; GFX10-NEXT:    v_lshlrev_b32_e32 v53, 16, v1111383; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v5411384; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v911385; GFX10-NEXT:    v_perm_b32 v14, v31, v28, 0x504010011386; GFX10-NEXT:    v_perm_b32 v12, v32, v12, 0x504010011387; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc_lo11388; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v53, v2911389; GFX10-NEXT:    v_lshlrev_b32_e32 v53, 16, v2511390; GFX10-NEXT:    v_cndmask_b32_e32 v29, v27, v11, vcc_lo11391; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5511392; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v1011393; GFX10-NEXT:    v_cndmask_b32_e32 v26, v26, v10, vcc_lo11394; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v5411395; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v2611396; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc_lo11397; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1111398; GFX10-NEXT:    v_cndmask_b32_e32 v11, v29, v11, vcc_lo11399; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v5311400; GFX10-NEXT:    v_cndmask_b32_e32 v25, v25, v9, vcc_lo11401; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2711402; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo11403; GFX10-NEXT:    v_lshlrev_b32_e32 v27, 16, v2911404; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v55, v5411405; GFX10-NEXT:    v_lshlrev_b32_e32 v54, 16, v2511406; GFX10-NEXT:    v_lshlrev_b32_e32 v55, 16, v911407; GFX10-NEXT:    v_cndmask_b32_e32 v53, v26, v10, vcc_lo11408; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2711409; GFX10-NEXT:    v_cndmask_b32_e32 v11, v29, v11, vcc_lo11410; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1011411; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v5311412; GFX10-NEXT:    v_perm_b32 v11, v33, v11, 0x504010011413; GFX10-NEXT:    v_cndmask_b32_e32 v10, v53, v10, vcc_lo11414; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v55, v5411415; GFX10-NEXT:    v_cndmask_b32_e32 v27, v25, v9, vcc_lo11416; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2611417; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc_lo11418; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v911419; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v811420; GFX10-NEXT:    v_cndmask_b32_e32 v9, v27, v9, vcc_lo11421; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2911422; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v2311423; GFX10-NEXT:    v_cndmask_b32_e32 v10, v53, v10, vcc_lo11424; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2511425; GFX10-NEXT:    v_perm_b32 v10, v30, v10, 0x504010011426; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc_lo11427; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v711428; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v2611429; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v2411430; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo11431; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2511432; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v2711433; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc_lo11434; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v2611435; GFX10-NEXT:    v_lshlrev_b32_e32 v53, 16, v711436; GFX10-NEXT:    v_cndmask_b32_e32 v24, v24, v8, vcc_lo11437; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2911438; GFX10-NEXT:    v_lshlrev_b32_e32 v26, 16, v2411439; GFX10-NEXT:    v_cndmask_b32_e32 v23, v23, v7, vcc_lo11440; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2511441; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v611442; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v2311443; GFX10-NEXT:    v_cndmask_b32_e32 v9, v27, v9, vcc_lo11444; GFX10-NEXT:    v_lshlrev_b32_e32 v27, 16, v811445; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2511446; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v2211447; GFX10-NEXT:    v_perm_b32 v9, v34, v9, 0x504010011448; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo11449; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v27, v2611450; GFX10-NEXT:    v_cndmask_b32_e32 v26, v24, v8, vcc_lo11451; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v53, v2911452; GFX10-NEXT:    v_lshlrev_b32_e32 v29, 16, v611453; GFX10-NEXT:    v_cndmask_b32_e32 v27, v23, v7, vcc_lo11454; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2511455; GFX10-NEXT:    v_cndmask_b32_e32 v22, v22, v6, vcc_lo11456; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v811457; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v2211458; GFX10-NEXT:    v_cndmask_b32_e32 v8, v26, v8, vcc_lo11459; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v711460; GFX10-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo11461; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2411462; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo11463; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2311464; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v2611465; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc_lo11466; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v29, v2511467; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v2711468; GFX10-NEXT:    v_cndmask_b32_e32 v23, v22, v6, vcc_lo11469; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2411470; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v511471; GFX10-NEXT:    v_cndmask_b32_e32 v8, v26, v8, vcc_lo11472; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v611473; GFX10-NEXT:    v_perm_b32 v8, v35, v8, 0x504010011474; GFX10-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc_lo11475; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2511476; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v2111477; GFX10-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo11478; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2211479; GFX10-NEXT:    v_perm_b32 v7, v36, v7, 0x504010011480; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo11481; GFX10-NEXT:    v_lshlrev_b32_e32 v22, 16, v2311482; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v2411483; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v411484; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc_lo11485; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2211486; GFX10-NEXT:    v_lshlrev_b32_e32 v22, 16, v2011487; GFX10-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc_lo11488; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2511489; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v311490; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v511491; GFX10-NEXT:    v_perm_b32 v6, v37, v6, 0x504010011492; GFX10-NEXT:    v_cndmask_b32_e32 v21, v21, v5, vcc_lo11493; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v2411494; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v2111495; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo11496; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v2211497; GFX10-NEXT:    v_lshlrev_b32_e32 v22, 16, v1911498; GFX10-NEXT:    v_cndmask_b32_e32 v20, v20, v4, vcc_lo11499; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v2311500; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc_lo11501; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2411502; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v2011503; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v411504; GFX10-NEXT:    v_cndmask_b32_e32 v23, v21, v5, vcc_lo11505; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v2211506; GFX10-NEXT:    v_cndmask_b32_e32 v19, v19, v3, vcc_lo11507; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v511508; GFX10-NEXT:    v_cndmask_b32_e32 v5, v23, v5, vcc_lo11509; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2411510; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v1911511; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v311512; GFX10-NEXT:    v_cndmask_b32_e32 v22, v20, v4, vcc_lo11513; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2111514; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc_lo11515; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v411516; GFX10-NEXT:    v_lshlrev_b32_e32 v21, 16, v2311517; GFX10-NEXT:    v_cndmask_b32_e32 v4, v22, v4, vcc_lo11518; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2411519; GFX10-NEXT:    v_cndmask_b32_e32 v24, v19, v3, vcc_lo11520; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2111521; GFX10-NEXT:    v_lshlrev_b32_e32 v21, 16, v2211522; GFX10-NEXT:    v_cndmask_b32_e32 v5, v23, v5, vcc_lo11523; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2011524; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v2411525; GFX10-NEXT:    v_perm_b32 v5, v38, v5, 0x504010011526; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo11527; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v311528; GFX10-NEXT:    v_lshlrev_b32_e32 v20, 16, v211529; GFX10-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo11530; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1911531; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc_lo11532; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2011533; GFX10-NEXT:    v_lshlrev_b32_e32 v19, 16, v1811534; GFX10-NEXT:    v_lshlrev_b32_e32 v20, 16, v111535; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc_lo11536; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2311537; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v011538; GFX10-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo11539; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v1911540; GFX10-NEXT:    v_lshlrev_b32_e32 v19, 16, v1711541; GFX10-NEXT:    v_perm_b32 v3, v39, v3, 0x504010011542; GFX10-NEXT:    v_cndmask_b32_e32 v18, v18, v2, vcc_lo11543; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2011544; GFX10-NEXT:    v_lshlrev_b32_e32 v20, 16, v1611545; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo11546; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v2311547; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v211548; GFX10-NEXT:    v_lshlrev_b32_e32 v24, 16, v111549; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo11550; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v1911551; GFX10-NEXT:    v_lshlrev_b32_e32 v19, 16, v1811552; GFX10-NEXT:    v_lshlrev_b32_e32 v25, 16, v011553; GFX10-NEXT:    v_cndmask_b32_e32 v17, v17, v1, vcc_lo11554; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2011555; GFX10-NEXT:    v_lshlrev_b32_e32 v20, 16, v1711556; GFX10-NEXT:    v_cndmask_b32_e32 v16, v16, v0, vcc_lo11557; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v1911558; GFX10-NEXT:    v_lshlrev_b32_e32 v23, 16, v1611559; GFX10-NEXT:    v_cndmask_b32_e32 v19, v18, v2, vcc_lo11560; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v24, v2011561; GFX10-NEXT:    v_cndmask_b32_e32 v20, v17, v1, vcc_lo11562; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v211563; GFX10-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo11564; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2311565; GFX10-NEXT:    v_cndmask_b32_e32 v23, v16, v0, vcc_lo11566; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v111567; GFX10-NEXT:    v_cndmask_b32_e32 v1, v20, v1, vcc_lo11568; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1811569; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc_lo11570; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v011571; GFX10-NEXT:    v_lshlrev_b32_e32 v18, 16, v2311572; GFX10-NEXT:    v_cndmask_b32_e32 v0, v23, v0, vcc_lo11573; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1711574; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo11575; GFX10-NEXT:    v_lshlrev_b32_e32 v17, 16, v2011576; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1611577; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo11578; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1711579; GFX10-NEXT:    v_lshlrev_b32_e32 v16, 16, v1911580; GFX10-NEXT:    v_cndmask_b32_e32 v1, v20, v1, vcc_lo11581; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1811582; GFX10-NEXT:    v_perm_b32 v1, v50, v1, 0x504010011583; GFX10-NEXT:    v_cndmask_b32_e32 v0, v23, v0, vcc_lo11584; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1611585; GFX10-NEXT:    v_perm_b32 v0, v52, v0, 0x504010011586; GFX10-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo11587; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2111588; GFX10-NEXT:    v_perm_b32 v2, v48, v2, 0x504010011589; GFX10-NEXT:    v_cndmask_b32_e32 v4, v22, v4, vcc_lo11590; GFX10-NEXT:    v_perm_b32 v4, v15, v4, 0x504010011591; GFX10-NEXT:    v_perm_b32 v15, v49, v51, 0x504010011592; GFX10-NEXT:    s_setpc_b64 s[30:31]11593;11594; GFX11-TRUE16-LABEL: v_minimumnum_v32bf16:11595; GFX11-TRUE16:       ; %bb.0:11596; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11597; GFX11-TRUE16-NEXT:    scratch_load_b32 v68, off, s3211598; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v1511599; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.l, 011600; GFX11-TRUE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v1411601; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v3011602; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v2911603; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v3111604; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v36.l11605; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v36.l11606; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v33, v3311607; GFX11-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v1311608; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v34, v3411609; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v36.l11610; GFX11-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v1211611; GFX11-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v2811612; GFX11-TRUE16-NEXT:    v_and_b32_e32 v48, 0xffff0000, v1111613; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v2711614; GFX11-TRUE16-NEXT:    v_and_b32_e32 v50, 0xffff0000, v2611615; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff0000, v2511616; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v39, v3911617; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v36.l11618; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v49, v4911619; GFX11-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v1011620; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v50, v5011621; GFX11-TRUE16-NEXT:    v_and_b32_e32 v50, 0xffff0000, v911622; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v51, v5111623; GFX11-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff0000, v811624; GFX11-TRUE16-NEXT:    v_and_b32_e32 v52, 0xffff0000, v2411625; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v2311626; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v2211627; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff0000, v2111628; GFX11-TRUE16-NEXT:    v_and_b32_e32 v64, 0xffff0000, v2011629; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v52, v5211630; GFX11-TRUE16-NEXT:    v_and_b32_e32 v52, 0xffff0000, v711631; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v53, v5311632; GFX11-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v611633; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v54, v5411634; GFX11-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v511635; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v55, v5511636; GFX11-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff0000, v411637; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v64, v6411638; GFX11-TRUE16-NEXT:    v_and_b32_e32 v64, 0xffff0000, v311639; GFX11-TRUE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v1911640; GFX11-TRUE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v1811641; GFX11-TRUE16-NEXT:    v_and_b32_e32 v67, 0xffff0000, v1711642; GFX11-TRUE16-NEXT:    v_and_b32_e32 v81, 0xffff0000, v1611643; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v82.l, v36.l11644; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v65, v6511645; GFX11-TRUE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v211646; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v66, v6611647; GFX11-TRUE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v111648; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v67, v6711649; GFX11-TRUE16-NEXT:    v_and_b32_e32 v67, 0xffff0000, v011650; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s15, v81, v8111651; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1511652; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v83, 16, v3011653; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v84, 16, v211654; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v86, 16, v011655; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v1711656; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v87, 16, v1611657; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s17, v83, v8311658; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v83.l, v36.l11659; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s42, v86, v8611660; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v96.l, v36.l11661; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)11662; GFX11-TRUE16-NEXT:    v_cndmask_b16 v96.h, v0.l, v16.l, s4211663; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s43, 0x8000, v96.h11664; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)11665; GFX11-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v6811666; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v15.h, v68.h, vcc_lo11667; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11668; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v3111669; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h11670; GFX11-TRUE16-NEXT:    v_cndmask_b16 v35.h, v68.h, v36.h, vcc_lo11671; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)11672; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v36, v3511673; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s42, 0x8000, v35.h11674; GFX11-TRUE16-NEXT:    v_cndmask_b16 v31.l, v35.h, v36.h, vcc_lo11675; GFX11-TRUE16-NEXT:    v_cndmask_b16 v31.h, v31.l, v36.h, s011676; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v31.l11677; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v32, v3211678; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11679; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3611680; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v14.h, v30.h, s011681; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11682; GFX11-TRUE16-NEXT:    v_cndmask_b16 v37.h, v30.h, v36.h, s111683; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v36.h11684; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v36, v3711685; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s44, 0x8000, v37.h11686; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)11687; GFX11-TRUE16-NEXT:    v_cndmask_b16 v32.l, v37.h, v36.h, s011688; GFX11-TRUE16-NEXT:    v_cndmask_b16 v32.h, v32.l, v36.h, s111689; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v32.l11690; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v33, v3311691; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11692; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v3611693; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v13.h, v29.h, s111694; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11695; GFX11-TRUE16-NEXT:    v_cndmask_b16 v38.h, v29.h, v36.h, s211696; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v36.h11697; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v36, v3811698; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11699; GFX11-TRUE16-NEXT:    v_cndmask_b16 v33.l, v38.h, v36.h, s111700; GFX11-TRUE16-NEXT:    v_cndmask_b16 v33.h, v33.l, v36.h, s211701; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v33.l11702; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v34, v3411703; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11704; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v3611705; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v12.h, v28.h, s211706; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11707; GFX11-TRUE16-NEXT:    v_cndmask_b16 v39.h, v28.h, v36.h, s311708; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v36.h11709; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v36, v3911710; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11711; GFX11-TRUE16-NEXT:    v_cndmask_b16 v34.l, v39.h, v36.h, s211712; GFX11-TRUE16-NEXT:    v_cndmask_b16 v34.h, v34.l, v36.h, s311713; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v34.l11714; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v48, v4811715; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v36.l11716; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11717; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v3611718; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v11.h, v27.h, s311719; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11720; GFX11-TRUE16-NEXT:    v_cndmask_b16 v48.h, v27.h, v36.h, s411721; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v36.h11722; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s3, v36, v4811723; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11724; GFX11-TRUE16-NEXT:    v_cndmask_b16 v35.l, v48.h, v36.h, s311725; GFX11-TRUE16-NEXT:    v_cndmask_b16 v37.l, v35.l, v36.h, s411726; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v35.l11727; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v49, v4911728; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v36.l11729; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11730; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v3611731; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v10.h, v26.h, s411732; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11733; GFX11-TRUE16-NEXT:    v_cndmask_b16 v49.h, v26.h, v36.h, s511734; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v36.h11735; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v36, v4911736; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11737; GFX11-TRUE16-NEXT:    v_cndmask_b16 v38.l, v49.h, v36.h, s411738; GFX11-TRUE16-NEXT:    v_cndmask_b16 v39.l, v38.l, v36.h, s511739; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v38.l11740; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v50, v5011741; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v36.l11742; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11743; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v3611744; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v9.h, v25.h, s511745; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11746; GFX11-TRUE16-NEXT:    v_cndmask_b16 v50.h, v25.h, v36.h, s611747; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v36.h11748; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s5, v36, v5011749; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11750; GFX11-TRUE16-NEXT:    v_cndmask_b16 v48.l, v50.h, v36.h, s511751; GFX11-TRUE16-NEXT:    v_cndmask_b16 v49.l, v48.l, v36.h, s611752; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v48.l11753; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v51, v5111754; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v36.l11755; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11756; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s5, 0, v3611757; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v8.h, v24.h, s611758; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11759; GFX11-TRUE16-NEXT:    v_cndmask_b16 v51.h, v24.h, v36.h, s711760; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v36.h11761; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s6, v36, v5111762; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11763; GFX11-TRUE16-NEXT:    v_cndmask_b16 v50.l, v51.h, v36.h, s611764; GFX11-TRUE16-NEXT:    v_cndmask_b16 v51.l, v50.l, v36.h, s711765; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v50.l11766; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v52, v5211767; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v36.l11768; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11769; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s6, 0, v3611770; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v7.h, v23.h, s711771; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11772; GFX11-TRUE16-NEXT:    v_cndmask_b16 v52.h, v23.h, v36.h, s811773; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v36.h11774; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s7, v36, v5211775; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11776; GFX11-TRUE16-NEXT:    v_cndmask_b16 v52.l, v52.h, v36.h, s711777; GFX11-TRUE16-NEXT:    v_cndmask_b16 v69.l, v52.l, v36.h, s811778; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v52.l11779; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v53, v5311780; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v36.l11781; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11782; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s7, 0, v3611783; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v6.h, v22.h, s811784; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11785; GFX11-TRUE16-NEXT:    v_cndmask_b16 v53.h, v22.h, v36.h, s911786; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v36.h11787; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s8, v36, v5311788; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11789; GFX11-TRUE16-NEXT:    v_cndmask_b16 v53.l, v53.h, v36.h, s811790; GFX11-TRUE16-NEXT:    v_cndmask_b16 v69.h, v53.l, v36.h, s911791; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v53.l11792; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v54, v5411793; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v36.l11794; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11795; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s8, 0, v3611796; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v5.h, v21.h, s911797; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11798; GFX11-TRUE16-NEXT:    v_cndmask_b16 v54.h, v21.h, v36.h, s1011799; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v36.h11800; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s9, v36, v5411801; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11802; GFX11-TRUE16-NEXT:    v_cndmask_b16 v54.l, v54.h, v36.h, s911803; GFX11-TRUE16-NEXT:    v_cndmask_b16 v70.l, v54.l, v36.h, s1011804; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v54.l11805; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v55, v5511806; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v36.l11807; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11808; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s9, 0, v3611809; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v4.h, v20.h, s1011810; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11811; GFX11-TRUE16-NEXT:    v_cndmask_b16 v55.h, v20.h, v36.h, s1111812; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s11, 0x8000, v36.h11813; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s10, v36, v5511814; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11815; GFX11-TRUE16-NEXT:    v_cndmask_b16 v55.l, v55.h, v36.h, s1011816; GFX11-TRUE16-NEXT:    v_cndmask_b16 v70.h, v55.l, v36.h, s1111817; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v55.l11818; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v64, v6411819; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v36.l11820; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11821; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s10, 0, v3611822; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v3.h, v19.h, s1111823; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11824; GFX11-TRUE16-NEXT:    v_cndmask_b16 v64.h, v19.h, v36.h, s1211825; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s12, 0x8000, v36.h11826; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s11, v36, v6411827; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11828; GFX11-TRUE16-NEXT:    v_cndmask_b16 v64.l, v64.h, v36.h, s1111829; GFX11-TRUE16-NEXT:    v_cndmask_b16 v71.l, v64.l, v36.h, s1211830; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v64.l11831; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v65, v6511832; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v36.l11833; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11834; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s11, 0, v3611835; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v2.h, v18.h, s1211836; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11837; GFX11-TRUE16-NEXT:    v_cndmask_b16 v65.h, v18.h, v36.h, s1311838; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v36.h11839; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s12, v36, v6511840; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11841; GFX11-TRUE16-NEXT:    v_cndmask_b16 v65.l, v65.h, v36.h, s1211842; GFX11-TRUE16-NEXT:    v_cndmask_b16 v71.h, v65.l, v36.h, s1311843; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v65.l11844; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v66, v6611845; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v36.l11846; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11847; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s12, 0, v3611848; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v1.h, v17.h, s1311849; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11850; GFX11-TRUE16-NEXT:    v_cndmask_b16 v66.h, v17.h, v36.h, s1411851; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s14, 0x8000, v36.h11852; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s13, v36, v6611853; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)11854; GFX11-TRUE16-NEXT:    v_cndmask_b16 v66.l, v66.h, v36.h, s1311855; GFX11-TRUE16-NEXT:    v_cndmask_b16 v80.l, v66.l, v36.h, s1411856; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v66.l11857; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v67, v6711858; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v36.l11859; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11860; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s13, 0, v3611861; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v0.h, v16.h, s1411862; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)11863; GFX11-TRUE16-NEXT:    v_cndmask_b16 v67.h, v16.h, v36.h, s1511864; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s15, v81, v8111865; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v36.h11866; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v6811867; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s14, v36, v6711868; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)11869; GFX11-TRUE16-NEXT:    v_cndmask_b16 v82.h, v15.l, v68.l, s1511870; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s15, v81, v8111871; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1411872; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)11873; GFX11-TRUE16-NEXT:    v_cndmask_b16 v67.l, v67.h, v36.h, s1411874; GFX11-TRUE16-NEXT:    v_cndmask_b16 v15.l, v67.l, v36.h, s1611875; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v67.l11876; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v82.h11877; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)11878; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s14, 0, v3611879; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v68.l, v82.h, s1511880; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s15, v82, v3611881; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)11882; GFX11-TRUE16-NEXT:    v_cndmask_b16 v68.l, v36.h, v82.h, s1511883; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s15, 0x8000, v36.h11884; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.h, v68.l, v82.h, s1611885; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s16, v81, v8111886; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1311887; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2911888; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)11889; GFX11-TRUE16-NEXT:    v_cndmask_b16 v30.h, v14.h, v36.h, s1511890; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v68.l11891; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.h, v14.l, v30.l, s1611892; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v36.l11893; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s18, v82, v8211894; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2811895; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s15, 0, v3611896; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v30.l, v14.h, s1711897; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v14.h11898; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)11899; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s19, v82, v8211900; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2711901; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s16, v14, v3611902; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)11903; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s20, v82, v8211904; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.l, v36.h, v14.h, s1611905; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v36.h11906; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2611907; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)11908; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.h, v14.l, v14.h, s1711909; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s17, v81, v8111910; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1211911; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s21, v82, v8211912; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2511913; GFX11-TRUE16-NEXT:    v_cndmask_b16 v29.h, v13.h, v36.h, s1611914; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v14.l11915; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.h, v13.l, v29.l, s1711916; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v36.l11917; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s22, v82, v8211918; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2411919; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s16, 0, v3611920; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v29.l, v13.h, s1811921; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s18, 0x8000, v13.h11922; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)11923; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s23, v82, v8211924; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2311925; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s17, v13, v3611926; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.l, v14.l, v29.h, s1611927; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11928; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s24, v82, v8211929; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.l, v36.h, v13.h, s1711930; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v36.h11931; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2211932; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)11933; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v13.l, v13.h, s1811934; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s18, v81, v8111935; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1111936; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s25, v82, v8211937; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2111938; GFX11-TRUE16-NEXT:    v_cndmask_b16 v28.h, v12.h, v36.h, s1711939; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v13.l11940; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v12.l, v28.l, s1811941; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v36.l11942; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s26, v82, v8211943; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2011944; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s17, 0, v3611945; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v28.l, v12.h, s1911946; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s19, 0x8000, v12.h11947; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)11948; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s27, v82, v8211949; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v1911950; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s18, v12, v3611951; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.l, v13.l, v28.h, s1711952; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)11953; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s28, v82, v8211954; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.l, v36.h, v12.h, s1811955; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s18, 0x8000, v36.h11956; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v82.l, v36.l11957; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)11958; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.h, v12.l, v12.h, s1911959; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s19, v81, v8111960; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1011961; GFX11-TRUE16-NEXT:    v_cndmask_b16 v27.h, v11.h, v36.h, s1811962; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v12.l11963; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11964; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.h, v11.l, v27.l, s1911965; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l11966; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s18, 0, v3611967; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11968; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v27.l, v11.h, s2011969; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s20, 0x8000, v11.h11970; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.l, v12.l, v27.h, s1811971; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11972; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s19, v11, v3611973; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.l, v36.h, v11.h, s1911974; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s19, 0x8000, v36.h11975; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11976; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.h, v11.l, v11.h, s2011977; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s20, v81, v8111978; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v911979; GFX11-TRUE16-NEXT:    v_cndmask_b16 v26.h, v10.h, v36.h, s1911980; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v11.l11981; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)11982; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.h, v10.l, v26.l, s2011983; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v36.l11984; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s19, 0, v3611985; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)11986; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v26.l, v10.h, s2111987; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s21, 0x8000, v10.h11988; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.l, v11.l, v26.h, s1911989; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)11990; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s20, v10, v3611991; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.l, v36.h, v10.h, s2011992; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s20, 0x8000, v36.h11993; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)11994; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v10.l, v10.h, s2111995; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s21, v81, v8111996; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v811997; GFX11-TRUE16-NEXT:    v_cndmask_b16 v25.h, v9.h, v36.h, s2011998; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v10.l11999; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12000; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v9.l, v25.l, s2112001; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v36.l12002; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s20, 0, v3612003; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12004; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v25.l, v9.h, s2212005; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s22, 0x8000, v9.h12006; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.l, v10.l, v25.h, s2012007; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12008; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s21, v9, v3612009; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.l, v36.h, v9.h, s2112010; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s21, 0x8000, v36.h12011; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12012; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v9.l, v9.h, s2212013; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s22, v81, v8112014; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v712015; GFX11-TRUE16-NEXT:    v_cndmask_b16 v24.h, v8.h, v36.h, s2112016; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v9.l12017; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12018; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v8.l, v24.l, s2212019; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v36.l12020; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s21, 0, v3612021; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12022; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v24.l, v8.h, s2312023; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s23, 0x8000, v8.h12024; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.l, v9.l, v24.h, s2112025; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12026; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s22, v8, v3612027; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.l, v36.h, v8.h, s2212028; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s22, 0x8000, v36.h12029; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12030; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v8.l, v8.h, s2312031; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s23, v81, v8112032; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v612033; GFX11-TRUE16-NEXT:    v_cndmask_b16 v23.h, v7.h, v36.h, s2212034; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v8.l12035; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12036; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v7.l, v23.l, s2312037; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v36.l12038; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s22, 0, v3612039; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12040; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v23.l, v7.h, s2412041; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s24, 0x8000, v7.h12042; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.l, v8.l, v23.h, s2212043; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12044; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s23, v7, v3612045; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v36.h, v7.h, s2312046; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s23, 0x8000, v36.h12047; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12048; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v7.l, v7.h, s2412049; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s24, v81, v8112050; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v512051; GFX11-TRUE16-NEXT:    v_cndmask_b16 v22.h, v6.h, v36.h, s2312052; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v7.l12053; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12054; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v6.l, v22.l, s2412055; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v36.l12056; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s23, 0, v3612057; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12058; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v22.l, v6.h, s2512059; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s25, 0x8000, v6.h12060; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v7.l, v22.h, s2312061; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12062; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s24, v6, v3612063; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.l, v36.h, v6.h, s2412064; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s24, 0x8000, v36.h12065; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12066; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v6.l, v6.h, s2512067; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s25, v81, v8112068; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v412069; GFX11-TRUE16-NEXT:    v_cndmask_b16 v21.h, v5.h, v36.h, s2412070; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v6.l12071; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12072; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v5.l, v21.l, s2512073; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v36.l12074; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s24, 0, v3612075; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12076; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v21.l, v5.h, s2612077; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s26, 0x8000, v5.h12078; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.l, v6.l, v21.h, s2412079; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12080; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s25, v5, v3612081; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v36.h, v5.h, s2512082; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s25, 0x8000, v36.h12083; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12084; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v5.l, v5.h, s2612085; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s26, v81, v8112086; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v312087; GFX11-TRUE16-NEXT:    v_cndmask_b16 v20.h, v4.h, v36.h, s2512088; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v5.l12089; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)12090; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v20.l, s2612091; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v36.l12092; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s25, 0, v3612093; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12094; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v20.l, v4.h, s2712095; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s27, 0x8000, v4.h12096; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v5.l, v20.h, s2512097; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)12098; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s26, v4, v3612099; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v36.h, v4.h, s2612100; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s26, 0x8000, v36.h12101; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12102; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v4.l, v4.h, s2712103; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s27, v81, v8112104; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1812105; GFX11-TRUE16-NEXT:    v_cndmask_b16 v18.h, v3.h, v36.h, s2612106; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v4.l12107; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)12108; GFX11-TRUE16-NEXT:    v_cndmask_b16 v83.h, v3.l, v19.l, s2712109; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v112110; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s29, v81, v8112111; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s26, 0, v3612112; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)12113; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v19.l, v83.h, s2812114; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s28, v84, v8412115; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s40, v3, v312116; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s41, 0x8000, v83.h12117; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v36.l12118; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s27, v83, v3612119; GFX11-TRUE16-NEXT:    v_cndmask_b16 v82.h, v2.l, v18.l, s2812120; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s28, 0x8000, v36.h12121; GFX11-TRUE16-NEXT:    v_cndmask_b16 v19.h, v1.l, v17.l, s4012122; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v32.h, v37.h, s4412123; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v36.h, v83.h, s2712124; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s40, 0x8000, v82.h12125; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s27, v85, v8512126; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.l, v18.h, s2612127; GFX11-TRUE16-NEXT:    v_cndmask_b16 v14.h, v32.l, v1.l, s012128; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.l, v83.h, s4112129; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s41, v87, v8712130; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)12131; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.h, v36.h, s2812132; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v3.l12133; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v31.h, v35.h, s4212134; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s42, 0x8000, v39.h12135; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s28, 0x8000, v19.h12136; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s45, 0, v3612137; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v18.l, v82.h, s2912138; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s29, 0x8000, v38.h12139; GFX11-TRUE16-NEXT:    v_cndmask_b16 v15.h, v31.l, v0.h, vcc_lo12140; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v34.h, v39.h, s4212141; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48.h12142; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s44, v82, v3612143; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v33.h, v38.h, s2912144; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h12145; GFX11-TRUE16-NEXT:    v_cndmask_b16 v12.h, v34.l, v1.h, s212146; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v37.l, v48.h, vcc_lo12147; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v36.h, v82.h, s4412148; GFX11-TRUE16-NEXT:    v_cndmask_b16 v13.h, v33.l, v0.h, s112149; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49.h12150; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v50.h12151; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.h, v35.l, v1.h, s312152; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v82.h, s4012153; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v51.h12154; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v54.h12155; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v49.l, v50.h, s112156; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, v0.l, s4512157; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v36.h, s012158; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v1.l12159; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v39.l, v49.h, vcc_lo12160; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v52.h12161; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v51.l, v51.h, s212162; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v53.h12163; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3612164; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v17.l, v19.h, s2712165; GFX11-TRUE16-NEXT:    v_cndmask_b16 v10.h, v38.l, v0.h, s412166; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v69.l, v52.h, s012167; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v55.h12168; GFX11-TRUE16-NEXT:    v_cndmask_b16 v9.h, v48.l, v1.h, s512169; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v19, v3612170; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h12171; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v69.h, v53.h, s212172; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v70.h, v55.h, s412173; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v66.h12174; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.h, v36.h, v19.h, s112175; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v65.h12176; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v50.l, v2.h, s612177; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v70.l, v54.h, s312178; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v52.l, v0.h, s712179; GFX11-TRUE16-NEXT:    v_cndmask_b16 v17.l, v16.h, v19.h, s2812180; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v53.l, v1.h, s812181; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v71.h, v65.h, s112182; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v54.l, v2.h, s912183; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v67.h12184; GFX11-TRUE16-NEXT:    v_cndmask_b16 v17.l, v17.l, v36.h, s012185; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v16.h12186; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v64.h12187; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v65.l, v1.h, s1212188; GFX11-TRUE16-NEXT:    v_cndmask_b16 v15.l, v15.l, v67.h, s312189; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v55.l, v3.h, s1012190; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v3612191; GFX11-TRUE16-NEXT:    v_cndmask_b16 v36.h, v16.l, v96.h, s4112192; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v71.l, v64.h, s012193; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.l, v80.l, v66.h, s212194; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v2.l, vcc_lo12195; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v16.h, v17.l, s412196; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v96, v3612197; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v64.l, v0.h, s1112198; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v66.l, v16.l, s1312199; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v67.l, v15.l, s1412200; GFX11-TRUE16-NEXT:    v_cndmask_b16 v15.l, v68.l, v30.h, s1512201; GFX11-TRUE16-NEXT:    v_cndmask_b16 v16.l, v36.h, v96.h, s012202; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h12203; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)12204; GFX11-TRUE16-NEXT:    v_cndmask_b16 v17.h, v16.l, v96.h, s4312205; GFX11-TRUE16-NEXT:    v_cndmask_b16 v17.h, v17.h, v36.h, s012206; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v16.l12207; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12208; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v3612209; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v16.l, v17.h, s012210; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]12211;12212; GFX11-FAKE16-LABEL: v_minimumnum_v32bf16:12213; GFX11-FAKE16:       ; %bb.0:12214; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12215; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v2512216; GFX11-FAKE16-NEXT:    v_and_b32_e32 v50, 0xffff0000, v1212217; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 16, v2812218; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v1212219; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v2912220; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1312221; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e64 s1, v50, v5012222; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3012223; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 16, v1412224; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v2412225; GFX11-FAKE16-NEXT:    v_and_b32_e32 v70, 0xffff0000, v912226; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v52, v52, v51, s112227; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v1312228; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 16, v912229; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 16, v2112230; GFX11-FAKE16-NEXT:    v_and_b32_e32 v82, 0xffff0000, v812231; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v812232; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e64 s0, v38, v3812233; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v2312234; GFX11-FAKE16-NEXT:    v_and_b32_e32 v86, 0xffff0000, v712235; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v712236; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 16, v2212237; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v48, v48, v39, s012238; GFX11-FAKE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v1412239; GFX11-FAKE16-NEXT:    v_and_b32_e32 v98, 0xffff0000, v612240; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v612241; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v2012242; GFX11-FAKE16-NEXT:    v_and_b32_e32 v102, 0xffff0000, v512243; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v3412244; GFX11-FAKE16-NEXT:    v_and_b32_e32 v37, 0xffff0000, v3012245; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 16, v512246; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 16, v1912247; GFX11-FAKE16-NEXT:    v_and_b32_e32 v114, 0xffff0000, v412248; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v36, v35, vcc_lo12249; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v7012250; GFX11-FAKE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v2912251; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 16, v412252; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v1812253; GFX11-FAKE16-NEXT:    v_and_b32_e32 v118, 0xffff0000, v312254; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v80, v71, vcc_lo12255; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v8212256; GFX11-FAKE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v2812257; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v312258; GFX11-FAKE16-NEXT:    v_and_b32_e32 v130, 0xffff0000, v212259; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 16, v212260; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v84, v83, vcc_lo12261; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v8612262; GFX11-FAKE16-NEXT:    v_and_b32_e32 v69, 0xffff0000, v2612263; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 16, v1712264; GFX11-FAKE16-NEXT:    v_and_b32_e32 v134, 0xffff0000, v112265; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v2712266; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v96, v87, vcc_lo12267; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v9812268; GFX11-FAKE16-NEXT:    v_and_b32_e32 v81, 0xffff0000, v2512269; GFX11-FAKE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v1112270; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v112271; GFX11-FAKE16-NEXT:    v_and_b32_e32 v146, 0xffff0000, v012272; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v100, v99, vcc_lo12273; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v102, v10212274; GFX11-FAKE16-NEXT:    v_and_b32_e32 v85, 0xffff0000, v2412275; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 16, v1612276; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v012277; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e64 s2, v54, v5412278; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v112, v103, vcc_lo12279; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v114, v11412280; GFX11-FAKE16-NEXT:    v_and_b32_e32 v101, 0xffff0000, v2212281; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v1412282; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 16, v1112283; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 16, v2612284; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v96, v116, v115, vcc_lo12285; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v118, v11812286; GFX11-FAKE16-NEXT:    v_and_b32_e32 v113, 0xffff0000, v2112287; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v64, v64, v55, s212288; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v1012289; GFX11-FAKE16-NEXT:    scratch_load_b32 v31, off, s3212290; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v98, v128, v119, vcc_lo12291; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v130, v13012292; GFX11-FAKE16-NEXT:    v_and_b32_e32 v117, 0xffff0000, v2012293; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v1512294; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v100, v132, v131, vcc_lo12295; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v134, v13412296; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v102, v144, v135 :: v_dual_and_b32 v133, 0xffff0000, v1812297; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v146, v14612298; GFX11-FAKE16-NEXT:    v_and_b32_e32 v145, 0xffff0000, v1712299; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v112, 16, v9612300; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v34, v147, vcc_lo12301; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v5412302; GFX11-FAKE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v2712303; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v54, v14, v30 :: v_dual_and_b32 v97, 0xffff0000, v2312304; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v3712305; GFX11-FAKE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v1512306; GFX11-FAKE16-NEXT:    v_and_b32_e32 v129, 0xffff0000, v1912307; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo12308; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v4912309; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo12310; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v5312311; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo12312; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6512313; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v116, 16, v10012314; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)12315; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v55, v55, v64 :: v_dual_lshlrev_b32 v130, 16, v5112316; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v6912317; GFX11-FAKE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v1012318; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v128, 16, v3412319; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e64 s3, v66, v6612320; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12321; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v68, v68, v67, s312322; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v67, v68, vcc_lo12323; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v8112324; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v6812325; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v8012326; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)12327; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6712328; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v8512329; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v83, v83, v80, vcc_lo12330; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v97, v9712331; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v66, 16, v3012332; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v97, 16, v8412333; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)12334; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v8312335; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v101, v10112336; GFX11-FAKE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v1612337; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v99, v99, v84, vcc_lo12338; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v113, v11312339; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9912340; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v117, v11712341; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v3612342; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v113, v115, v96, vcc_lo12343; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v129, v12912344; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v8212345; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)12346; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v115, v119, v98 :: v_dual_lshlrev_b32 v146, 16, v11312347; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v133, v13312348; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v4812349; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v117, v131, v100, vcc_lo12350; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v145, v14512351; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v101, 16, v8612352; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v119, v135, v102, vcc_lo12353; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v3812354; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v38, v147, v34 :: v_dual_lshlrev_b32 v49, 16, v5212355; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v6612356; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)12357; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e64 s0, v49, v13012358; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v66, v30, v54 :: v_dual_lshlrev_b32 v53, 16, v6412359; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v3512360; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v3012361; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v69, 16, v7012362; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v11712363; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v130, v35, v36 :: v_dual_lshlrev_b32 v129, 16, v3912364; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)12365; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v37, v12912366; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v129, v51, v52, s012367; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v37, v39, v48 :: v_dual_lshlrev_b32 v118, 16, v10212368; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v131, 16, v5512369; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v53, v13112370; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v50, 16, v1512371; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v133, 16, v7112372; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v13212373; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v65, v67, v68, vcc_lo12374; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12375; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v69, v13312376; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v135, 16, v8712377; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6512378; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v81, v13412379; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v81, v83, v80, vcc_lo12380; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)12381; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v85, v13512382; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v145, 16, v10312383; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v85, v87, v82, vcc_lo12384; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v97, v14412385; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v9812386; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v101, v14512387; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v147, 16, v11512388; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)12389; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9712390; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v112, v14612391; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v112, v113, v96, vcc_lo12392; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v114, v14712393; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v11912394; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v49, 16, v3812395; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v114, v115, v98, vcc_lo12396; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v116, v1412397; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v116, v117, v100, vcc_lo12398; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v118, v3012399; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v118, v119, v102, vcc_lo12400; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v128, v4912401; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v128, v38, v34, vcc_lo12402; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3612403; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v130, v36, vcc_lo12404; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4812405; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v37, v48, vcc_lo12406; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5212407; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v129, v52, vcc_lo12408; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6412409; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v12912410; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v64, v53, v64, vcc_lo12411; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6812412; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v68, v65, v68, vcc_lo12413; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7012414; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v69, v70, vcc_lo12415; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8012416; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v81, v80, vcc_lo12417; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8212418; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v85, v82, vcc_lo12419; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8412420; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v97, v84, vcc_lo12421; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8612422; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v101, v86, vcc_lo12423; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9612424; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v96, v112, v96, vcc_lo12425; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9812426; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v5312427; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10012428; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v133, 16, v6912429; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3512430; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v135, 16, v8512431; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10212432; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v118, v102, vcc_lo12433; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3912434; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v36, v36, v39 :: v_dual_lshlrev_b32 v145, 16, v10112435; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3412436; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v128, v34, vcc_lo12437; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5112438; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v49, v51, vcc_lo12439; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5512440; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v12812441; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v64, v55, vcc_lo12442; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6712443; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v68, v67, vcc_lo12444; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7112445; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v147, 16, v11412446; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8312447; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v80, v83, vcc_lo12448; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8712449; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v68, v82, v87, vcc_lo12450; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9912451; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v84, v99, vcc_lo12452; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10312453; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v71, v86, v103 :: v_dual_lshlrev_b32 v30, 16, v13012454; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11312455; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v48, 16, v3712456; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v96, v113, vcc_lo12457; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11512458; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v98, v115, vcc_lo12459; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11712460; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v134, 16, v8112461; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v83, v100, v117, vcc_lo12462; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11912463; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v35, v119, vcc_lo12464; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3812465; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v34, v38, vcc_lo12466; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3012467; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v130, v14, vcc_lo12468; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4812469; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v37, v36, vcc_lo12470; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5212471; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)12472; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v3112473; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v129, v39, vcc_lo12474; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13112475; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v53, v49, vcc_lo12476; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13212477; GFX11-FAKE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v3112478; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v65, v55, vcc_lo12479; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13312480; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v37, v69, v64, vcc_lo12481; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13412482; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v38, v81, v67, vcc_lo12483; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13512484; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v85, v68, vcc_lo12485; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14412486; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v48, v97, v70, vcc_lo12487; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14512488; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v101, v71, vcc_lo12489; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v5012490; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v15, v31, vcc_lo12491; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v3212492; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v3112493; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v148, 16, v11612494; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)12495; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v5512496; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v52, vcc_lo12497; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v146, 16, v11212498; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v3312499; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)12500; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14612501; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v112, v80, vcc_lo12502; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v5312503; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v52, v33, vcc_lo12504; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v3212505; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v102, 16, v11812506; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)12507; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v31, v55 :: v_dual_lshlrev_b32 v64, 16, v5212508; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14712509; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v5312510; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v114, v82, vcc_lo12511; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14812512; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v116, v83, vcc_lo12513; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v50, v6412514; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v64, v52, v33, vcc_lo12515; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v6712516; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)12517; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v6412518; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v65, v53, v55, vcc_lo12519; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v10212520; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v68, 16, v6512521; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v50, v118, v84, vcc_lo12522; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3312523; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v64, v33, vcc_lo12524; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5512525; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v65, v55, vcc_lo12526; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5212527; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)12528; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v52, vcc_lo12529; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5312530; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v53, v55, v53, vcc_lo12531; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6712532; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v1312533; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v64, v33, vcc_lo12534; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5112535; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v128, v86, vcc_lo12536; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6812537; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v65, v53, vcc_lo12538; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5512539; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v6612540; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2912541; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v1212542; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v64, 16, v5412543; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)12544; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v64, v5312545; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v53, v66, v54, vcc_lo12546; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6512547; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v1312548; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v29, v13, vcc_lo12549; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5512550; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v2812551; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)12552; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v64, 16, v2912553; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo12554; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5412555; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v53, v54, vcc_lo12556; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5512557; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v28, v12, vcc_lo12558; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6612559; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)12560; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v54, v66, vcc_lo12561; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v6412562; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v64, 16, v5312563; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2812564; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v55, v29, v13 :: v_dual_lshlrev_b32 v66, 16, v1212565; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1312566; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)12567; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v55, v13, vcc_lo12568; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6412569; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v5512570; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v66, v6512571; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2712572; GFX11-FAKE16-NEXT:    v_perm_b32 v14, v14, v53, 0x504010012573; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v28, v12, vcc_lo12574; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2912575; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc_lo12576; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v1112577; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1212578; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v54, v12, vcc_lo12579; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)12580; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2912581; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v1012582; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo12583; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2812584; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo12585; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6512586; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)12587; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v5412588; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6412589; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v55, v13, vcc_lo12590; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2812591; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v2612592; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)12593; GFX11-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0x504010012594; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v54, v12, vcc_lo12595; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2912596; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v1112597; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v912598; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v2712599; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)12600; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v54, v2812601; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v27, v11, vcc_lo12602; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5512603; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v26, v10, vcc_lo12604; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2912605; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v2512606; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc_lo12607; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1112608; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v2612609; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)12610; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2912611; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v25, v9, vcc_lo12612; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2712613; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)12614; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo12615; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v2812616; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v1012617; GFX11-FAKE16-NEXT:    v_perm_b32 v12, v34, v12, 0x504010012618; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v55, v5412619; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v2512620; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v912621; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v26, v10, vcc_lo12622; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2712623; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc_lo12624; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1012625; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)12626; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v2912627; GFX11-FAKE16-NEXT:    v_perm_b32 v11, v35, v11, 0x504010012628; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v29, v10, vcc_lo12629; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v55, v5412630; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v25, v9, vcc_lo12631; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2612632; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)12633; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc_lo12634; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v912635; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v27, v9, vcc_lo12636; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2812637; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v2312638; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v29, v10, vcc_lo12639; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2512640; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v26, 16, v812641; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v712642; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)12643; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v2612644; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo12645; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2512646; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2712647; GFX11-FAKE16-NEXT:    v_perm_b32 v10, v36, v10, 0x504010012648; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v2412649; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)12650; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v712651; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v2612652; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v24, v8, vcc_lo12653; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v2812654; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)12655; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v2412656; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2512657; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v612658; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v2312659; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)12660; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2512661; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v812662; GFX11-FAKE16-NEXT:    v_perm_b32 v9, v37, v9, 0x504010012663; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo12664; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)12665; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v27, v2612666; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v24, v8 :: v_dual_lshlrev_b32 v25, 16, v2212667; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v29, v2812668; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v23, v7, vcc_lo12669; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2512670; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v6, vcc_lo12671; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v812672; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v26, v8, vcc_lo12673; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v712674; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo12675; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2412676; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)12677; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo12678; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2312679; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v2612680; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2212681; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v612682; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)12683; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v28, v2512684; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2712685; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v22, v6, vcc_lo12686; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2412687; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v512688; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v26, v8, vcc_lo12689; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v612690; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc_lo12691; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2512692; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2112693; GFX11-FAKE16-NEXT:    v_perm_b32 v8, v38, v8, 0x504010012694; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo12695; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2212696; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)12697; GFX11-FAKE16-NEXT:    v_perm_b32 v7, v39, v7, 0x504010012698; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo12699; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v2412700; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v412701; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2312702; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2212703; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2012704; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc_lo12705; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2512706; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v312707; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v512708; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v21, v5, vcc_lo12709; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v2412710; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)12711; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v2112712; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo12713; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v2212714; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v20, v4, vcc_lo12715; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v2312716; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc_lo12717; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2412718; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)12719; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v2012720; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v412721; GFX11-FAKE16-NEXT:    v_perm_b32 v6, v48, v6, 0x504010012722; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v1912723; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v2212724; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v19, v3, vcc_lo12725; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v512726; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)12727; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v23, v5, vcc_lo12728; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2412729; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v312730; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v1912731; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v20, v4, vcc_lo12732; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2112733; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc_lo12734; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v412735; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)12736; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v22, v4 :: v_dual_lshlrev_b32 v21, 16, v2312737; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2412738; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v19, v3, vcc_lo12739; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2112740; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v2212741; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v23, v5, vcc_lo12742; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2012743; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)12744; GFX11-FAKE16-NEXT:    v_perm_b32 v5, v49, v5, 0x504010012745; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo12746; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v312747; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo12748; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1912749; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v20, 16, v212750; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v1812751; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)12752; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2012753; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v2, v18 :: v_dual_lshlrev_b32 v23, 16, v2412754; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2312755; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo12756; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v1912757; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v012758; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)12759; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v31, v3, 0x504010012760; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v18, v2, vcc_lo12761; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v112762; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2012763; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo12764; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v2312765; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v1712766; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12767; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v112768; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo12769; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v1912770; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v17, v1 :: v_dual_lshlrev_b32 v20, 16, v1612771; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v212772; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)12773; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2012774; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v0 :: v_dual_lshlrev_b32 v19, 16, v1812775; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v1712776; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)12777; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v1912778; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v18, v2, vcc_lo12779; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v24, v2012780; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v17, v1, vcc_lo12781; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v212782; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)12783; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v19, v2 :: v_dual_lshlrev_b32 v23, 16, v1612784; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v012785; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2312786; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v16, v0, vcc_lo12787; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v112788; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v20, v1, vcc_lo12789; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1812790; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc_lo12791; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v012792; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v23, v0, vcc_lo12793; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1712794; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo12795; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2012796; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1612797; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo12798; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)12799; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1712800; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v2312801; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v1912802; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1812803; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)12804; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v50, v1, 0x504010012805; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v23, v0, vcc_lo12806; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1612807; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)12808; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v52, v0, 0x504010012809; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo12810; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2112811; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v32, v2, 0x504010012812; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v22, v4, vcc_lo12813; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)12814; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v15, v4, 0x504010012815; GFX11-FAKE16-NEXT:    v_perm_b32 v15, v33, v51, 0x504010012816; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]12817;12818; GFX12-TRUE16-LABEL: v_minimumnum_v32bf16:12819; GFX12-TRUE16:       ; %bb.0:12820; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x012821; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x012822; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x012823; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x012824; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x012825; GFX12-TRUE16-NEXT:    scratch_load_b32 v68, off, s3212826; GFX12-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v1512827; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.l, 012828; GFX12-TRUE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v1412829; GFX12-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v3012830; GFX12-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v2912831; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v3112832; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v35.l, v36.l12833; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v37.l, v36.l12834; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v33, v3312835; GFX12-TRUE16-NEXT:    v_and_b32_e32 v33, 0xffff0000, v1312836; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v34, v3412837; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v38.l, v36.l12838; GFX12-TRUE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v1212839; GFX12-TRUE16-NEXT:    v_and_b32_e32 v39, 0xffff0000, v2812840; GFX12-TRUE16-NEXT:    v_and_b32_e32 v48, 0xffff0000, v1112841; GFX12-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v2712842; GFX12-TRUE16-NEXT:    v_and_b32_e32 v50, 0xffff0000, v2612843; GFX12-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff0000, v2512844; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v39, v3912845; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v39.l, v36.l12846; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v49, v4912847; GFX12-TRUE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v1012848; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v50, v5012849; GFX12-TRUE16-NEXT:    v_and_b32_e32 v50, 0xffff0000, v912850; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v51, v5112851; GFX12-TRUE16-NEXT:    v_and_b32_e32 v51, 0xffff0000, v812852; GFX12-TRUE16-NEXT:    v_and_b32_e32 v52, 0xffff0000, v2412853; GFX12-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v2312854; GFX12-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v2212855; GFX12-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff0000, v2112856; GFX12-TRUE16-NEXT:    v_and_b32_e32 v64, 0xffff0000, v2012857; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v52, v5212858; GFX12-TRUE16-NEXT:    v_and_b32_e32 v52, 0xffff0000, v712859; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v53, v5312860; GFX12-TRUE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v612861; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v54, v5412862; GFX12-TRUE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v512863; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v55, v5512864; GFX12-TRUE16-NEXT:    v_and_b32_e32 v55, 0xffff0000, v412865; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v64, v6412866; GFX12-TRUE16-NEXT:    v_and_b32_e32 v64, 0xffff0000, v312867; GFX12-TRUE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v1912868; GFX12-TRUE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v1812869; GFX12-TRUE16-NEXT:    v_and_b32_e32 v67, 0xffff0000, v1712870; GFX12-TRUE16-NEXT:    v_and_b32_e32 v81, 0xffff0000, v1612871; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v82.l, v36.l12872; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v65, v6512873; GFX12-TRUE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v212874; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v66, v6612875; GFX12-TRUE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v112876; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v67, v6712877; GFX12-TRUE16-NEXT:    v_and_b32_e32 v67, 0xffff0000, v012878; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s15, v81, v8112879; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1512880; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v83, 16, v3012881; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v84, 16, v212882; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v86, 16, v012883; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v1712884; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v87, 16, v1612885; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s17, v83, v8312886; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v83.l, v36.l12887; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s42, v86, v8612888; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v96.l, v36.l12889; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12890; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)12891; GFX12-TRUE16-NEXT:    v_cndmask_b16 v96.h, v0.l, v16.l, s4212892; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s43, 0x8000, v96.h12893; GFX12-TRUE16-NEXT:    s_wait_loadcnt 0x012894; GFX12-TRUE16-NEXT:    v_and_b32_e32 v31, 0xffff0000, v6812895; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)12896; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v15.h, v68.h, vcc_lo12897; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)12898; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v31, v3112899; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h12900; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)12901; GFX12-TRUE16-NEXT:    v_cndmask_b16 v35.h, v68.h, v36.h, vcc_lo12902; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)12903; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v36, v3512904; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s42, 0x8000, v35.h12905; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)12906; GFX12-TRUE16-NEXT:    v_cndmask_b16 v31.l, v35.h, v36.h, vcc_lo12907; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12908; GFX12-TRUE16-NEXT:    v_cndmask_b16 v31.h, v31.l, v36.h, s012909; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v31.l12910; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v32, v3212911; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)12912; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3612913; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12914; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v14.h, v30.h, s012915; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12916; GFX12-TRUE16-NEXT:    v_cndmask_b16 v37.h, v30.h, v36.h, s112917; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v36.h12918; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v36, v3712919; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s44, 0x8000, v37.h12920; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12921; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)12922; GFX12-TRUE16-NEXT:    v_cndmask_b16 v32.l, v37.h, v36.h, s012923; GFX12-TRUE16-NEXT:    v_cndmask_b16 v32.h, v32.l, v36.h, s112924; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v32.l12925; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v33, v3312926; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)12927; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v3612928; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12929; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v13.h, v29.h, s112930; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12931; GFX12-TRUE16-NEXT:    v_cndmask_b16 v38.h, v29.h, v36.h, s212932; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v36.h12933; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v36, v3812934; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12935; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12936; GFX12-TRUE16-NEXT:    v_cndmask_b16 v33.l, v38.h, v36.h, s112937; GFX12-TRUE16-NEXT:    v_cndmask_b16 v33.h, v33.l, v36.h, s212938; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v33.l12939; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v34, v3412940; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)12941; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v3612942; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12943; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v12.h, v28.h, s212944; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12945; GFX12-TRUE16-NEXT:    v_cndmask_b16 v39.h, v28.h, v36.h, s312946; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v36.h12947; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v36, v3912948; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12949; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12950; GFX12-TRUE16-NEXT:    v_cndmask_b16 v34.l, v39.h, v36.h, s212951; GFX12-TRUE16-NEXT:    v_cndmask_b16 v34.h, v34.l, v36.h, s312952; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v34.l12953; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v48, v4812954; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v48.l, v36.l12955; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12956; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v3612957; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12958; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v11.h, v27.h, s312959; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12960; GFX12-TRUE16-NEXT:    v_cndmask_b16 v48.h, v27.h, v36.h, s412961; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v36.h12962; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s3, v36, v4812963; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12964; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12965; GFX12-TRUE16-NEXT:    v_cndmask_b16 v35.l, v48.h, v36.h, s312966; GFX12-TRUE16-NEXT:    v_cndmask_b16 v37.l, v35.l, v36.h, s412967; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v35.l12968; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s4, v49, v4912969; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v49.l, v36.l12970; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12971; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s3, 0, v3612972; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12973; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v10.h, v26.h, s412974; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12975; GFX12-TRUE16-NEXT:    v_cndmask_b16 v49.h, v26.h, v36.h, s512976; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s5, 0x8000, v36.h12977; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s4, v36, v4912978; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12979; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12980; GFX12-TRUE16-NEXT:    v_cndmask_b16 v38.l, v49.h, v36.h, s412981; GFX12-TRUE16-NEXT:    v_cndmask_b16 v39.l, v38.l, v36.h, s512982; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v38.l12983; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s5, v50, v5012984; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v50.l, v36.l12985; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)12986; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v3612987; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12988; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v9.h, v25.h, s512989; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)12990; GFX12-TRUE16-NEXT:    v_cndmask_b16 v50.h, v25.h, v36.h, s612991; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s6, 0x8000, v36.h12992; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s5, v36, v5012993; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)12994; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)12995; GFX12-TRUE16-NEXT:    v_cndmask_b16 v48.l, v50.h, v36.h, s512996; GFX12-TRUE16-NEXT:    v_cndmask_b16 v49.l, v48.l, v36.h, s612997; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v48.l12998; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s6, v51, v5112999; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v51.l, v36.l13000; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13001; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s5, 0, v3613002; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13003; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v8.h, v24.h, s613004; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13005; GFX12-TRUE16-NEXT:    v_cndmask_b16 v51.h, v24.h, v36.h, s713006; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s7, 0x8000, v36.h13007; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s6, v36, v5113008; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13009; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13010; GFX12-TRUE16-NEXT:    v_cndmask_b16 v50.l, v51.h, v36.h, s613011; GFX12-TRUE16-NEXT:    v_cndmask_b16 v51.l, v50.l, v36.h, s713012; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v50.l13013; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s7, v52, v5213014; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v52.l, v36.l13015; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13016; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s6, 0, v3613017; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13018; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v7.h, v23.h, s713019; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13020; GFX12-TRUE16-NEXT:    v_cndmask_b16 v52.h, v23.h, v36.h, s813021; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s8, 0x8000, v36.h13022; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s7, v36, v5213023; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13024; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13025; GFX12-TRUE16-NEXT:    v_cndmask_b16 v52.l, v52.h, v36.h, s713026; GFX12-TRUE16-NEXT:    v_cndmask_b16 v69.l, v52.l, v36.h, s813027; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v52.l13028; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s8, v53, v5313029; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v53.l, v36.l13030; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13031; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s7, 0, v3613032; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13033; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v6.h, v22.h, s813034; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13035; GFX12-TRUE16-NEXT:    v_cndmask_b16 v53.h, v22.h, v36.h, s913036; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s9, 0x8000, v36.h13037; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s8, v36, v5313038; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13039; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13040; GFX12-TRUE16-NEXT:    v_cndmask_b16 v53.l, v53.h, v36.h, s813041; GFX12-TRUE16-NEXT:    v_cndmask_b16 v69.h, v53.l, v36.h, s913042; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v53.l13043; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s9, v54, v5413044; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v54.l, v36.l13045; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13046; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s8, 0, v3613047; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13048; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v5.h, v21.h, s913049; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13050; GFX12-TRUE16-NEXT:    v_cndmask_b16 v54.h, v21.h, v36.h, s1013051; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s10, 0x8000, v36.h13052; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s9, v36, v5413053; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13054; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13055; GFX12-TRUE16-NEXT:    v_cndmask_b16 v54.l, v54.h, v36.h, s913056; GFX12-TRUE16-NEXT:    v_cndmask_b16 v70.l, v54.l, v36.h, s1013057; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v54.l13058; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s10, v55, v5513059; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v55.l, v36.l13060; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13061; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s9, 0, v3613062; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13063; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v4.h, v20.h, s1013064; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13065; GFX12-TRUE16-NEXT:    v_cndmask_b16 v55.h, v20.h, v36.h, s1113066; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s11, 0x8000, v36.h13067; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s10, v36, v5513068; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13069; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13070; GFX12-TRUE16-NEXT:    v_cndmask_b16 v55.l, v55.h, v36.h, s1013071; GFX12-TRUE16-NEXT:    v_cndmask_b16 v70.h, v55.l, v36.h, s1113072; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v55.l13073; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s11, v64, v6413074; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v64.l, v36.l13075; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13076; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s10, 0, v3613077; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13078; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v3.h, v19.h, s1113079; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13080; GFX12-TRUE16-NEXT:    v_cndmask_b16 v64.h, v19.h, v36.h, s1213081; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s12, 0x8000, v36.h13082; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s11, v36, v6413083; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13084; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13085; GFX12-TRUE16-NEXT:    v_cndmask_b16 v64.l, v64.h, v36.h, s1113086; GFX12-TRUE16-NEXT:    v_cndmask_b16 v71.l, v64.l, v36.h, s1213087; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v64.l13088; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s12, v65, v6513089; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v65.l, v36.l13090; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13091; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s11, 0, v3613092; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13093; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v2.h, v18.h, s1213094; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13095; GFX12-TRUE16-NEXT:    v_cndmask_b16 v65.h, v18.h, v36.h, s1313096; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s13, 0x8000, v36.h13097; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s12, v36, v6513098; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13099; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13100; GFX12-TRUE16-NEXT:    v_cndmask_b16 v65.l, v65.h, v36.h, s1213101; GFX12-TRUE16-NEXT:    v_cndmask_b16 v71.h, v65.l, v36.h, s1313102; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v65.l13103; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s13, v66, v6613104; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v66.l, v36.l13105; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13106; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s12, 0, v3613107; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13108; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v1.h, v17.h, s1313109; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13110; GFX12-TRUE16-NEXT:    v_cndmask_b16 v66.h, v17.h, v36.h, s1413111; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s14, 0x8000, v36.h13112; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s13, v36, v6613113; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13114; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)13115; GFX12-TRUE16-NEXT:    v_cndmask_b16 v66.l, v66.h, v36.h, s1313116; GFX12-TRUE16-NEXT:    v_cndmask_b16 v80.l, v66.l, v36.h, s1413117; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v66.l13118; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s14, v67, v6713119; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v67.l, v36.l13120; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)13121; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s13, 0, v3613122; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13123; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v0.h, v16.h, s1413124; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)13125; GFX12-TRUE16-NEXT:    v_cndmask_b16 v67.h, v16.h, v36.h, s1513126; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s15, v81, v8113127; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v36.h13128; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v6813129; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s14, v36, v6713130; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13131; GFX12-TRUE16-NEXT:    v_cndmask_b16 v82.h, v15.l, v68.l, s1513132; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)13133; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s15, v81, v8113134; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1413135; GFX12-TRUE16-NEXT:    v_cndmask_b16 v67.l, v67.h, v36.h, s1413136; GFX12-TRUE16-NEXT:    v_cndmask_b16 v15.l, v67.l, v36.h, s1613137; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v67.l13138; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v82.h13139; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)13140; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s14, 0, v3613141; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13142; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v68.l, v82.h, s1513143; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s15, v82, v3613144; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13145; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13146; GFX12-TRUE16-NEXT:    v_cndmask_b16 v68.l, v36.h, v82.h, s1513147; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s15, 0x8000, v36.h13148; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.h, v68.l, v82.h, s1613149; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s16, v81, v8113150; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1313151; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2913152; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13153; GFX12-TRUE16-NEXT:    v_cndmask_b16 v30.h, v14.h, v36.h, s1513154; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v68.l13155; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.h, v14.l, v30.l, s1613156; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v14.l, v36.l13157; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s18, v82, v8213158; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2813159; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s15, 0, v3613160; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v30.l, v14.h, s1713161; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v14.h13162; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)13163; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s19, v82, v8213164; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2713165; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s16, v14, v3613166; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)13167; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s20, v82, v8213168; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13169; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.l, v36.h, v14.h, s1613170; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s16, 0x8000, v36.h13171; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2613172; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)13173; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.h, v14.l, v14.h, s1713174; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s17, v81, v8113175; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1213176; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s21, v82, v8213177; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2513178; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13179; GFX12-TRUE16-NEXT:    v_cndmask_b16 v29.h, v13.h, v36.h, s1613180; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v14.l13181; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.h, v13.l, v29.l, s1713182; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v13.l, v36.l13183; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s22, v82, v8213184; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2413185; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s16, 0, v3613186; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v29.l, v13.h, s1813187; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s18, 0x8000, v13.h13188; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)13189; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s23, v82, v8213190; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2313191; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s17, v13, v3613192; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13193; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.l, v14.l, v29.h, s1613194; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13195; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s24, v82, v8213196; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.l, v36.h, v13.h, s1713197; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s17, 0x8000, v36.h13198; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2213199; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)13200; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v13.l, v13.h, s1813201; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s18, v81, v8113202; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1113203; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s25, v82, v8213204; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2113205; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13206; GFX12-TRUE16-NEXT:    v_cndmask_b16 v28.h, v12.h, v36.h, s1713207; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v13.l13208; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v12.l, v28.l, s1813209; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v36.l13210; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s26, v82, v8213211; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v2013212; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s17, 0, v3613213; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v28.l, v12.h, s1913214; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s19, 0x8000, v12.h13215; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)13216; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s27, v82, v8213217; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v82, 16, v1913218; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s18, v12, v3613219; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13220; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.l, v13.l, v28.h, s1713221; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13222; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s28, v82, v8213223; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.l, v36.h, v12.h, s1813224; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s18, 0x8000, v36.h13225; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v82.l, v36.l13226; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13227; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.h, v12.l, v12.h, s1913228; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s19, v81, v8113229; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1013230; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13231; GFX12-TRUE16-NEXT:    v_cndmask_b16 v27.h, v11.h, v36.h, s1813232; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v12.l13233; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.h, v11.l, v27.l, s1913234; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v36.l13235; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13236; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s18, 0, v3613237; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v27.l, v11.h, s2013238; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s20, 0x8000, v11.h13239; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13240; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13241; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.l, v12.l, v27.h, s1813242; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s19, v11, v3613243; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13244; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13245; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.l, v36.h, v11.h, s1913246; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s19, 0x8000, v36.h13247; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.h, v11.l, v11.h, s2013248; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s20, v81, v8113249; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v913250; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13251; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13252; GFX12-TRUE16-NEXT:    v_cndmask_b16 v26.h, v10.h, v36.h, s1913253; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v11.l13254; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.h, v10.l, v26.l, s2013255; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v10.l, v36.l13256; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s19, 0, v3613257; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13258; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v26.l, v10.h, s2113259; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s21, 0x8000, v10.h13260; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13261; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.l, v11.l, v26.h, s1913262; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13263; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s20, v10, v3613264; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13265; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.l, v36.h, v10.h, s2013266; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s20, 0x8000, v36.h13267; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13268; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v10.l, v10.h, s2113269; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s21, v81, v8113270; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v813271; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13272; GFX12-TRUE16-NEXT:    v_cndmask_b16 v25.h, v9.h, v36.h, s2013273; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v10.l13274; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v9.l, v25.l, s2113275; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v36.l13276; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13277; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s20, 0, v3613278; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v25.l, v9.h, s2213279; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s22, 0x8000, v9.h13280; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13281; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13282; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.l, v10.l, v25.h, s2013283; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s21, v9, v3613284; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13285; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13286; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.l, v36.h, v9.h, s2113287; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s21, 0x8000, v36.h13288; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v9.l, v9.h, s2213289; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s22, v81, v8113290; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v713291; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13292; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13293; GFX12-TRUE16-NEXT:    v_cndmask_b16 v24.h, v8.h, v36.h, s2113294; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v9.l13295; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v8.l, v24.l, s2213296; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v36.l13297; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s21, 0, v3613298; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13299; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v24.l, v8.h, s2313300; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s23, 0x8000, v8.h13301; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13302; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.l, v9.l, v24.h, s2113303; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13304; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s22, v8, v3613305; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13306; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.l, v36.h, v8.h, s2213307; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s22, 0x8000, v36.h13308; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13309; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v8.l, v8.h, s2313310; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s23, v81, v8113311; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v613312; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13313; GFX12-TRUE16-NEXT:    v_cndmask_b16 v23.h, v7.h, v36.h, s2213314; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v8.l13315; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v7.l, v23.l, s2313316; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v36.l13317; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13318; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s22, 0, v3613319; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v23.l, v7.h, s2413320; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s24, 0x8000, v7.h13321; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13322; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13323; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.l, v8.l, v23.h, s2213324; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s23, v7, v3613325; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13326; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13327; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.l, v36.h, v7.h, s2313328; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s23, 0x8000, v36.h13329; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v7.l, v7.h, s2413330; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s24, v81, v8113331; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v513332; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13333; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13334; GFX12-TRUE16-NEXT:    v_cndmask_b16 v22.h, v6.h, v36.h, s2313335; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v7.l13336; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v6.l, v22.l, s2413337; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v36.l13338; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s23, 0, v3613339; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13340; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v22.l, v6.h, s2513341; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s25, 0x8000, v6.h13342; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13343; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.l, v7.l, v22.h, s2313344; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13345; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s24, v6, v3613346; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13347; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.l, v36.h, v6.h, s2413348; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s24, 0x8000, v36.h13349; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13350; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v6.l, v6.h, s2513351; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s25, v81, v8113352; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v413353; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13354; GFX12-TRUE16-NEXT:    v_cndmask_b16 v21.h, v5.h, v36.h, s2413355; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v6.l13356; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v5.l, v21.l, s2513357; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v36.l13358; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13359; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s24, 0, v3613360; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v21.l, v5.h, s2613361; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s26, 0x8000, v5.h13362; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13363; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)13364; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.l, v6.l, v21.h, s2413365; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s25, v5, v3613366; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13367; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)13368; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v36.h, v5.h, s2513369; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s25, 0x8000, v36.h13370; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v5.l, v5.h, s2613371; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s26, v81, v8113372; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v313373; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13374; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)13375; GFX12-TRUE16-NEXT:    v_cndmask_b16 v20.h, v4.h, v36.h, s2513376; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v5.l13377; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v20.l, s2613378; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v36.l13379; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s25, 0, v3613380; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13381; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v20.l, v4.h, s2713382; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s27, 0x8000, v4.h13383; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13384; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v5.l, v20.h, s2513385; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)13386; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s26, v4, v3613387; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13388; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v36.h, v4.h, s2613389; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s26, 0x8000, v36.h13390; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)13391; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v4.l, v4.h, s2713392; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s27, v81, v8113393; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v1813394; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13395; GFX12-TRUE16-NEXT:    v_cndmask_b16 v18.h, v3.h, v36.h, s2613396; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v4.l13397; GFX12-TRUE16-NEXT:    v_cndmask_b16 v83.h, v3.l, v19.l, s2713398; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v113399; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s29, v81, v8113400; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)13401; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s26, 0, v3613402; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v19.l, v83.h, s2813403; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s28, v84, v8413404; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s40, v3, v313405; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s41, 0x8000, v83.h13406; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v19.l, v36.l13407; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s27, v83, v3613408; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13409; GFX12-TRUE16-NEXT:    v_cndmask_b16 v82.h, v2.l, v18.l, s2813410; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s28, 0x8000, v36.h13411; GFX12-TRUE16-NEXT:    v_cndmask_b16 v19.h, v1.l, v17.l, s4013412; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v32.h, v37.h, s4413413; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v36.h, v83.h, s2713414; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s40, 0x8000, v82.h13415; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s27, v85, v8513416; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.l, v18.h, s2613417; GFX12-TRUE16-NEXT:    v_cndmask_b16 v14.h, v32.l, v1.l, s013418; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v3.l, v83.h, s4113419; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s41, v87, v8713420; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13421; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)13422; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.h, v36.h, s2813423; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v3.l13424; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v31.h, v35.h, s4213425; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s42, 0x8000, v39.h13426; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s28, 0x8000, v19.h13427; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s45, 0, v3613428; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v18.l, v82.h, s2913429; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s29, 0x8000, v38.h13430; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)13431; GFX12-TRUE16-NEXT:    v_cndmask_b16 v15.h, v31.l, v0.h, vcc_lo13432; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13433; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v34.h, v39.h, s4213434; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v48.h13435; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s44, v82, v3613436; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v33.h, v38.h, s2913437; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h13438; GFX12-TRUE16-NEXT:    v_cndmask_b16 v12.h, v34.l, v1.h, s213439; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)13440; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v37.l, v48.h, vcc_lo13441; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13442; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v36.h, v82.h, s4413443; GFX12-TRUE16-NEXT:    v_cndmask_b16 v13.h, v33.l, v0.h, s113444; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v49.h13445; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v50.h13446; GFX12-TRUE16-NEXT:    v_cndmask_b16 v11.h, v35.l, v1.h, s313447; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v82.h, s4013448; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v51.h13449; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v54.h13450; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13451; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v49.l, v50.h, s113452; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v3.l, v0.l, s4513453; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v36.h, s013454; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v1.l13455; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)13456; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v39.l, v49.h, vcc_lo13457; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v52.h13458; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v51.l, v51.h, s213459; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v53.h13460; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3613461; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v17.l, v19.h, s2713462; GFX12-TRUE16-NEXT:    v_cndmask_b16 v10.h, v38.l, v0.h, s413463; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13464; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v69.l, v52.h, s013465; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v55.h13466; GFX12-TRUE16-NEXT:    v_cndmask_b16 v9.h, v48.l, v1.h, s513467; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v19, v3613468; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h13469; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v69.h, v53.h, s213470; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13471; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v70.h, v55.h, s413472; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v66.h13473; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.h, v36.h, v19.h, s113474; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v65.h13475; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v50.l, v2.h, s613476; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v70.l, v54.h, s313477; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v52.l, v0.h, s713478; GFX12-TRUE16-NEXT:    v_cndmask_b16 v17.l, v16.h, v19.h, s2813479; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v53.l, v1.h, s813480; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13481; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v71.h, v65.h, s113482; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v54.l, v2.h, s913483; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v67.h13484; GFX12-TRUE16-NEXT:    v_cndmask_b16 v17.l, v17.l, v36.h, s013485; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v16.h13486; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v64.h13487; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v65.l, v1.h, s1213488; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13489; GFX12-TRUE16-NEXT:    v_cndmask_b16 v15.l, v15.l, v67.h, s313490; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v55.l, v3.h, s1013491; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s4, 0, v3613492; GFX12-TRUE16-NEXT:    v_cndmask_b16 v36.h, v16.l, v96.h, s4113493; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v71.l, v64.h, s013494; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.l, v80.l, v66.h, s213495; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)13496; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v1.l, v2.l, vcc_lo13497; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13498; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v16.h, v17.l, s413499; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v96, v3613500; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v64.l, v0.h, s1113501; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v66.l, v16.l, s1313502; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v67.l, v15.l, s1413503; GFX12-TRUE16-NEXT:    v_cndmask_b16 v15.l, v68.l, v30.h, s1513504; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13505; GFX12-TRUE16-NEXT:    v_cndmask_b16 v16.l, v36.h, v96.h, s013506; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v36.h13507; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)13508; GFX12-TRUE16-NEXT:    v_cndmask_b16 v17.h, v16.l, v96.h, s4313509; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13510; GFX12-TRUE16-NEXT:    v_cndmask_b16 v17.h, v17.h, v36.h, s013511; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v36.h, v16.l13512; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)13513; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v3613514; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)13515; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v16.l, v17.h, s013516; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]13517;13518; GFX12-FAKE16-LABEL: v_minimumnum_v32bf16:13519; GFX12-FAKE16:       ; %bb.0:13520; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x013521; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x013522; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x013523; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x013524; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x013525; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v71, 16, v2513526; GFX12-FAKE16-NEXT:    v_and_b32_e32 v50, 0xffff0000, v1213527; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v51, 16, v2813528; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v1213529; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v39, 16, v2913530; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v48, 16, v1313531; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e64 s1, v50, v5013532; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v35, 16, v3013533; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v36, 16, v1413534; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v83, 16, v2413535; GFX12-FAKE16-NEXT:    v_and_b32_e32 v70, 0xffff0000, v913536; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)13537; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v52, v52, v51, s113538; GFX12-FAKE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v1313539; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v80, 16, v913540; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v103, 16, v2113541; GFX12-FAKE16-NEXT:    v_and_b32_e32 v82, 0xffff0000, v813542; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v84, 16, v813543; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e64 s0, v38, v3813544; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v87, 16, v2313545; GFX12-FAKE16-NEXT:    v_and_b32_e32 v86, 0xffff0000, v713546; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v96, 16, v713547; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v99, 16, v2213548; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)13549; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v48, v48, v39, s013550; GFX12-FAKE16-NEXT:    v_and_b32_e32 v34, 0xffff0000, v1413551; GFX12-FAKE16-NEXT:    v_and_b32_e32 v98, 0xffff0000, v613552; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v100, 16, v613553; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v115, 16, v2013554; GFX12-FAKE16-NEXT:    v_and_b32_e32 v102, 0xffff0000, v513555; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v34, v3413556; GFX12-FAKE16-NEXT:    v_and_b32_e32 v37, 0xffff0000, v3013557; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v112, 16, v513558; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v119, 16, v1913559; GFX12-FAKE16-NEXT:    v_and_b32_e32 v114, 0xffff0000, v413560; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13561; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v36, v35, vcc_lo13562; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v70, v7013563; GFX12-FAKE16-NEXT:    v_and_b32_e32 v49, 0xffff0000, v2913564; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v116, 16, v413565; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v131, 16, v1813566; GFX12-FAKE16-NEXT:    v_and_b32_e32 v118, 0xffff0000, v313567; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13568; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v80, v71, vcc_lo13569; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v82, v8213570; GFX12-FAKE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v2813571; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v128, 16, v313572; GFX12-FAKE16-NEXT:    v_and_b32_e32 v130, 0xffff0000, v213573; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v132, 16, v213574; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13575; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v84, v83, vcc_lo13576; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v86, v8613577; GFX12-FAKE16-NEXT:    v_and_b32_e32 v69, 0xffff0000, v2613578; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v135, 16, v1713579; GFX12-FAKE16-NEXT:    v_and_b32_e32 v134, 0xffff0000, v113580; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v55, 16, v2713581; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13582; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v96, v87, vcc_lo13583; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v98, v9813584; GFX12-FAKE16-NEXT:    v_and_b32_e32 v81, 0xffff0000, v2513585; GFX12-FAKE16-NEXT:    v_and_b32_e32 v54, 0xffff0000, v1113586; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v144, 16, v113587; GFX12-FAKE16-NEXT:    v_and_b32_e32 v146, 0xffff0000, v013588; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13589; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v100, v99, vcc_lo13590; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v102, v10213591; GFX12-FAKE16-NEXT:    v_and_b32_e32 v85, 0xffff0000, v2413592; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v147, 16, v1613593; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v34, 16, v013594; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e64 s2, v54, v5413595; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13596; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v112, v103, vcc_lo13597; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v114, v11413598; GFX12-FAKE16-NEXT:    v_and_b32_e32 v101, 0xffff0000, v2213599; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v1413600; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v64, 16, v1113601; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v67, 16, v2613602; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13603; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v96, v116, v115, vcc_lo13604; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v118, v11813605; GFX12-FAKE16-NEXT:    v_and_b32_e32 v113, 0xffff0000, v2113606; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)13607; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v64, v64, v55, s213608; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v68, 16, v1013609; GFX12-FAKE16-NEXT:    scratch_load_b32 v31, off, s3213610; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13611; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v98, v128, v119, vcc_lo13612; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v130, v13013613; GFX12-FAKE16-NEXT:    v_and_b32_e32 v117, 0xffff0000, v2013614; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v33, 16, v1513615; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13616; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v100, v132, v131, vcc_lo13617; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v134, v13413618; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13619; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v102, v144, v135 :: v_dual_and_b32 v133, 0xffff0000, v1813620; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v146, v14613621; GFX12-FAKE16-NEXT:    v_and_b32_e32 v145, 0xffff0000, v1713622; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v112, 16, v9613623; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13624; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v34, v147, vcc_lo13625; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v54, v5413626; GFX12-FAKE16-NEXT:    v_and_b32_e32 v65, 0xffff0000, v2713627; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13628; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v54, v14, v30 :: v_dual_and_b32 v97, 0xffff0000, v2313629; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v37, v3713630; GFX12-FAKE16-NEXT:    v_and_b32_e32 v32, 0xffff0000, v1513631; GFX12-FAKE16-NEXT:    v_and_b32_e32 v129, 0xffff0000, v1913632; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13633; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v35, v36, vcc_lo13634; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v49, v4913635; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13636; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v39, v48, vcc_lo13637; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v5313638; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13639; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v51, v52, vcc_lo13640; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6513641; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v116, 16, v10013642; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13643; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)13644; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v55, v55, v64 :: v_dual_lshlrev_b32 v130, 16, v5113645; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v69, v6913646; GFX12-FAKE16-NEXT:    v_and_b32_e32 v66, 0xffff0000, v1013647; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v128, 16, v3413648; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e64 s3, v66, v6613649; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)13650; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)13651; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v68, v68, v67, s313652; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13653; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v67, v68, vcc_lo13654; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v81, v8113655; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v6813656; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v81, 16, v8013657; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13658; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v71, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6713659; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v85, v8513660; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13661; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v83, v83, v80, vcc_lo13662; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v97, v9713663; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v66, 16, v3013664; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v97, 16, v8413665; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13666; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v87, v87, v82 :: v_dual_lshlrev_b32 v134, 16, v8313667; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v101, v10113668; GFX12-FAKE16-NEXT:    v_and_b32_e32 v38, 0xffff0000, v1613669; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13670; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v99, v99, v84, vcc_lo13671; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v113, v11313672; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13673; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)13674; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v103, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9913675; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v117, v11713676; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v3613677; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13678; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v113, v115, v96, vcc_lo13679; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v129, v12913680; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v85, 16, v8213681; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13682; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)13683; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v115, v119, v98 :: v_dual_lshlrev_b32 v146, 16, v11313684; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v133, v13313685; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v37, 16, v4813686; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13687; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v117, v131, v100, vcc_lo13688; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v145, v14513689; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v101, 16, v8613690; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13691; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v119, v135, v102, vcc_lo13692; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v38, v3813693; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13694; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v38, v147, v34 :: v_dual_lshlrev_b32 v49, 16, v5213695; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v66, v6613696; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)13697; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e64 s0, v49, v13013698; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13699; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v66, v30, v54 :: v_dual_lshlrev_b32 v53, 16, v6413700; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v3513701; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v14, v3013702; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v69, 16, v7013703; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v14, 16, v11713704; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13705; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v130, v35, v36 :: v_dual_lshlrev_b32 v129, 16, v3913706; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)13707; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v37, v12913708; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_sdst(0)13709; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v129, v51, v52, s013710; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13711; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v37, v39, v48 :: v_dual_lshlrev_b32 v118, 16, v10213712; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v131, 16, v5513713; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)13714; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v53, v13113715; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13716; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v55, v64 :: v_dual_lshlrev_b32 v50, 16, v1513717; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v133, 16, v7113718; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v13213719; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13720; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v65, v67, v68, vcc_lo13721; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)13722; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v69, v13313723; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v135, 16, v8713724; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13725; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v69, v71, v70 :: v_dual_lshlrev_b32 v132, 16, v6513726; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v81, v13413727; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13728; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v81, v83, v80, vcc_lo13729; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v85, v13513730; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v145, 16, v10313731; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13732; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v85, v87, v82, vcc_lo13733; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v97, v14413734; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13735; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v97, v99, v84 :: v_dual_lshlrev_b32 v114, 16, v9813736; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v101, v14513737; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v147, 16, v11513738; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13739; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)13740; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v101, v103, v86 :: v_dual_lshlrev_b32 v144, 16, v9713741; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v112, v14613742; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13743; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v112, v113, v96, vcc_lo13744; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v114, v14713745; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v30, 16, v11913746; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v49, 16, v3813747; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13748; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v114, v115, v98, vcc_lo13749; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v116, v1413750; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13751; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v116, v117, v100, vcc_lo13752; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v118, v3013753; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13754; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v118, v119, v102, vcc_lo13755; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v128, v4913756; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13757; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v128, v38, v34, vcc_lo13758; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3613759; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13760; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v130, v36, vcc_lo13761; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4813762; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13763; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v37, v48, vcc_lo13764; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5213765; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13766; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v129, v52, vcc_lo13767; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6413768; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v52, 16, v12913769; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13770; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v64, v53, v64, vcc_lo13771; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6813772; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13773; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v68, v65, v68, vcc_lo13774; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7013775; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13776; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v69, v70, vcc_lo13777; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8013778; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13779; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v81, v80, vcc_lo13780; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8213781; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13782; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v85, v82, vcc_lo13783; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8413784; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13785; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v97, v84, vcc_lo13786; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8613787; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13788; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v101, v86, vcc_lo13789; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9613790; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13791; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v96, v112, v96, vcc_lo13792; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9813793; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13794; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v98, v114, v98 :: v_dual_lshlrev_b32 v131, 16, v5313795; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10013796; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13797; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v100, v116, v100 :: v_dual_lshlrev_b32 v133, 16, v6913798; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3513799; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13800; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v14, v14, v35 :: v_dual_lshlrev_b32 v135, 16, v8513801; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10213802; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13803; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v118, v102, vcc_lo13804; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3913805; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13806; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v36, v36, v39 :: v_dual_lshlrev_b32 v145, 16, v10113807; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3413808; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13809; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v128, v34, vcc_lo13810; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5113811; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13812; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v49, v51, vcc_lo13813; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5513814; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v51, 16, v12813815; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13816; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v64, v55, vcc_lo13817; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6713818; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13819; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v68, v67, vcc_lo13820; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7113821; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13822; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v64, v70, v71 :: v_dual_lshlrev_b32 v147, 16, v11413823; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8313824; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13825; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v67, v80, v83, vcc_lo13826; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8713827; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13828; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v68, v82, v87, vcc_lo13829; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v9913830; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13831; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v70, v84, v99, vcc_lo13832; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v10313833; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13834; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v71, v86, v103 :: v_dual_lshlrev_b32 v30, 16, v13013835; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11313836; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v48, 16, v3713837; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13838; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v80, v96, v113, vcc_lo13839; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11513840; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13841; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v82, v98, v115, vcc_lo13842; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11713843; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v134, 16, v8113844; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13845; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v83, v100, v117, vcc_lo13846; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v11913847; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13848; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v84, v35, v119, vcc_lo13849; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3813850; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13851; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v86, v34, v38, vcc_lo13852; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v3013853; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13854; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v14, v130, v14, vcc_lo13855; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4813856; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13857; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v30, v37, v36, vcc_lo13858; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5213859; GFX12-FAKE16-NEXT:    s_wait_loadcnt 0x013860; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v52, 16, v3113861; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13862; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v34, v129, v39, vcc_lo13863; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13113864; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13865; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v35, v53, v49, vcc_lo13866; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13213867; GFX12-FAKE16-NEXT:    v_and_b32_e32 v53, 0xffff0000, v3113868; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13869; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v36, v65, v55, vcc_lo13870; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13313871; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13872; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v37, v69, v64, vcc_lo13873; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13413874; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13875; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v38, v81, v67, vcc_lo13876; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v13513877; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13878; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v39, v85, v68, vcc_lo13879; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14413880; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13881; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v48, v97, v70, vcc_lo13882; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14513883; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13884; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v49, v101, v71, vcc_lo13885; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v50, v5013886; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13887; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v15, v31, vcc_lo13888; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v3213889; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v32, 16, v3113890; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v148, 16, v11613891; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_2)13892; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v5513893; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13894; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v52, vcc_lo13895; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v146, 16, v11213896; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v50, 16, v3313897; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)13898; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14613899; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13900; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v15, v112, v80, vcc_lo13901; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v53, v5313902; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13903; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v52, v33, vcc_lo13904; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v32, v3213905; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v102, 16, v11813906; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13907; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)13908; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v31, v55 :: v_dual_lshlrev_b32 v64, 16, v5213909; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14713910; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v5313911; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13912; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v31, v114, v82, vcc_lo13913; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v14813914; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13915; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v32, v116, v83, vcc_lo13916; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v50, v6413917; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13918; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v64, v52, v33, vcc_lo13919; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v6713920; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)13921; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v67, 16, v6413922; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13923; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v65, v53, v55, vcc_lo13924; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v10213925; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v68, 16, v6513926; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13927; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v50, v118, v84, vcc_lo13928; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3313929; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13930; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v64, v33, vcc_lo13931; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5513932; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13933; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v55, v65, v55, vcc_lo13934; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5213935; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13936; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v33, v52, vcc_lo13937; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5313938; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13939; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v53, v55, v53, vcc_lo13940; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6713941; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v1313942; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13943; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v33, v64, v33, vcc_lo13944; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5113945; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13946; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v52, v128, v86, vcc_lo13947; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6813948; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13949; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v51, v65, v53, vcc_lo13950; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5513951; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v53, 16, v6613952; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2913953; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v1213954; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13955; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v13, v13, v29 :: v_dual_lshlrev_b32 v64, 16, v5413956; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)13957; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v64, v5313958; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13959; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v53, v66, v54, vcc_lo13960; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6513961; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v1313962; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13963; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v29, v13, vcc_lo13964; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5513965; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v2813966; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)13967; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v64, 16, v2913968; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13969; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo13970; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v5413971; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13972; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v53, v54, vcc_lo13973; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5513974; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13975; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v28, v12, vcc_lo13976; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6613977; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13978; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v54, v66, vcc_lo13979; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v65, v6413980; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v64, 16, v5313981; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2813982; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13983; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v55, v29, v13 :: v_dual_lshlrev_b32 v66, 16, v1213984; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1313985; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13986; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)13987; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v55, v13, vcc_lo13988; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6413989; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13990; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v53, v53, v54 :: v_dual_lshlrev_b32 v64, 16, v5513991; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v66, v6513992; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v65, 16, v2713993; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)13994; GFX12-FAKE16-NEXT:    v_perm_b32 v14, v14, v53, 0x504010013995; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13996; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v54, v28, v12, vcc_lo13997; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2913998; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)13999; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc_lo14000; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v1114001; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1214002; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14003; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v54, v12, vcc_lo14004; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)14005; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2914006; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v1014007; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14008; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo14009; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2814010; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14011; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo14012; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v65, v6514013; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14014; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v27, v27, v11 :: v_dual_lshlrev_b32 v28, 16, v5414015; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6414016; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14017; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v55, v13, vcc_lo14018; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)14019; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2814020; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v2614021; GFX12-FAKE16-NEXT:    v_perm_b32 v13, v30, v13, 0x504010014022; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14023; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v54, v12, vcc_lo14024; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2914025; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v1114026; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14027; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v10, v26 :: v_dual_lshlrev_b32 v29, 16, v914028; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v2714029; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14030; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v54, v2814031; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14032; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v28, v27, v11, vcc_lo14033; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v55, v5514034; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14035; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v26, v26, v10, vcc_lo14036; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2914037; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v2514038; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14039; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc_lo14040; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1114041; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14042; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v11, v28, v11 :: v_dual_lshlrev_b32 v54, 16, v2614043; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v29, v2914044; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14045; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v25, v25, v9, vcc_lo14046; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2714047; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14048; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo14049; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v2814050; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v1014051; GFX12-FAKE16-NEXT:    v_perm_b32 v12, v34, v12, 0x504010014052; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)14053; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v55, v5414054; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v54, 16, v2514055; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v55, 16, v914056; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14057; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v29, v26, v10, vcc_lo14058; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2714059; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14060; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v28, v11, vcc_lo14061; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1014062; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v2914063; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)14064; GFX12-FAKE16-NEXT:    v_perm_b32 v11, v35, v11, 0x504010014065; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14066; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v29, v10, vcc_lo14067; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v55, v5414068; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14069; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v25, v9, vcc_lo14070; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2614071; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14072; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc_lo14073; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v914074; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14075; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v27, v9, vcc_lo14076; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2814077; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v2314078; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14079; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v29, v10, vcc_lo14080; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2514081; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14082; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v9, v25 :: v_dual_lshlrev_b32 v26, 16, v814083; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v714084; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)14085; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v2614086; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14087; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo14088; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2514089; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2714090; GFX12-FAKE16-NEXT:    v_perm_b32 v10, v36, v10, 0x504010014091; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14092; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v26, 16, v2414093; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)14094; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v29, 16, v714095; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v26, v2614096; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14097; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v24, v8, vcc_lo14098; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v28, v2814099; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14100; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)14101; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v23, v7 :: v_dual_lshlrev_b32 v26, 16, v2414102; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2514103; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v614104; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14105; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v9, v27, v9 :: v_dual_lshlrev_b32 v28, 16, v2314106; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14107; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2514108; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v27, 16, v814109; GFX12-FAKE16-NEXT:    v_perm_b32 v9, v37, v9, 0x504010014110; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14111; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo14112; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)14113; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v27, v2614114; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14115; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v26, v24, v8 :: v_dual_lshlrev_b32 v25, 16, v2214116; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v29, v2814117; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14118; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v27, v23, v7, vcc_lo14119; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)14120; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2514121; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14122; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v22, v6, vcc_lo14123; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v814124; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14125; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v26, v8, vcc_lo14126; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v714127; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14128; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo14129; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2414130; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14131; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo14132; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2314133; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14134; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v23 :: v_dual_lshlrev_b32 v24, 16, v2614135; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2214136; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v28, 16, v614137; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14138; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v28, v2514139; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2714140; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14141; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v22, v6, vcc_lo14142; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2414143; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v514144; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14145; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v26, v8, vcc_lo14146; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v614147; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14148; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc_lo14149; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2514150; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v2114151; GFX12-FAKE16-NEXT:    v_perm_b32 v8, v38, v8, 0x504010014152; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14153; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v27, v7, vcc_lo14154; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2214155; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)14156; GFX12-FAKE16-NEXT:    v_perm_b32 v7, v39, v7, 0x504010014157; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14158; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo14159; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v2414160; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14161; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v21 :: v_dual_lshlrev_b32 v24, 16, v414162; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2314163; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14164; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2214165; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v22, 16, v2014166; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14167; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v23, v6, vcc_lo14168; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v25, v2514169; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v314170; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v514171; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14172; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v21, v21, v5, vcc_lo14173; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v24, v2414174; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)14175; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v2114176; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14177; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo14178; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v2214179; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14180; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v20, v4, vcc_lo14181; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v2314182; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14183; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc_lo14184; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2414185; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v2014186; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v414187; GFX12-FAKE16-NEXT:    v_perm_b32 v6, v48, v6, 0x504010014188; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14189; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v23, v21, v5 :: v_dual_lshlrev_b32 v22, 16, v1914190; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14191; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v22, v2214192; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14193; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v19, v3, vcc_lo14194; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v514195; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14196; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v23, v5, vcc_lo14197; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2414198; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v314199; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v1914200; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14201; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v22, v20, v4, vcc_lo14202; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2114203; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14204; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc_lo14205; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v414206; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14207; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v22, v4 :: v_dual_lshlrev_b32 v21, 16, v2314208; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2414209; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14210; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v24, v19, v3, vcc_lo14211; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)14212; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2114213; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v21, 16, v2214214; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14215; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v23, v5, vcc_lo14216; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2014217; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v49, v5, 0x504010014218; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14219; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo14220; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v314221; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14222; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo14223; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1914224; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14225; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14226; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v19 :: v_dual_lshlrev_b32 v20, 16, v214227; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v1814228; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2014229; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14230; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v2, v18 :: v_dual_lshlrev_b32 v23, 16, v2414231; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)14232; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2314233; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14234; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v24, v3, vcc_lo14235; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v1914236; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v014237; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v31, v3, 0x504010014238; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14239; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v18, v18, v2, vcc_lo14240; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v114241; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)14242; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2014243; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14244; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo14245; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v23, v2314246; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v19, 16, v1714247; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v24, 16, v114248; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14249; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo14250; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)14251; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v19, v1914252; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14253; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v17, v17, v1 :: v_dual_lshlrev_b32 v20, 16, v1614254; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v23, 16, v214255; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v20, v2014256; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14257; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v16, v16, v0 :: v_dual_lshlrev_b32 v19, 16, v1814258; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v20, 16, v1714259; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)14260; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v23, v1914261; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14262; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v19, v18, v2, vcc_lo14263; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v24, v2014264; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14265; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v20, v17, v1, vcc_lo14266; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v214267; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14268; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v19, v2 :: v_dual_lshlrev_b32 v23, 16, v1614269; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v25, 16, v014270; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14271; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v25, v2314272; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14273; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v23, v16, v0, vcc_lo14274; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114275; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14276; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v20, v1, vcc_lo14277; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1814278; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14279; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc_lo14280; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014281; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14282; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v23, v0, vcc_lo14283; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1714284; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14285; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo14286; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v17, 16, v2014287; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1614288; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14289; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo14290; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)14291; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1714292; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v18, 16, v2314293; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14294; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v20, v1 :: v_dual_lshlrev_b32 v16, 16, v1914295; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1814296; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)14297; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v50, v1, 0x504010014298; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14299; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v23, v0, vcc_lo14300; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1614301; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v52, v0, 0x504010014302; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14303; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo14304; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2114305; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)14306; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v32, v2, 0x504010014307; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14308; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v22, v4, vcc_lo14309; GFX12-FAKE16-NEXT:    v_perm_b32 v4, v15, v4, 0x504010014310; GFX12-FAKE16-NEXT:    v_perm_b32 v15, v33, v51, 0x504010014311; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]14312  %result = call <32 x bfloat> @llvm.minimumnum.v32bf16(<32 x bfloat> %x, <32 x bfloat> %y)14313  ret <32 x bfloat> %result14314}14315 14316define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {14317; GFX7-LABEL: v_minimumnum_bf16_no_ieee:14318; GFX7:       ; %bb.0:14319; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14320; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v014321; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v114322; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v114323; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014324; GFX7-NEXT:    v_min_f32_e32 v0, v0, v114325; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014326; GFX7-NEXT:    s_setpc_b64 s[30:31]14327;14328; GFX8-LABEL: v_minimumnum_bf16_no_ieee:14329; GFX8:       ; %bb.0:14330; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14331; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v014332; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214333; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v114334; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14335; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214336; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc14337; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v114338; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v014339; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v3, v214340; GFX8-NEXT:    s_movk_i32 s4, 0x800014341; GFX8-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc14342; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v014343; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc14344; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114345; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14346; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v214347; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114348; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc14349; GFX8-NEXT:    s_setpc_b64 s[30:31]14350;14351; GFX900-LABEL: v_minimumnum_bf16_no_ieee:14352; GFX900:       ; %bb.0:14353; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14354; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v014355; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214356; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v114357; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14358; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314359; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc14360; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v014361; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v114362; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v2, v314363; GFX900-NEXT:    s_movk_i32 s4, 0x800014364; GFX900-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc14365; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v014366; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc14367; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114368; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14369; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v214370; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114371; GFX900-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc14372; GFX900-NEXT:    s_setpc_b64 s[30:31]14373;14374; GFX950-LABEL: v_minimumnum_bf16_no_ieee:14375; GFX950:       ; %bb.0:14376; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14377; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v014378; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214379; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v114380; GFX950-NEXT:    s_movk_i32 s0, 0x800014381; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14382; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314383; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v014384; GFX950-NEXT:    s_nop 014385; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc14386; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v114387; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v2, v314388; GFX950-NEXT:    s_nop 114389; GFX950-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc14390; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v014391; GFX950-NEXT:    s_nop 114392; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc14393; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v114394; GFX950-NEXT:    s_nop 114395; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14396; GFX950-NEXT:    v_lshlrev_b32_e32 v1, 16, v214397; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114398; GFX950-NEXT:    s_nop 114399; GFX950-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc14400; GFX950-NEXT:    s_setpc_b64 s[30:31]14401;14402; GFX10-LABEL: v_minimumnum_bf16_no_ieee:14403; GFX10:       ; %bb.0:14404; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14405; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v014406; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v114407; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214408; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14409; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314410; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v014411; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo14412; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v114413; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v314414; GFX10-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo14415; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014416; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v214417; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo14418; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114419; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14420; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v314421; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo14422; GFX10-NEXT:    s_setpc_b64 s[30:31]14423;14424; GFX11-TRUE16-LABEL: v_minimumnum_bf16_no_ieee:14425; GFX11-TRUE16:       ; %bb.0:14426; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14427; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 014428; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l14429; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l14430; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)14431; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214432; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l14433; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l14434; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo14435; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14436; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214437; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.h14438; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo14439; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)14440; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v1, v214441; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo14442; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h14443; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v1.h, s014444; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14445; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo14446; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l14447; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v214448; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)14449; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo14450; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]14451;14452; GFX11-FAKE16-LABEL: v_minimumnum_bf16_no_ieee:14453; GFX11-FAKE16:       ; %bb.0:14454; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14455; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v014456; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)14457; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214458; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14459; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v114460; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v014461; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)14462; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314463; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo14464; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v114465; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14466; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v314467; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo14468; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v214469; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014470; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo14471; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114472; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14473; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14474; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v314475; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo14476; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]14477;14478; GFX12-TRUE16-LABEL: v_minimumnum_bf16_no_ieee:14479; GFX12-TRUE16:       ; %bb.0:14480; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x014481; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x014482; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x014483; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x014484; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x014485; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 014486; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l14487; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l14488; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)14489; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214490; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v1.l14491; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.l14492; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14493; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v0.l, v0.h, vcc_lo14494; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214495; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)14496; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v1.h14497; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14498; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v1.h, vcc_lo14499; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v1, v214500; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14501; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v2.h, v1.h, vcc_lo14502; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.h14503; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)14504; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)14505; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v1.h, s014506; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14507; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, vcc_lo14508; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l14509; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)14510; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v214511; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14512; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo14513; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]14514;14515; GFX12-FAKE16-LABEL: v_minimumnum_bf16_no_ieee:14516; GFX12-FAKE16:       ; %bb.0:14517; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x014518; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x014519; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x014520; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x014521; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x014522; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v014523; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)14524; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214525; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14526; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14527; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v114528; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v014529; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)14530; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314531; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14532; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo14533; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v114534; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)14535; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v2, v314536; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14537; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v1, v0, vcc_lo14538; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v214539; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014540; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14541; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo14542; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114543; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14544; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)14545; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14546; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v314547; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14548; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo14549; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]14550  %result = call bfloat @llvm.minimumnum.bf16(bfloat %x, bfloat %y)14551  ret bfloat %result14552}14553 14554define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %y) #0 {14555; GFX7-LABEL: v_minimumnum_v2bf16_no_ieee:14556; GFX7:       ; %bb.0:14557; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14558; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v014559; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v214560; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v114561; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v314562; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v314563; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v114564; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v214565; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014566; GFX7-NEXT:    v_min_f32_e32 v1, v1, v314567; GFX7-NEXT:    v_min_f32_e32 v0, v0, v214568; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014569; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v114570; GFX7-NEXT:    s_setpc_b64 s[30:31]14571;14572; GFX8-LABEL: v_minimumnum_v2bf16_no_ieee:14573; GFX8:       ; %bb.0:14574; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14575; GFX8-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014576; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214577; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v114578; GFX8-NEXT:    v_and_b32_e32 v5, 0xffff0000, v114579; GFX8-NEXT:    v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14580; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v514581; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc14582; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v314583; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v214584; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v514585; GFX8-NEXT:    s_movk_i32 s4, 0x800014586; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc14587; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v314588; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc14589; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v214590; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc14591; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v414592; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v314593; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v014594; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc14595; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314596; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v114597; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14598; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314599; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc14600; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v114601; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v014602; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v314603; GFX8-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc14604; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v014605; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc14606; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114607; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14608; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v314609; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114610; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v214611; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc14612; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD14613; GFX8-NEXT:    s_setpc_b64 s[30:31]14614;14615; GFX900-LABEL: v_minimumnum_v2bf16_no_ieee:14616; GFX900:       ; %bb.0:14617; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14618; GFX900-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014619; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214620; GFX900-NEXT:    v_lshrrev_b32_e32 v2, 16, v114621; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v114622; GFX900-NEXT:    v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14623; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v514624; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc14625; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v314626; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v214627; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v514628; GFX900-NEXT:    s_movk_i32 s4, 0x800014629; GFX900-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc14630; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v314631; GFX900-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc14632; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v214633; GFX900-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc14634; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v414635; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v314636; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v014637; GFX900-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc14638; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314639; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v114640; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14641; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314642; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc14643; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v114644; GFX900-NEXT:    v_lshlrev_b32_e32 v4, 16, v014645; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v314646; GFX900-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc14647; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v014648; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc14649; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v114650; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14651; GFX900-NEXT:    v_lshlrev_b32_e32 v1, 16, v314652; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114653; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc14654; GFX900-NEXT:    s_mov_b32 s4, 0x504010014655; GFX900-NEXT:    v_perm_b32 v0, v2, v0, s414656; GFX900-NEXT:    s_setpc_b64 s[30:31]14657;14658; GFX950-LABEL: v_minimumnum_v2bf16_no_ieee:14659; GFX950:       ; %bb.0:14660; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14661; GFX950-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014662; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v2, v214663; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 16, v114664; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v114665; GFX950-NEXT:    v_cndmask_b32_sdwa v3, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14666; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v514667; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v314668; GFX950-NEXT:    s_movk_i32 s0, 0x800014669; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc14670; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v214671; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v514672; GFX950-NEXT:    s_nop 114673; GFX950-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc14674; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v314675; GFX950-NEXT:    s_nop 114676; GFX950-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc14677; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v214678; GFX950-NEXT:    s_nop 114679; GFX950-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc14680; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v414681; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v314682; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v014683; GFX950-NEXT:    s_nop 014684; GFX950-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc14685; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314686; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v114687; GFX950-NEXT:    s_nop 014688; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14689; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v314690; GFX950-NEXT:    v_lshlrev_b32_e32 v4, 16, v014691; GFX950-NEXT:    s_nop 014692; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc14693; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v114694; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v4, v314695; GFX950-NEXT:    s_nop 114696; GFX950-NEXT:    v_cndmask_b32_e32 v3, v1, v0, vcc14697; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v014698; GFX950-NEXT:    s_nop 114699; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc14700; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v114701; GFX950-NEXT:    s_mov_b32 s0, 0x504010014702; GFX950-NEXT:    s_nop 014703; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc14704; GFX950-NEXT:    v_lshlrev_b32_e32 v1, 16, v314705; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v114706; GFX950-NEXT:    s_nop 114707; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc14708; GFX950-NEXT:    v_perm_b32 v0, v2, v0, s014709; GFX950-NEXT:    s_setpc_b64 s[30:31]14710;14711; GFX10-LABEL: v_minimumnum_v2bf16_no_ieee:14712; GFX10:       ; %bb.0:14713; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14714; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014715; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v014716; GFX10-NEXT:    v_and_b32_e32 v3, 0xffff0000, v114717; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v114718; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214719; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v114720; GFX10-NEXT:    v_cndmask_b32_sdwa v6, v0, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD14721; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v414722; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14723; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314724; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v614725; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo14726; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v514727; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v014728; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v214729; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc_lo14730; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v3, v414731; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v114732; GFX10-NEXT:    v_cndmask_b32_e32 v3, v2, v6, vcc_lo14733; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v714734; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v314735; GFX10-NEXT:    v_cndmask_b32_e32 v4, v1, v0, vcc_lo14736; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v614737; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v6, vcc_lo14738; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014739; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v414740; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo14741; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v214742; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc_lo14743; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114744; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14745; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v714746; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v2, vcc_lo14747; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v614748; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo14749; GFX10-NEXT:    v_perm_b32 v0, v1, v0, 0x504010014750; GFX10-NEXT:    s_setpc_b64 s[30:31]14751;14752; GFX11-TRUE16-LABEL: v_minimumnum_v2bf16_no_ieee:14753; GFX11-TRUE16:       ; %bb.0:14754; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14755; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014756; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v114757; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 014758; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v114759; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14760; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214761; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v3, v314762; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)14763; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l14764; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v014765; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v5, v514766; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo14767; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v1.h, v4.h, s014768; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h14769; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)14770; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v214771; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo14772; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314773; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.l14774; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v4.h, s014775; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l14776; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo14777; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)14778; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v414779; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v1.l, v3.h, s114780; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v3.h14781; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)14782; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v3, v414783; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v4.h, v3.h, s014784; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h14785; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14786; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, v3.h, s114787; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v2.h14788; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v4.h, s014789; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v0.l14790; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14791; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, s114792; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v414793; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)14794; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo14795; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s014796; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]14797;14798; GFX11-FAKE16-LABEL: v_minimumnum_v2bf16_no_ieee:14799; GFX11-FAKE16:       ; %bb.0:14800; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14801; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014802; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v114803; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v014804; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)14805; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214806; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v014807; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v114808; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14809; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v514810; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14811; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v614812; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v2, vcc_lo14813; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14814; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v314815; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v114816; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v414817; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v214818; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)14819; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v514820; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v114821; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v014822; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)14823; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v714824; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v414825; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v1, v0, vcc_lo14826; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v214827; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)14828; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v514829; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014830; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo14831; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v314832; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo14833; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114834; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)14835; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14836; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v614837; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc_lo14838; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v714839; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)14840; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo14841; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x504010014842; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]14843;14844; GFX12-TRUE16-LABEL: v_minimumnum_v2bf16_no_ieee:14845; GFX12-TRUE16:       ; %bb.0:14846; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x014847; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x014848; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x014849; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x014850; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x014851; GFX12-TRUE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014852; GFX12-TRUE16-NEXT:    v_and_b32_e32 v3, 0xffff0000, v114853; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 014854; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v114855; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)14856; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214857; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v3, v314858; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)14859; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v4.l14860; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v014861; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v5, v514862; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14863; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v0.h, v1.h, vcc_lo14864; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)14865; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)14866; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v1.h, v4.h, s014867; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h14868; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v214869; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14870; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v2.h, v4.h, vcc_lo14871; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v3, v314872; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v4.l14873; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)14874; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)14875; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v4.h, s014876; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v2.l14877; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14878; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.h, v0.l, v1.l, vcc_lo14879; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v414880; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14881; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v1.l, v3.h, s114882; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v3.h14883; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v3, v414884; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)14885; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)14886; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v4.h, v3.h, s014887; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v4.h14888; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v0.l, v3.h, s114889; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v2.h14890; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)14891; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)14892; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v4.h, s014893; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v0.l14894; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.h, v2.h, s114895; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)14896; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v414897; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)14898; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v2.l, v0.h, vcc_lo14899; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)14900; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)14901; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v1.l, s014902; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]14903;14904; GFX12-FAKE16-LABEL: v_minimumnum_v2bf16_no_ieee:14905; GFX12-FAKE16:       ; %bb.0:14906; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x014907; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x014908; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x014909; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x014910; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x014911; GFX12-FAKE16-NEXT:    v_and_b32_e32 v2, 0xffff0000, v014912; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v114913; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v014914; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)14915; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v2, v214916; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14917; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v3 :: v_dual_lshlrev_b32 v5, 16, v014918; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v114919; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)14920; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v514921; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14922; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14923; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v614924; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14925; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v2, vcc_lo14926; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)14927; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v314928; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v4, 16, v114929; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v414930; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14931; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v1, v0 :: v_dual_lshlrev_b32 v4, 16, v214932; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)14933; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v4, v514934; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14935; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v3, v2 :: v_dual_lshlrev_b32 v7, 16, v114936; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v014937; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)14938; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v714939; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v6, 16, v414940; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14941; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v1, v0, vcc_lo14942; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v214943; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14944; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)14945; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v2, v4, v2 :: v_dual_lshlrev_b32 v7, 16, v514946; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v014947; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14948; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo14949; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v314950; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14951; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo14952; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v114953; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14954; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo14955; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v614956; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14957; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc_lo14958; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v714959; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)14960; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo14961; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)14962; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x504010014963; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]14964  %result = call <2 x bfloat> @llvm.minimumnum.v2bf16(<2 x bfloat> %x, <2 x bfloat> %y)14965  ret <2 x bfloat> %result14966}14967 14968define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %y) #0 {14969; GFX7-LABEL: v_minimumnum_v3bf16_no_ieee:14970; GFX7:       ; %bb.0:14971; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14972; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v014973; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v314974; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v114975; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v414976; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v214977; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v514978; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v514979; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v214980; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v414981; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v114982; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v314983; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014984; GFX7-NEXT:    v_min_f32_e32 v2, v2, v514985; GFX7-NEXT:    v_min_f32_e32 v1, v1, v414986; GFX7-NEXT:    v_min_f32_e32 v0, v0, v314987; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v214988; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v014989; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v114990; GFX7-NEXT:    s_setpc_b64 s[30:31]14991;14992; GFX8-LABEL: v_minimumnum_v3bf16_no_ieee:14993; GFX8:       ; %bb.0:14994; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14995; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v014996; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v4, v414997; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v214998; GFX8-NEXT:    v_and_b32_e32 v7, 0xffff0000, v214999; GFX8-NEXT:    v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15000; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v715001; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc15002; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v515003; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v415004; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v715005; GFX8-NEXT:    s_movk_i32 s4, 0x800015006; GFX8-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc15007; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v515008; GFX8-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc15009; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v415010; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc15011; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v615012; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v515013; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v115014; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc15015; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515016; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v315017; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15018; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515019; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc15020; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v315021; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v115022; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v515023; GFX8-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc15024; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v115025; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc15026; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v315027; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15028; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v515029; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v315030; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v015031; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc15032; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315033; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v215034; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15035; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315036; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc15037; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v215038; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v015039; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v315040; GFX8-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc15041; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v015042; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15043; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v215044; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15045; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v315046; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v215047; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15048; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v415049; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15050; GFX8-NEXT:    s_setpc_b64 s[30:31]15051;15052; GFX900-LABEL: v_minimumnum_v3bf16_no_ieee:15053; GFX900:       ; %bb.0:15054; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15055; GFX900-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015056; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v4, v415057; GFX900-NEXT:    v_lshrrev_b32_e32 v4, 16, v215058; GFX900-NEXT:    v_and_b32_e32 v7, 0xffff0000, v215059; GFX900-NEXT:    v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15060; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v715061; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc15062; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v515063; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v415064; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v715065; GFX900-NEXT:    s_movk_i32 s4, 0x800015066; GFX900-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc15067; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v515068; GFX900-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc15069; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v415070; GFX900-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc15071; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v615072; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v515073; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v115074; GFX900-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc15075; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515076; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v315077; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15078; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515079; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc15080; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v315081; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v115082; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v515083; GFX900-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc15084; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v115085; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc15086; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v315087; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15088; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v515089; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v315090; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v015091; GFX900-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc15092; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315093; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v215094; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15095; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315096; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc15097; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v215098; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v015099; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v315100; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc15101; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v015102; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15103; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v215104; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15105; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v315106; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v215107; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15108; GFX900-NEXT:    s_mov_b32 s4, 0x504010015109; GFX900-NEXT:    v_perm_b32 v0, v4, v0, s415110; GFX900-NEXT:    s_setpc_b64 s[30:31]15111;15112; GFX950-LABEL: v_minimumnum_v3bf16_no_ieee:15113; GFX950:       ; %bb.0:15114; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15115; GFX950-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015116; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v4, v415117; GFX950-NEXT:    v_lshrrev_b32_e32 v4, 16, v215118; GFX950-NEXT:    v_and_b32_e32 v7, 0xffff0000, v215119; GFX950-NEXT:    v_cndmask_b32_sdwa v5, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15120; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v715121; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v515122; GFX950-NEXT:    s_movk_i32 s0, 0x800015123; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc15124; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v415125; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v715126; GFX950-NEXT:    s_nop 115127; GFX950-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc15128; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v515129; GFX950-NEXT:    s_nop 115130; GFX950-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc15131; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v415132; GFX950-NEXT:    s_nop 115133; GFX950-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc15134; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v615135; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v515136; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v115137; GFX950-NEXT:    s_nop 015138; GFX950-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc15139; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515140; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v315141; GFX950-NEXT:    s_nop 015142; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15143; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515144; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v115145; GFX950-NEXT:    s_nop 015146; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc15147; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v315148; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v515149; GFX950-NEXT:    s_nop 115150; GFX950-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc15151; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v115152; GFX950-NEXT:    s_nop 115153; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc15154; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v315155; GFX950-NEXT:    s_nop 115156; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15157; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v515158; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v315159; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v015160; GFX950-NEXT:    s_nop 015161; GFX950-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc15162; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315163; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v215164; GFX950-NEXT:    s_nop 015165; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15166; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315167; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v015168; GFX950-NEXT:    s_nop 015169; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc15170; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v215171; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v5, v315172; GFX950-NEXT:    s_nop 115173; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc15174; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v015175; GFX950-NEXT:    s_nop 115176; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15177; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v215178; GFX950-NEXT:    s_mov_b32 s0, 0x504010015179; GFX950-NEXT:    s_nop 015180; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15181; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v315182; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v215183; GFX950-NEXT:    s_nop 115184; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15185; GFX950-NEXT:    v_perm_b32 v0, v4, v0, s015186; GFX950-NEXT:    s_setpc_b64 s[30:31]15187;15188; GFX10-LABEL: v_minimumnum_v3bf16_no_ieee:15189; GFX10:       ; %bb.0:15190; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15191; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015192; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v215193; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v015194; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v215195; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v215196; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415197; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v115198; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v315199; GFX10-NEXT:    v_cndmask_b32_sdwa v10, v0, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15200; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v815201; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo15202; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415203; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15204; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v615205; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v10, vcc_lo15206; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v915207; GFX10-NEXT:    v_lshlrev_b32_e32 v5, 16, v1015208; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v115209; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v415210; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo15211; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v715212; GFX10-NEXT:    v_lshlrev_b32_e32 v7, 16, v015213; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v215214; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo15215; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v615216; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v315217; GFX10-NEXT:    v_cndmask_b32_e32 v5, v4, v10, vcc_lo15218; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v815219; GFX10-NEXT:    v_cndmask_b32_e32 v6, v2, v0, vcc_lo15220; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v1115221; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v515222; GFX10-NEXT:    v_cndmask_b32_e32 v7, v3, v1, vcc_lo15223; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1015224; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v10, vcc_lo15225; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v015226; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo15227; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v415228; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc_lo15229; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v215230; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v615231; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo15232; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v915233; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v4, vcc_lo15234; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115235; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 16, v715236; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo15237; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v815238; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo15239; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v315240; GFX10-NEXT:    v_perm_b32 v0, v2, v0, 0x504010015241; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15242; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v415243; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo15244; GFX10-NEXT:    s_setpc_b64 s[30:31]15245;15246; GFX11-TRUE16-LABEL: v_minimumnum_v3bf16_no_ieee:15247; GFX11-TRUE16:       ; %bb.0:15248; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15249; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015250; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v215251; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 015252; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v315253; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15254; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415255; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v515256; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)15257; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v6.l15258; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v115259; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v7, v715260; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo15261; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v215262; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.h, v6.h, s015263; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15264; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15265; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v7, v715266; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v415267; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo15268; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v515269; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l15270; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)15271; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v6.h, s015272; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l15273; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo15274; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v615275; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)15276; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v5.h, s115277; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v5.h15278; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v015279; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v5, v615280; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15281; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v5.h, s015282; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15283; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v5.h, s115284; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v3, v315285; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15286; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s015287; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l15288; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s115289; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l15290; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15291; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v615292; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s215293; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v0.h15294; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15295; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s015296; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v0, v615297; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15298; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s115299; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v6.h15300; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s215301; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v4.h15302; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15303; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s115304; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l15305; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v4.h, s215306; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15307; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v615308; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo15309; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)15310; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s115311; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]15312;15313; GFX11-FAKE16-LABEL: v_minimumnum_v3bf16_no_ieee:15314; GFX11-FAKE16:       ; %bb.0:15315; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15316; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015317; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v215318; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v015319; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v015320; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)15321; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415322; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v215323; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)15324; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v715325; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v115326; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v815327; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v315328; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v215329; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)15330; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v615331; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15332; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v715333; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v415334; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo15335; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v515336; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)15337; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v1015338; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v4, vcc_lo15339; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v915340; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v115341; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v615342; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v415343; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v215344; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo15345; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v515346; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)15347; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v015348; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v815349; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v315350; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc_lo15351; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1015352; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo15353; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v015354; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)15355; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo15356; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v715357; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v515358; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc_lo15359; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v215360; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo15361; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115362; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)15363; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v615364; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v715365; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo15366; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v315367; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)15368; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x504010015369; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15370; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v215371; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc_lo15372; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]15373;15374; GFX12-TRUE16-LABEL: v_minimumnum_v3bf16_no_ieee:15375; GFX12-TRUE16:       ; %bb.0:15376; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x015377; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x015378; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x015379; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x015380; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x015381; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015382; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v215383; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 015384; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v315385; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)15386; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415387; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v515388; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)15389; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v6.l15390; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v5, 16, v115391; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v7, v715392; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)15393; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo15394; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v215395; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15396; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15397; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v2.h, v6.h, s015398; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15399; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v7, v715400; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)15401; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v415402; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)15403; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v4.h, v6.h, vcc_lo15404; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v5, v515405; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l15406; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15407; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)15408; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v6.h, s015409; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l15410; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)15411; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v1.l, v3.l, vcc_lo15412; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v615413; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)15414; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v5.h, s115415; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v5.h15416; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v015417; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v5, v615418; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15419; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15420; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v5.h, s015421; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15422; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v5.h, s115423; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s1, v3, v315424; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15425; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15426; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s015427; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l15428; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s115429; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l15430; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15431; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v615432; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s215433; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v0.h15434; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15435; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15436; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s015437; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s1, v0, v615438; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15439; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15440; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s115441; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s1, 0x8000, v6.h15442; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s215443; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v4.h15444; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15445; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15446; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s115447; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l15448; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.h, v4.h, s215449; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)15450; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v615451; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)15452; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.l, v0.h, vcc_lo15453; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)15454; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)15455; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s115456; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]15457;15458; GFX12-FAKE16-LABEL: v_minimumnum_v3bf16_no_ieee:15459; GFX12-FAKE16:       ; %bb.0:15460; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x015461; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x015462; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x015463; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x015464; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x015465; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015466; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v215467; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v015468; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v015469; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)15470; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415471; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15472; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v215473; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15474; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v715475; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15476; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v4 :: v_dual_lshlrev_b32 v6, 16, v115477; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v815478; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15479; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v9, 16, v315480; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v215481; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v615482; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15483; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15484; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)15485; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v715486; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v415487; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15488; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo15489; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v515490; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v1015491; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15492; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v4, vcc_lo15493; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v915494; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v115495; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15496; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)15497; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v3, v3, v1 :: v_dual_lshlrev_b32 v10, 16, v615498; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v415499; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v215500; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15501; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo15502; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v515503; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15504; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)15505; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v7, 16, v015506; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v7, v815507; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v315508; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15509; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v2, v0, vcc_lo15510; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1015511; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15512; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo15513; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v015514; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15515; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo15516; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v715517; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v7, 16, v515518; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15519; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc_lo15520; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v215521; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15522; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo15523; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115524; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15525; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v6, v1 :: v_dual_lshlrev_b32 v2, 16, v615526; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v715527; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15528; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc_lo15529; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v315530; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)15531; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x504010015532; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15533; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15534; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v215535; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)15536; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc_lo15537; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]15538  %result = call <3 x bfloat> @llvm.minimumnum.v3bf16(<3 x bfloat> %x, <3 x bfloat> %y)15539  ret <3 x bfloat> %result15540}15541 15542define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %y) #0 {15543; GFX7-LABEL: v_minimumnum_v4bf16_no_ieee:15544; GFX7:       ; %bb.0:15545; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15546; GFX7-NEXT:    v_mul_f32_e32 v0, 1.0, v015547; GFX7-NEXT:    v_mul_f32_e32 v4, 1.0, v415548; GFX7-NEXT:    v_mul_f32_e32 v1, 1.0, v115549; GFX7-NEXT:    v_mul_f32_e32 v5, 1.0, v515550; GFX7-NEXT:    v_mul_f32_e32 v2, 1.0, v215551; GFX7-NEXT:    v_mul_f32_e32 v6, 1.0, v615552; GFX7-NEXT:    v_mul_f32_e32 v3, 1.0, v315553; GFX7-NEXT:    v_mul_f32_e32 v7, 1.0, v715554; GFX7-NEXT:    v_and_b32_e32 v7, 0xffff0000, v715555; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v315556; GFX7-NEXT:    v_and_b32_e32 v6, 0xffff0000, v615557; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v215558; GFX7-NEXT:    v_and_b32_e32 v5, 0xffff0000, v515559; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v115560; GFX7-NEXT:    v_and_b32_e32 v4, 0xffff0000, v415561; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v015562; GFX7-NEXT:    v_min_f32_e32 v3, v3, v715563; GFX7-NEXT:    v_min_f32_e32 v2, v2, v615564; GFX7-NEXT:    v_min_f32_e32 v1, v1, v515565; GFX7-NEXT:    v_min_f32_e32 v0, v0, v415566; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff0000, v015567; GFX7-NEXT:    v_and_b32_e32 v1, 0xffff0000, v115568; GFX7-NEXT:    v_and_b32_e32 v2, 0xffff0000, v215569; GFX7-NEXT:    v_and_b32_e32 v3, 0xffff0000, v315570; GFX7-NEXT:    s_setpc_b64 s[30:31]15571;15572; GFX8-LABEL: v_minimumnum_v4bf16_no_ieee:15573; GFX8:       ; %bb.0:15574; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15575; GFX8-NEXT:    v_and_b32_e32 v4, 0xffff0000, v115576; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v4, v415577; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v315578; GFX8-NEXT:    v_and_b32_e32 v7, 0xffff0000, v315579; GFX8-NEXT:    v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15580; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v7, v715581; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc15582; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v515583; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v415584; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v715585; GFX8-NEXT:    s_movk_i32 s4, 0x800015586; GFX8-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc15587; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v515588; GFX8-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc15589; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v415590; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc15591; GFX8-NEXT:    v_lshlrev_b32_e32 v5, 16, v615592; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v515593; GFX8-NEXT:    v_and_b32_e32 v5, 0xffff0000, v015594; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc15595; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v215596; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v015597; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515598; GFX8-NEXT:    v_and_b32_e32 v8, 0xffff0000, v215599; GFX8-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc15600; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v8, v815601; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc15602; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v515603; GFX8-NEXT:    v_lshlrev_b32_e32 v8, 16, v615604; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v815605; GFX8-NEXT:    v_cndmask_b32_e32 v7, v6, v5, vcc15606; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v515607; GFX8-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc15608; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v615609; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc15610; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v715611; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v615612; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v115613; GFX8-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc15614; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v615615; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v315616; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15617; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v6, v615618; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc15619; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v315620; GFX8-NEXT:    v_lshlrev_b32_e32 v7, 16, v115621; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v615622; GFX8-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc15623; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v115624; GFX8-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc15625; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v315626; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15627; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v615628; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v315629; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v015630; GFX8-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc15631; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315632; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v215633; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15634; GFX8-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315635; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc15636; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v215637; GFX8-NEXT:    v_lshlrev_b32_e32 v6, 16, v015638; GFX8-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v315639; GFX8-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc15640; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v015641; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15642; GFX8-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v215643; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15644; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v315645; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v215646; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15647; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v515648; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15649; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v415650; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD15651; GFX8-NEXT:    s_setpc_b64 s[30:31]15652;15653; GFX900-LABEL: v_minimumnum_v4bf16_no_ieee:15654; GFX900:       ; %bb.0:15655; GFX900-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15656; GFX900-NEXT:    v_and_b32_e32 v4, 0xffff0000, v115657; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v4, v415658; GFX900-NEXT:    v_lshrrev_b32_e32 v4, 16, v315659; GFX900-NEXT:    v_and_b32_e32 v7, 0xffff0000, v315660; GFX900-NEXT:    v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15661; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v7, v715662; GFX900-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc15663; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v515664; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v415665; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v715666; GFX900-NEXT:    s_movk_i32 s4, 0x800015667; GFX900-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc15668; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v515669; GFX900-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc15670; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v415671; GFX900-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc15672; GFX900-NEXT:    v_lshlrev_b32_e32 v5, 16, v615673; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v515674; GFX900-NEXT:    v_and_b32_e32 v5, 0xffff0000, v015675; GFX900-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc15676; GFX900-NEXT:    v_lshrrev_b32_e32 v6, 16, v215677; GFX900-NEXT:    v_lshrrev_b32_e32 v7, 16, v015678; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515679; GFX900-NEXT:    v_and_b32_e32 v8, 0xffff0000, v215680; GFX900-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc15681; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v8, v815682; GFX900-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc15683; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v515684; GFX900-NEXT:    v_lshlrev_b32_e32 v8, 16, v615685; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v815686; GFX900-NEXT:    v_cndmask_b32_e32 v7, v6, v5, vcc15687; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v515688; GFX900-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc15689; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v615690; GFX900-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc15691; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v715692; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v615693; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v115694; GFX900-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc15695; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v615696; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v315697; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15698; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v6, v615699; GFX900-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc15700; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v315701; GFX900-NEXT:    v_lshlrev_b32_e32 v7, 16, v115702; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v615703; GFX900-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc15704; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v115705; GFX900-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc15706; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v315707; GFX900-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15708; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v615709; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v315710; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v015711; GFX900-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc15712; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315713; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v215714; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15715; GFX900-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315716; GFX900-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc15717; GFX900-NEXT:    v_lshlrev_b32_e32 v3, 16, v215718; GFX900-NEXT:    v_lshlrev_b32_e32 v6, 16, v015719; GFX900-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v315720; GFX900-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc15721; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v015722; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15723; GFX900-NEXT:    v_cmp_eq_u16_e32 vcc, s4, v215724; GFX900-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15725; GFX900-NEXT:    v_lshlrev_b32_e32 v2, 16, v315726; GFX900-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v215727; GFX900-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15728; GFX900-NEXT:    s_mov_b32 s4, 0x504010015729; GFX900-NEXT:    v_perm_b32 v0, v5, v0, s415730; GFX900-NEXT:    v_perm_b32 v1, v4, v1, s415731; GFX900-NEXT:    s_setpc_b64 s[30:31]15732;15733; GFX950-LABEL: v_minimumnum_v4bf16_no_ieee:15734; GFX950:       ; %bb.0:15735; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15736; GFX950-NEXT:    v_and_b32_e32 v4, 0xffff0000, v115737; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v4, v415738; GFX950-NEXT:    v_lshrrev_b32_e32 v4, 16, v315739; GFX950-NEXT:    v_and_b32_e32 v7, 0xffff0000, v315740; GFX950-NEXT:    v_cndmask_b32_sdwa v5, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15741; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v7, v715742; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v515743; GFX950-NEXT:    s_movk_i32 s0, 0x800015744; GFX950-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc15745; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v415746; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v715747; GFX950-NEXT:    v_lshrrev_b32_e32 v7, 16, v015748; GFX950-NEXT:    v_and_b32_e32 v8, 0xffff0000, v215749; GFX950-NEXT:    v_cndmask_b32_e32 v6, v4, v5, vcc15750; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v515751; GFX950-NEXT:    s_nop 115752; GFX950-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc15753; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v415754; GFX950-NEXT:    s_nop 115755; GFX950-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc15756; GFX950-NEXT:    v_lshlrev_b32_e32 v5, 16, v615757; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v515758; GFX950-NEXT:    v_and_b32_e32 v5, 0xffff0000, v015759; GFX950-NEXT:    s_nop 015760; GFX950-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc15761; GFX950-NEXT:    v_lshrrev_b32_e32 v6, 16, v215762; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v5, v515763; GFX950-NEXT:    s_nop 115764; GFX950-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc15765; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v8, v815766; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v515767; GFX950-NEXT:    s_nop 015768; GFX950-NEXT:    v_cndmask_b32_e32 v6, v6, v5, vcc15769; GFX950-NEXT:    v_lshlrev_b32_e32 v8, 16, v615770; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v815771; GFX950-NEXT:    s_nop 115772; GFX950-NEXT:    v_cndmask_b32_e32 v7, v6, v5, vcc15773; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v515774; GFX950-NEXT:    s_nop 115775; GFX950-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc15776; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v615777; GFX950-NEXT:    s_nop 115778; GFX950-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc15779; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v715780; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v615781; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v115782; GFX950-NEXT:    s_nop 015783; GFX950-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc15784; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v615785; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v315786; GFX950-NEXT:    s_nop 015787; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15788; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v6, v615789; GFX950-NEXT:    v_lshlrev_b32_e32 v7, 16, v115790; GFX950-NEXT:    s_nop 015791; GFX950-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc15792; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v315793; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v7, v615794; GFX950-NEXT:    s_nop 115795; GFX950-NEXT:    v_cndmask_b32_e32 v6, v3, v1, vcc15796; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v115797; GFX950-NEXT:    s_nop 115798; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc15799; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v315800; GFX950-NEXT:    s_nop 115801; GFX950-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc15802; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v615803; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v315804; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v015805; GFX950-NEXT:    s_nop 015806; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc15807; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315808; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v215809; GFX950-NEXT:    s_nop 015810; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15811; GFX950-NEXT:    v_cmp_u_f32_e32 vcc, v3, v315812; GFX950-NEXT:    v_lshlrev_b32_e32 v6, 16, v015813; GFX950-NEXT:    s_nop 015814; GFX950-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc15815; GFX950-NEXT:    v_lshlrev_b32_e32 v3, 16, v215816; GFX950-NEXT:    v_cmp_lt_f32_e32 vcc, v6, v315817; GFX950-NEXT:    s_nop 115818; GFX950-NEXT:    v_cndmask_b32_e32 v3, v2, v0, vcc15819; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v015820; GFX950-NEXT:    s_nop 115821; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15822; GFX950-NEXT:    v_cmp_eq_u16_e32 vcc, s0, v215823; GFX950-NEXT:    s_mov_b32 s0, 0x504010015824; GFX950-NEXT:    v_perm_b32 v1, v4, v1, s015825; GFX950-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc15826; GFX950-NEXT:    v_lshlrev_b32_e32 v2, 16, v315827; GFX950-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v215828; GFX950-NEXT:    s_nop 115829; GFX950-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc15830; GFX950-NEXT:    v_perm_b32 v0, v5, v0, s015831; GFX950-NEXT:    s_setpc_b64 s[30:31]15832;15833; GFX10-LABEL: v_minimumnum_v4bf16_no_ieee:15834; GFX10:       ; %bb.0:15835; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15836; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v115837; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v315838; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff0000, v315839; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v215840; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v015841; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415842; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff0000, v015843; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v115844; GFX10-NEXT:    v_lshlrev_b32_e32 v13, 16, v015845; GFX10-NEXT:    v_and_b32_e32 v9, 0xffff0000, v215846; GFX10-NEXT:    v_cndmask_b32_sdwa v10, v1, v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD15847; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v615848; GFX10-NEXT:    v_lshlrev_b32_e32 v12, 16, v315849; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v215850; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v10, vcc_lo15851; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415852; GFX10-NEXT:    v_lshlrev_b32_e32 v14, 16, v515853; GFX10-NEXT:    v_cndmask_b32_e32 v4, v8, v7, vcc_lo15854; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v11, v1115855; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v1015856; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v415857; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15858; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v1315859; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo15860; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v1415861; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v10, vcc_lo15862; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v915863; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v4, vcc_lo15864; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v1215865; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo15866; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1015867; GFX10-NEXT:    v_cndmask_b32_e32 v9, v8, v10, vcc_lo15868; GFX10-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v615869; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v715870; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v815871; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo15872; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v515873; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo15874; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v615875; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v315876; GFX10-NEXT:    v_lshlrev_b32_e32 v11, 16, v015877; GFX10-NEXT:    v_cndmask_b32_e32 v6, v7, v4, vcc_lo15878; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v1015879; GFX10-NEXT:    v_lshlrev_b32_e32 v10, 16, v215880; GFX10-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo15881; GFX10-NEXT:    v_lshlrev_b32_e32 v8, 16, v115882; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v415883; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo15884; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v8, v915885; GFX10-NEXT:    v_lshlrev_b32_e32 v9, 16, v615886; GFX10-NEXT:    v_cndmask_b32_e32 v8, v3, v1, vcc_lo15887; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v715888; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc_lo15889; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v1015890; GFX10-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo15891; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v115892; GFX10-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo15893; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v015894; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo15895; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v315896; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo15897; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v215898; GFX10-NEXT:    v_lshlrev_b32_e32 v3, 16, v715899; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo15900; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v915901; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v815902; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo15903; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v315904; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo15905; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v215906; GFX10-NEXT:    v_perm_b32 v0, v4, v0, 0x504010015907; GFX10-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo15908; GFX10-NEXT:    v_perm_b32 v1, v5, v1, 0x504010015909; GFX10-NEXT:    s_setpc_b64 s[30:31]15910;15911; GFX11-TRUE16-LABEL: v_minimumnum_v4bf16_no_ieee:15912; GFX11-TRUE16:       ; %bb.0:15913; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15914; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v115915; GFX11-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v315916; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 015917; GFX11-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v015918; GFX11-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v215919; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v415920; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v515921; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l15922; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v315923; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo15924; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15925; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v9, v915926; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v215927; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.h, v6.h, s015928; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15929; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15930; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v9, v915931; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v515932; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo15933; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v715934; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l15935; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)15936; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v6.h, s015937; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l15938; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v8, v815939; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v115940; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v615941; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo15942; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15943; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.h, v2.h, v6.h, s015944; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15945; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v715946; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v7.h15947; GFX11-TRUE16-NEXT:    v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo15948; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v815949; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l15950; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)15951; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.l, v6.h, s015952; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v5.l15953; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo15954; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v615955; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)15956; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v8.h, s215957; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v8.h15958; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v015959; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v8, v615960; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15961; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v8.h, s015962; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h15963; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v8.h, s215964; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v3, v315965; GFX11-TRUE16-NEXT:    v_cndmask_b16 v3.l, v1.h, v7.h, s415966; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)15967; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s015968; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l15969; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s215970; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l15971; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15972; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v615973; GFX11-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s315974; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v0.h15975; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)15976; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s015977; GFX11-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v615978; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)15979; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s215980; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v6.h15981; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s315982; GFX11-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v5.h15983; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)15984; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s215985; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l15986; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v5.h, s315987; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)15988; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v615989; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v0.h, s115990; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo15991; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)15992; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s215993; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]15994;15995; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee:15996; GFX11-FAKE16:       ; %bb.0:15997; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)15998; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v115999; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v316000; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v116001; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v016002; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v116003; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v416004; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)16005; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v316006; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v716007; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v216008; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v016009; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)16010; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v416011; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc_lo16012; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v516013; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)16014; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v1116015; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v216016; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v616017; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc_lo16018; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v1216019; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo16020; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v416021; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v316022; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v916023; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v016024; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v516025; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v216026; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)16027; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v716028; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v1416029; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo16030; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v1016031; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)16032; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v016033; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v816034; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v616035; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v1316036; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo16037; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)16038; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v916039; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v116040; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc_lo16041; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v1516042; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v316043; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo16044; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v616045; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc_lo16046; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)16047; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v816048; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v516049; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v3, v1, vcc_lo16050; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v216051; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v716052; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc_lo16053; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)16054; GFX11-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v1016055; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo16056; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v116057; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo16058; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v016059; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo16060; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v316061; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)16062; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo16063; GFX11-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v216064; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v716065; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v916066; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v816067; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)16068; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v316069; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo16070; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16071; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v216072; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x504010016073; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo16074; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)16075; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x504010016076; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]16077;16078; GFX12-TRUE16-LABEL: v_minimumnum_v4bf16_no_ieee:16079; GFX12-TRUE16:       ; %bb.0:16080; GFX12-TRUE16-NEXT:    s_wait_loadcnt_dscnt 0x016081; GFX12-TRUE16-NEXT:    s_wait_expcnt 0x016082; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x016083; GFX12-TRUE16-NEXT:    s_wait_bvhcnt 0x016084; GFX12-TRUE16-NEXT:    s_wait_kmcnt 0x016085; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v116086; GFX12-TRUE16-NEXT:    v_and_b32_e32 v5, 0xffff0000, v316087; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.l, 016088; GFX12-TRUE16-NEXT:    v_and_b32_e32 v7, 0xffff0000, v016089; GFX12-TRUE16-NEXT:    v_and_b32_e32 v8, 0xffff0000, v216090; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v416091; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v5, v516092; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v6.l16093; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v316094; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)16095; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v1.h, v3.h, vcc_lo16096; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)16097; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v9, v916098; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v216099; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16100; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.h, v3.h, v6.h, s016101; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h16102; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)16103; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s3, v9, v916104; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v516105; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)16106; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.l, v5.h, v6.h, vcc_lo16107; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v716108; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v6.l16109; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16110; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)16111; GFX12-TRUE16-NEXT:    v_cndmask_b16 v4.h, v4.l, v6.h, s016112; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v4.l16113; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s0, v8, v816114; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v116115; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s1, 0, v616116; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)16117; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v0.h, v2.h, vcc_lo16118; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16119; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)16120; GFX12-TRUE16-NEXT:    v_cndmask_b16 v7.h, v2.h, v6.h, s016121; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h16122; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v6, v716123; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s4, 0x8000, v7.h16124; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)16125; GFX12-TRUE16-NEXT:    v_cndmask_b16 v5.l, v7.h, v6.h, vcc_lo16126; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v8, v816127; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v6.l16128; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16129; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)16130; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v5.l, v6.h, s016131; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v5.l16132; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)16133; GFX12-TRUE16-NEXT:    v_cndmask_b16 v8.h, v1.l, v3.l, vcc_lo16134; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v616135; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)16136; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v3.l, v8.h, s216137; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v8.h16138; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v016139; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s0, v8, v616140; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16141; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)16142; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v6.h, v8.h, s016143; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s0, 0x8000, v6.h16144; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v1.l, v8.h, s216145; GFX12-TRUE16-NEXT:    v_cmp_u_f32_e64 s2, v3, v316146; GFX12-TRUE16-NEXT:    v_cndmask_b16 v3.l, v1.h, v7.h, s416147; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16148; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)16149; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.h, v0.h, v6.h, s016150; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v1.l16151; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v2.l, s216152; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v6.l16153; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s0, 0, v616154; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)16155; GFX12-TRUE16-NEXT:    v_cndmask_b16 v6.h, v2.l, v0.h, s316156; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v0.h16157; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16158; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.l, v1.l, v2.h, s016159; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)16160; GFX12-TRUE16-NEXT:    v_cmp_lt_f32_e64 s2, v0, v616161; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16162; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v6.h, v0.h, s216163; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s2, 0x8000, v6.h16164; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)16165; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v0.l, v0.h, s316166; GFX12-TRUE16-NEXT:    v_cmp_eq_u16_e64 s3, 0x8000, v5.h16167; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16168; GFX12-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.h, v6.h, s216169; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v0.l16170; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)16171; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v4.h, v5.h, s316172; GFX12-TRUE16-NEXT:    v_cmp_eq_f32_e64 s2, 0, v616173; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)16174; GFX12-TRUE16-NEXT:    v_cndmask_b16 v1.h, v4.l, v0.h, s116175; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)16176; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.h, v5.l, v3.l, vcc_lo16177; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_sdst(0)16178; GFX12-TRUE16-NEXT:    v_cndmask_b16 v0.l, v0.l, v2.l, s216179; GFX12-TRUE16-NEXT:    s_setpc_b64 s[30:31]16180;16181; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16_no_ieee:16182; GFX12-FAKE16:       ; %bb.0:16183; GFX12-FAKE16-NEXT:    s_wait_loadcnt_dscnt 0x016184; GFX12-FAKE16-NEXT:    s_wait_expcnt 0x016185; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x016186; GFX12-FAKE16-NEXT:    s_wait_bvhcnt 0x016187; GFX12-FAKE16-NEXT:    s_wait_kmcnt 0x016188; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff0000, v116189; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v316190; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v116191; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v016192; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v12, 16, v116193; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v4, v416194; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16195; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v6, v5 :: v_dual_and_b32 v7, 0xffff0000, v316196; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)16197; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v7, v716198; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v216199; GFX12-FAKE16-NEXT:    v_and_b32_e32 v6, 0xffff0000, v016200; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v416201; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16202; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v4, vcc_lo16203; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)16204; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v516205; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v10, v1116206; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16207; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v10, v5, v4 :: v_dual_and_b32 v9, 0xffff0000, v216208; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v6, v616209; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16210; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v8, v7, vcc_lo16211; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v12, v1216212; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16213; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo16214; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v416215; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16216; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v13, 16, v316217; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v9, v916218; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16219; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v7, v7, v6 :: v_dual_lshlrev_b32 v14, 16, v016220; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v516221; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v15, 16, v216222; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16223; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)16224; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v4, v5 :: v_dual_lshlrev_b32 v9, 16, v716225; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v14, v1416226; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16227; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo16228; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v1016229; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v11, 16, v016230; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)16231; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v816232; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16233; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v4, v10, v4 :: v_dual_lshlrev_b32 v5, 16, v616234; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v13, v1316235; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16236; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo16237; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)16238; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v5, v916239; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v116240; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16241; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v7, v6, vcc_lo16242; GFX12-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v15, v1516243; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v8, 16, v316244; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16245; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo16246; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v616247; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16248; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc_lo16249; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v9, v816250; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v9, 16, v516251; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16252; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v3, v1, vcc_lo16253; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v10, 16, v216254; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v716255; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16256; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc_lo16257; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)16258; GFX12-FAKE16-NEXT:    v_cmp_lt_f32_e32 vcc_lo, v11, v1016259; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16260; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v2, v0, vcc_lo16261; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v116262; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16263; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo16264; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v016265; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16266; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo16267; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v316268; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16269; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo16270; GFX12-FAKE16-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x8000, v216271; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16272; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v0, v0, v2 :: v_dual_lshlrev_b32 v3, 16, v716273; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v916274; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16275; GFX12-FAKE16-NEXT:    v_dual_cndmask_b32 v5, v5, v6 :: v_dual_lshlrev_b32 v2, 16, v816276; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)16277; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v316278; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16279; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo16280; GFX12-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v216281; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)16282; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v5, v0, 0x504010016283; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)16284; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc_lo16285; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v4, v1, 0x504010016286; GFX12-FAKE16-NEXT:    s_setpc_b64 s[30:31]16287  %result = call <4 x bfloat> @llvm.minimumnum.v4bf16(<4 x bfloat> %x, <4 x bfloat> %y)16288  ret <4 x bfloat> %result16289}16290 16291attributes #0 = { "amdgpu-ieee"="false" }16292;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:16293; GFX11: {{.*}}16294; GFX12: {{.*}}16295; GFX9: {{.*}}16296