40 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 %s -o - | FileCheck -check-prefix=GCN %s3 4; The si-mode-register pass is changing the default mode for FP constrained operations.5; It must ignore for strictfp functions.6 7define double @ignoreStrictfp(double noundef %a, double noundef %b) #0 {8; GCN-LABEL: ignoreStrictfp:9; GCN: ; %bb.0:10; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 112; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]13; GCN-NEXT: s_setpc_b64 s[30:31]14 tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 1)15 %val = tail call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #016 ret double %val17}18 19define double @set_fpenv(double noundef %a, double noundef %b) #0 {20; GCN-LABEL: set_fpenv:21; GCN: ; %bb.0: ; %entry22; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 23), 424; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 0, 5), 025; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]26; GCN-NEXT: s_setpc_b64 s[30:31]27entry:28 call void @llvm.set.fpenv.i64(i64 4)29 %val = tail call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #030 ret double %val31}32 33declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)34 35declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)36 37declare void @llvm.set.fpenv.i64(i64)38 39attributes #0 = { strictfp }40