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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s3 4---5name: flat_load_saddr_to_valu6tracksRegLiveness: true7body: |8 ; GCN-LABEL: name: flat_load_saddr_to_valu9 ; GCN: bb.0:10 ; GCN-NEXT: successors: %bb.1(0x80000000)11 ; GCN-NEXT: liveins: $vgpr0_vgpr112 ; GCN-NEXT: {{ $}}13 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr114 ; GCN-NEXT: {{ $}}15 ; GCN-NEXT: bb.1:16 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)17 ; GCN-NEXT: {{ $}}18 ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.119 ; GCN-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr20 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub021 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub122 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec23 ; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec24 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub125 ; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec26 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec27 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc28 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo29 ; GCN-NEXT: {{ $}}30 ; GCN-NEXT: bb.2:31 ; GCN-NEXT: S_ENDPGM 032 bb.0:33 liveins: $vgpr0_vgpr134 %0:sreg_64 = COPY $vgpr0_vgpr135 36 bb.1:37 %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.138 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec39 %4:vgpr_32 = FLAT_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec, implicit $flat_scr40 %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc41 S_CMP_LG_U64 %2, 0, implicit-def $scc42 S_CBRANCH_SCC1 %bb.1, implicit $scc43 44 bb.2:45 S_ENDPGM 046...47 48---49name: flat_load_saddr_to_valu_non_zero_vaddr50tracksRegLiveness: true51body: |52 ; GCN-LABEL: name: flat_load_saddr_to_valu_non_zero_vaddr53 ; GCN: bb.0:54 ; GCN-NEXT: successors: %bb.1(0x80000000)55 ; GCN-NEXT: liveins: $vgpr0_vgpr156 ; GCN-NEXT: {{ $}}57 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr158 ; GCN-NEXT: {{ $}}59 ; GCN-NEXT: bb.1:60 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)61 ; GCN-NEXT: {{ $}}62 ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.163 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec64 ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec65 ; GCN-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec66 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub167 ; GCN-NEXT: [[FLAT_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr68 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub069 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub170 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec71 ; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec72 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub173 ; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec74 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]], implicit $exec75 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc76 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo77 ; GCN-NEXT: {{ $}}78 ; GCN-NEXT: bb.2:79 ; GCN-NEXT: S_ENDPGM 080 bb.0:81 liveins: $vgpr0_vgpr182 %0:sreg_64 = COPY $vgpr0_vgpr183 84 bb.1:85 %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.186 %3:vgpr_32 = V_MOV_B32_e32 1, implicit $exec87 %4:vgpr_32 = FLAT_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec, implicit $flat_scr88 %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc89 S_CMP_LG_U64 %2, 0, implicit-def $scc90 S_CBRANCH_SCC1 %bb.1, implicit $scc91 92 bb.2:93 S_ENDPGM 094...95 96 97---98name: flat_load_saddr_to_valu_undef_vaddr99tracksRegLiveness: true100body: |101 ; GCN-LABEL: name: flat_load_saddr_to_valu_undef_vaddr102 ; GCN: bb.0:103 ; GCN-NEXT: successors: %bb.1(0x80000000)104 ; GCN-NEXT: liveins: $vgpr0_vgpr1105 ; GCN-NEXT: {{ $}}106 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1107 ; GCN-NEXT: {{ $}}108 ; GCN-NEXT: bb.1:109 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)110 ; GCN-NEXT: {{ $}}111 ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1112 ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec113 ; GCN-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec114 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec_xnull = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1115 ; GCN-NEXT: [[FLAT_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr116 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0117 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1118 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec119 ; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec120 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1121 ; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec122 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]], implicit $exec123 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc124 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo125 ; GCN-NEXT: {{ $}}126 ; GCN-NEXT: bb.2:127 ; GCN-NEXT: S_ENDPGM 0128 bb.0:129 liveins: $vgpr0_vgpr1130 %0:sreg_64 = COPY $vgpr0_vgpr1131 132 bb.1:133 %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1134 %4:vgpr_32 = FLAT_LOAD_DWORD_SADDR %1, undef %3:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr135 %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc136 S_CMP_LG_U64 %2, 0, implicit-def $scc137 S_CBRANCH_SCC1 %bb.1, implicit $scc138 139 bb.2:140 S_ENDPGM 0141...142 143---144name: flat_store_saddr_to_valu145tracksRegLiveness: true146body: |147 ; GCN-LABEL: name: flat_store_saddr_to_valu148 ; GCN: bb.0:149 ; GCN-NEXT: successors: %bb.1(0x80000000)150 ; GCN-NEXT: liveins: $vgpr0_vgpr1151 ; GCN-NEXT: {{ $}}152 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1153 ; GCN-NEXT: {{ $}}154 ; GCN-NEXT: bb.1:155 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)156 ; GCN-NEXT: {{ $}}157 ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1158 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF159 ; GCN-NEXT: FLAT_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec, implicit $flat_scr160 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0161 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1162 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec163 ; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec164 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1165 ; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec166 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec167 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc168 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo169 ; GCN-NEXT: {{ $}}170 ; GCN-NEXT: bb.2:171 ; GCN-NEXT: S_ENDPGM 0172 bb.0:173 liveins: $vgpr0_vgpr1174 %0:sreg_64 = COPY $vgpr0_vgpr1175 176 bb.1:177 %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1178 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec179 %4:vgpr_32 = IMPLICIT_DEF180 FLAT_STORE_DWORD_SADDR %3, %4, %1, 0, 0, implicit $exec, implicit $flat_scr181 %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc182 S_CMP_LG_U64 %2, 0, implicit-def $scc183 S_CBRANCH_SCC1 %bb.1, implicit $scc184 185 bb.2:186 S_ENDPGM 0187...188 189---190name: flat_atomic_noret_saddr_to_valu191tracksRegLiveness: true192body: |193 ; GCN-LABEL: name: flat_atomic_noret_saddr_to_valu194 ; GCN: bb.0:195 ; GCN-NEXT: successors: %bb.1(0x80000000)196 ; GCN-NEXT: liveins: $vgpr0_vgpr1197 ; GCN-NEXT: {{ $}}198 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1199 ; GCN-NEXT: {{ $}}200 ; GCN-NEXT: bb.1:201 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)202 ; GCN-NEXT: {{ $}}203 ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %6, %bb.1204 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec205 ; GCN-NEXT: FLAT_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr206 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0207 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1208 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec209 ; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec210 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1211 ; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec212 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec213 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc214 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo215 ; GCN-NEXT: {{ $}}216 ; GCN-NEXT: bb.2:217 ; GCN-NEXT: S_ENDPGM 0218 bb.0:219 liveins: $vgpr0_vgpr1220 %0:sreg_64 = COPY $vgpr0_vgpr1221 222 bb.1:223 %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1224 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec225 FLAT_ATOMIC_ADD_SADDR %3, %3, %1, 0, 0, implicit $exec, implicit $flat_scr226 %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc227 S_CMP_LG_U64 %2, 0, implicit-def $scc228 S_CBRANCH_SCC1 %bb.1, implicit $scc229 230 bb.2:231 S_ENDPGM 0232...233 234---235name: flat_atomic_rtn_saddr_to_valu236tracksRegLiveness: true237body: |238 ; GCN-LABEL: name: flat_atomic_rtn_saddr_to_valu239 ; GCN: bb.0:240 ; GCN-NEXT: successors: %bb.1(0x80000000)241 ; GCN-NEXT: liveins: $vgpr0_vgpr1242 ; GCN-NEXT: {{ $}}243 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1244 ; GCN-NEXT: {{ $}}245 ; GCN-NEXT: bb.1:246 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)247 ; GCN-NEXT: {{ $}}248 ; GCN-NEXT: [[PHI:%[0-9]+]]:vreg_64_align2 = PHI [[COPY]], %bb.0, %7, %bb.1249 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec250 ; GCN-NEXT: [[FLAT_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr251 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0252 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1253 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec254 ; GCN-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec255 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1256 ; GCN-NEXT: [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec257 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]], implicit $exec258 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U64_e64_]], implicit-def $scc259 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo260 ; GCN-NEXT: {{ $}}261 ; GCN-NEXT: bb.2:262 ; GCN-NEXT: S_ENDPGM 0263 bb.0:264 liveins: $vgpr0_vgpr1265 %0:sreg_64 = COPY $vgpr0_vgpr1266 267 bb.1:268 %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1269 %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec270 %4:vgpr_32 = FLAT_ATOMIC_ADD_SADDR_RTN %3, %3, %1, 0, 0, implicit $exec, implicit $flat_scr271 %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc272 S_CMP_LG_U64 %2, 0, implicit-def $scc273 S_CBRANCH_SCC1 %bb.1, implicit $scc274 275 bb.2:276 S_ENDPGM 0277...278 279---280name: scratch_load_saddr_to_valu281tracksRegLiveness: true282body: |283 ; GCN-LABEL: name: scratch_load_saddr_to_valu284 ; GCN: bb.0:285 ; GCN-NEXT: successors: %bb.1(0x80000000)286 ; GCN-NEXT: liveins: $vgpr0287 ; GCN-NEXT: {{ $}}288 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0289 ; GCN-NEXT: {{ $}}290 ; GCN-NEXT: bb.1:291 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)292 ; GCN-NEXT: {{ $}}293 ; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1294 ; GCN-NEXT: [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr295 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec296 ; GCN-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec297 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec298 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U32_e64_]], implicit-def $scc299 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo300 ; GCN-NEXT: {{ $}}301 ; GCN-NEXT: bb.2:302 ; GCN-NEXT: S_ENDPGM 0303 bb.0:304 liveins: $vgpr0305 %0:sgpr_32 = COPY $vgpr0306 307 bb.1:308 %1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1309 %4:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %1, 0, 0, implicit $exec, implicit $flat_scr310 %2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc311 S_CMP_LG_U32 %2, 0, implicit-def $scc312 S_CBRANCH_SCC1 %bb.1, implicit $scc313 314 bb.2:315 S_ENDPGM 0316...317 318---319name: scratch_store_saddr_to_valu320tracksRegLiveness: true321body: |322 ; GCN-LABEL: name: scratch_store_saddr_to_valu323 ; GCN: bb.0:324 ; GCN-NEXT: successors: %bb.1(0x80000000)325 ; GCN-NEXT: liveins: $vgpr0326 ; GCN-NEXT: {{ $}}327 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0328 ; GCN-NEXT: {{ $}}329 ; GCN-NEXT: bb.1:330 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)331 ; GCN-NEXT: {{ $}}332 ; GCN-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1333 ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF334 ; GCN-NEXT: SCRATCH_STORE_DWORD [[DEF]], [[PHI]], 0, 0, implicit $exec, implicit $flat_scr335 ; GCN-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec336 ; GCN-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec337 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec338 ; GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U32_e64_]], implicit-def $scc339 ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc_lo340 ; GCN-NEXT: {{ $}}341 ; GCN-NEXT: bb.2:342 ; GCN-NEXT: S_ENDPGM 0343 bb.0:344 liveins: $vgpr0345 %0:sgpr_32 = COPY $vgpr0346 347 bb.1:348 %1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1349 %4:vgpr_32 = IMPLICIT_DEF350 SCRATCH_STORE_DWORD_SADDR %4, %1, 0, 0, implicit $exec, implicit $flat_scr351 %2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc352 S_CMP_LG_U32 %2, 0, implicit-def $scc353 S_CBRANCH_SCC1 %bb.1, implicit $scc354 355 bb.2:356 S_ENDPGM 0357...358