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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s3; XUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefixes=GCN,VI %s4 5; FIXME: broken on VI because flat instructions need to be emitted6; instead of addr64 equivalent of the _OFFSET variants.7 8; Check that moving the pointer out of the resource descriptor to9; vaddr works for atomics.10 11declare i32 @llvm.amdgcn.workitem.id.x() #112 13define amdgpu_kernel void @atomic_max_i32(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(1) %x, i32 %y) #0 {14; GCN-LABEL: atomic_max_i32:15; GCN: ; %bb.0:16; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x917; GCN-NEXT: s_mov_b32 s11, 0xf00018; GCN-NEXT: s_mov_b32 s10, 019; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v020; GCN-NEXT: v_mov_b32_e32 v2, 021; GCN-NEXT: s_waitcnt lgkmcnt(0)22; GCN-NEXT: s_mov_b64 s[8:9], s[2:3]23; GCN-NEXT: buffer_load_dwordx2 v[1:2], v[1:2], s[8:11], 0 addr64 glc24; GCN-NEXT: s_waitcnt vmcnt(0)25; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v026; GCN-NEXT: s_and_saveexec_b64 s[2:3], vcc27; GCN-NEXT: s_cbranch_execz .LBB0_228; GCN-NEXT: ; %bb.1: ; %atomic29; GCN-NEXT: s_load_dword s2, s[4:5], 0xf30; GCN-NEXT: s_mov_b32 s8, s1031; GCN-NEXT: s_mov_b32 s9, s1032; GCN-NEXT: s_mov_b32 s3, s1133; GCN-NEXT: s_waitcnt lgkmcnt(0)34; GCN-NEXT: v_mov_b32_e32 v0, s235; GCN-NEXT: buffer_atomic_smax v0, v[1:2], s[8:11], 0 addr64 offset:400 glc36; GCN-NEXT: s_mov_b32 s2, -137; GCN-NEXT: s_waitcnt vmcnt(0)38; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 039; GCN-NEXT: .LBB0_2: ; %exit40; GCN-NEXT: s_endpgm41 %tid = call i32 @llvm.amdgcn.workitem.id.x()42 %tid.gep = getelementptr ptr addrspace(1), ptr addrspace(1) %in, i32 %tid43 %ptr = load volatile ptr addrspace(1), ptr addrspace(1) %tid.gep44 %xor = xor i32 %tid, 145 %cmp = icmp ne i32 %xor, 046 br i1 %cmp, label %atomic, label %exit47 48atomic:49 %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 10050 %ret = atomicrmw max ptr addrspace(1) %gep, i32 %y syncscope("workgroup") seq_cst, !amdgpu.no.fine.grained.memory !051 store i32 %ret, ptr addrspace(1) %out52 br label %exit53 54exit:55 ret void56}57 58define amdgpu_kernel void @atomic_max_i32_noret(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(1) %x, i32 %y) #0 {59; GCN-LABEL: atomic_max_i32_noret:60; GCN: ; %bb.0:61; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb62; GCN-NEXT: s_mov_b32 s3, 0xf00063; GCN-NEXT: s_mov_b32 s2, 064; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v065; GCN-NEXT: v_mov_b32_e32 v2, 066; GCN-NEXT: s_waitcnt lgkmcnt(0)67; GCN-NEXT: buffer_load_dwordx2 v[1:2], v[1:2], s[0:3], 0 addr64 glc68; GCN-NEXT: s_waitcnt vmcnt(0)69; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v070; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc71; GCN-NEXT: s_cbranch_execz .LBB1_272; GCN-NEXT: ; %bb.1: ; %atomic73; GCN-NEXT: s_load_dword s4, s[4:5], 0xf74; GCN-NEXT: s_mov_b32 s0, s275; GCN-NEXT: s_mov_b32 s1, s276; GCN-NEXT: s_waitcnt lgkmcnt(0)77; GCN-NEXT: v_mov_b32_e32 v0, s478; GCN-NEXT: buffer_atomic_smax v0, v[1:2], s[0:3], 0 addr64 offset:40079; GCN-NEXT: .LBB1_2: ; %exit80; GCN-NEXT: s_endpgm81 %tid = call i32 @llvm.amdgcn.workitem.id.x()82 %tid.gep = getelementptr ptr addrspace(1), ptr addrspace(1) %in, i32 %tid83 %ptr = load volatile ptr addrspace(1), ptr addrspace(1) %tid.gep84 %xor = xor i32 %tid, 185 %cmp = icmp ne i32 %xor, 086 br i1 %cmp, label %atomic, label %exit87 88atomic:89 %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 10090 %ret = atomicrmw max ptr addrspace(1) %gep, i32 %y syncscope("workgroup") seq_cst, !amdgpu.no.fine.grained.memory !091 br label %exit92 93exit:94 ret void95}96 97attributes #0 = { nounwind }98attributes #1 = { nounwind readnone }99 100!0 = !{}101