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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s3 4define amdgpu_kernel void @lshl1_add(ptr addrspace(1) %in, ptr addrspace(7) %in2) {5; CHECK-LABEL: lshl1_add:6; CHECK: ; %bb.0:7; CHECK-NEXT: s_clause 0x18; CHECK-NEXT: s_load_b64 s[6:7], s[4:5], 0x249; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x4410; CHECK-NEXT: v_mov_b32_e32 v0, 011; CHECK-NEXT: s_load_b32 s5, s[4:5], 0x5412; CHECK-NEXT: s_mov_b32 s4, 013; CHECK-NEXT: s_wait_kmcnt 0x014; CHECK-NEXT: global_load_b32 v1, v0, s[6:7] scope:SCOPE_SYS15; CHECK-NEXT: s_wait_loadcnt 0x016; CHECK-NEXT: s_mov_b32 s6, s317; CHECK-NEXT: s_mov_b32 s7, s418; CHECK-NEXT: s_mov_b32 s3, s419; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], s[4:5]20; CHECK-NEXT: s_mov_b32 s5, s221; CHECK-NEXT: s_mov_b32 s2, s122; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)23; CHECK-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]24; CHECK-NEXT: v_lshl_add_u32 v1, v1, 1, s025; CHECK-NEXT: buffer_store_b16 v0, v1, s[4:7], null offen26; CHECK-NEXT: s_endpgm27 %vaddr = load volatile i32, ptr addrspace(1) %in, align 428 %1 = sext i32 %vaddr to i6429 %gep = getelementptr i16, ptr addrspace(7) %in2, i64 %130 store i16 0, ptr addrspace(7) %gep, align 231 ret void32}33 34define amdgpu_kernel void @lshl2_add(ptr addrspace(1) %in, ptr addrspace(7) %in2) {35; CHECK-LABEL: lshl2_add:36; CHECK: ; %bb.0:37; CHECK-NEXT: s_clause 0x138; CHECK-NEXT: s_load_b64 s[6:7], s[4:5], 0x2439; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x4440; CHECK-NEXT: v_mov_b32_e32 v0, 041; CHECK-NEXT: s_load_b32 s5, s[4:5], 0x5442; CHECK-NEXT: s_mov_b32 s4, 043; CHECK-NEXT: s_wait_kmcnt 0x044; CHECK-NEXT: global_load_b32 v1, v0, s[6:7] scope:SCOPE_SYS45; CHECK-NEXT: s_wait_loadcnt 0x046; CHECK-NEXT: s_mov_b32 s6, s347; CHECK-NEXT: s_mov_b32 s7, s448; CHECK-NEXT: s_mov_b32 s3, s449; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], s[4:5]50; CHECK-NEXT: s_mov_b32 s5, s251; CHECK-NEXT: s_mov_b32 s2, s152; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)53; CHECK-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]54; CHECK-NEXT: v_lshl_add_u32 v1, v1, 2, s055; CHECK-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen56; CHECK-NEXT: s_endpgm57 %vaddr = load volatile i32, ptr addrspace(1) %in, align 458 %1 = sext i32 %vaddr to i6459 %gep = getelementptr i32, ptr addrspace(7) %in2, i64 %160 store i32 0, ptr addrspace(7) %gep, align 461 ret void62}63 64define amdgpu_kernel void @lshl3_add(ptr addrspace(1) %in, ptr addrspace(7) %in2) {65; CHECK-LABEL: lshl3_add:66; CHECK: ; %bb.0:67; CHECK-NEXT: s_clause 0x168; CHECK-NEXT: s_load_b64 s[6:7], s[4:5], 0x2469; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x4470; CHECK-NEXT: v_mov_b32_e32 v0, 071; CHECK-NEXT: s_load_b32 s5, s[4:5], 0x5472; CHECK-NEXT: s_mov_b32 s4, 073; CHECK-NEXT: s_wait_kmcnt 0x074; CHECK-NEXT: global_load_b32 v2, v0, s[6:7] scope:SCOPE_SYS75; CHECK-NEXT: s_wait_loadcnt 0x076; CHECK-NEXT: s_mov_b32 s6, s377; CHECK-NEXT: s_mov_b32 s7, s478; CHECK-NEXT: v_mov_b32_e32 v0, 079; CHECK-NEXT: v_mov_b32_e32 v1, 080; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], s[4:5]81; CHECK-NEXT: s_mov_b32 s5, s282; CHECK-NEXT: s_mov_b32 s2, s183; CHECK-NEXT: s_mov_b32 s3, s484; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)85; CHECK-NEXT: s_or_b64 s[4:5], s[2:3], s[4:5]86; CHECK-NEXT: v_lshl_add_u32 v2, v2, 3, s087; CHECK-NEXT: buffer_store_b64 v[0:1], v2, s[4:7], null offen88; CHECK-NEXT: s_endpgm89 %vaddr = load volatile i32, ptr addrspace(1) %in, align 490 %1 = sext i32 %vaddr to i6491 %gep = getelementptr i64, ptr addrspace(7) %in2, i64 %192 store i64 0, ptr addrspace(7) %gep, align 893 ret void94}95 96define amdgpu_kernel void @lshl4_add(ptr addrspace(1) %in, ptr addrspace(7) %in2) {97; CHECK-LABEL: lshl4_add:98; CHECK: ; %bb.0:99; CHECK-NEXT: s_clause 0x1100; CHECK-NEXT: s_load_b64 s[6:7], s[4:5], 0x24101; CHECK-NEXT: s_load_b128 s[0:3], s[4:5], 0x44102; CHECK-NEXT: v_mov_b32_e32 v0, 0103; CHECK-NEXT: s_load_b32 s5, s[4:5], 0x54104; CHECK-NEXT: s_mov_b32 s4, 0105; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)106; CHECK-NEXT: s_mov_b32 s9, s4107; CHECK-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v2, v0108; CHECK-NEXT: s_wait_kmcnt 0x0109; CHECK-NEXT: global_load_b32 v3, v0, s[6:7] scope:SCOPE_SYS110; CHECK-NEXT: s_wait_loadcnt 0x0111; CHECK-NEXT: s_mov_b32 s7, s4112; CHECK-NEXT: s_mov_b32 s6, s3113; CHECK-NEXT: s_mov_b32 s8, s1114; CHECK-NEXT: s_or_b64 s[6:7], s[6:7], s[4:5]115; CHECK-NEXT: s_mov_b32 s5, s2116; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)117; CHECK-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]118; CHECK-NEXT: v_lshl_add_u32 v4, v3, 4, s0119; CHECK-NEXT: v_mov_b32_e32 v3, v0120; CHECK-NEXT: buffer_store_b128 v[0:3], v4, s[4:7], null offen121; CHECK-NEXT: s_endpgm122 %vaddr = load volatile i32, ptr addrspace(1) %in, align 4123 %1 = sext i32 %vaddr to i64124 %gep = getelementptr i128, ptr addrspace(7) %in2, i64 %1125 store i128 0, ptr addrspace(7) %gep, align 16126 ret void127}128