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1; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN %s2 3; In moveToVALU(), move to vector ALU is performed, all instrs in4; the use chain will be visited. We do not want the same node to be5; pushed to the visit worklist more than once.6 7; GCN-LABEL: {{^}}in_worklist_once:8; GCN: buffer_load_dword9; GCN: BB0_1:10; GCN: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}11; GCN-NEXT: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}12; GCN: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}13; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}14define amdgpu_kernel void @in_worklist_once() #0 {15bb:16 %tmp = load i64, ptr addrspace(5) poison17br label %bb118 19bb1: ; preds = %bb1, %bb20 %tmp2 = phi i64 [ poison, %bb ], [ %tmp16, %bb1 ]21 %tmp3 = phi i64 [ %tmp, %bb ], [ poison, %bb1 ]22 %tmp11 = shl i64 %tmp2, 1423 %tmp13 = xor i64 %tmp11, %tmp224 %tmp15 = and i64 %tmp3, %tmp1325 %tmp16 = xor i64 %tmp15, %tmp326br label %bb127}28 29attributes #0 = { nounwind }30