33 lines · plain
1# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass post-RA-sched %s -o - | FileCheck %s2# RUN: llc -mtriple=amdgcn -passes=post-RA-sched %s -o - | FileCheck %s3 4# This tests a situation where a sub-register of a killed super-register operand5# of V_MOVRELS happens to have an undef use later on. This leads to the post RA6# scheduler adding additional implicit operands to the V_MOVRELS, which used7# to fail machine instruction verification.8 9--- |10 11 define amdgpu_vs void @main(i32 %arg) { ret void }12 13...14---15# CHECK-LABEL: name: main16# CHECK-LABEL: bb.0:17# CHECK: V_MOVRELS_B32_e3218# CHECK: V_MAC_F32_e3219 20name: main21tracksRegLiveness: true22body: |23 bb.0:24 $m0 = S_MOV_B32 undef $sgpr025 V_MOVRELD_B32_e32 undef $vgpr2, 0, implicit $m0, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)26 $m0 = S_MOV_B32 undef $sgpr027 $vgpr1 = V_MOVRELS_B32_e32 undef $vgpr1, implicit $m0, implicit $exec, implicit killed $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr828 $vgpr4 = nofpexcept V_MAC_F32_e32 undef $vgpr0, undef $vgpr0, undef $vgpr4, implicit $mode, implicit $exec29 EXP_DONE 15, undef $vgpr0, killed $vgpr1, killed $vgpr4, undef $vgpr0, 0, 0, 12, implicit $exec30 S_ENDPGM 031 32...33