160 lines · plain
1; RUN: llc -mtriple=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s2; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s4 5; Test addressing modes when the scratch base is not a frame index.6 7; GCN-LABEL: {{^}}store_private_offset_i8:8; GCN: buffer_store_byte v{{[0-9]+}}, off, s[12:15], 0 offset:89define amdgpu_kernel void @store_private_offset_i8() #0 {10 store volatile i8 5, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))11 ret void12}13 14; GCN-LABEL: {{^}}store_private_offset_i16:15; GCN: buffer_store_short v{{[0-9]+}}, off, s[12:15], 0 offset:816define amdgpu_kernel void @store_private_offset_i16() #0 {17 store volatile i16 5, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))18 ret void19}20 21; GCN-LABEL: {{^}}store_private_offset_i32:22; GCN: buffer_store_dword v{{[0-9]+}}, off, s[12:15], 0 offset:823define amdgpu_kernel void @store_private_offset_i32() #0 {24 store volatile i32 5, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))25 ret void26}27 28; GCN-LABEL: {{^}}store_private_offset_v2i32:29; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:830define amdgpu_kernel void @store_private_offset_v2i32() #0 {31 store volatile <2 x i32> <i32 5, i32 10>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))32 ret void33}34 35; GCN-LABEL: {{^}}store_private_offset_v4i32:36; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:837define amdgpu_kernel void @store_private_offset_v4i32() #0 {38 store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))39 ret void40}41 42; GCN-LABEL: {{^}}load_private_offset_i8:43; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[12:15], 0 offset:844define amdgpu_kernel void @load_private_offset_i8() #0 {45 %load = load volatile i8, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))46 ret void47}48 49; GCN-LABEL: {{^}}sextload_private_offset_i8:50; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[12:15], 0 offset:851define amdgpu_kernel void @sextload_private_offset_i8(ptr addrspace(1) %out) #0 {52 %load = load volatile i8, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))53 %sextload = sext i8 %load to i3254 store i32 %sextload, ptr addrspace(1) poison55 ret void56}57 58; GCN-LABEL: {{^}}zextload_private_offset_i8:59; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[12:15], 0 offset:860define amdgpu_kernel void @zextload_private_offset_i8(ptr addrspace(1) %out) #0 {61 %load = load volatile i8, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))62 %zextload = zext i8 %load to i3263 store i32 %zextload, ptr addrspace(1) poison64 ret void65}66 67; GCN-LABEL: {{^}}load_private_offset_i16:68; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[12:15], 0 offset:869define amdgpu_kernel void @load_private_offset_i16() #0 {70 %load = load volatile i16, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))71 ret void72}73 74; GCN-LABEL: {{^}}sextload_private_offset_i16:75; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[12:15], 0 offset:876define amdgpu_kernel void @sextload_private_offset_i16(ptr addrspace(1) %out) #0 {77 %load = load volatile i16, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))78 %sextload = sext i16 %load to i3279 store i32 %sextload, ptr addrspace(1) poison80 ret void81}82 83; GCN-LABEL: {{^}}zextload_private_offset_i16:84; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[12:15], 0 offset:885define amdgpu_kernel void @zextload_private_offset_i16(ptr addrspace(1) %out) #0 {86 %load = load volatile i16, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))87 %zextload = zext i16 %load to i3288 store i32 %zextload, ptr addrspace(1) poison89 ret void90}91 92; GCN-LABEL: {{^}}load_private_offset_i32:93; GCN: buffer_load_dword v{{[0-9]+}}, off, s[12:15], 0 offset:894define amdgpu_kernel void @load_private_offset_i32() #0 {95 %load = load volatile i32, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))96 ret void97}98 99; GCN-LABEL: {{^}}load_private_offset_v2i32:100; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:8101define amdgpu_kernel void @load_private_offset_v2i32() #0 {102 %load = load volatile <2 x i32>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))103 ret void104}105 106; GCN-LABEL: {{^}}load_private_offset_v4i32:107; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[12:15], 0 offset:8108define amdgpu_kernel void @load_private_offset_v4i32() #0 {109 %load = load volatile <4 x i32>, ptr addrspace(5) inttoptr (i32 8 to ptr addrspace(5))110 ret void111}112 113; GCN-LABEL: {{^}}store_private_offset_i8_max_offset:114; GCN: buffer_store_byte v{{[0-9]+}}, off, s[12:15], 0 offset:4095115define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 {116 store volatile i8 5, ptr addrspace(5) inttoptr (i32 4095 to ptr addrspace(5))117 ret void118}119 120; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus1:121; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000122; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[12:15], 0 offen{{$}}123define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 {124 store volatile i8 5, ptr addrspace(5) inttoptr (i32 4096 to ptr addrspace(5))125 ret void126}127 128; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus2:129; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000130; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[12:15], 0 offen offset:1{{$}}131define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {132 store volatile i8 5, ptr addrspace(5) inttoptr (i32 4097 to ptr addrspace(5))133 ret void134}135 136; MUBUF used for stack access has bounds checking enabled before gfx9,137; so a possibly negative base index can't be used for the vgpr offset.138 139; GCN-LABEL: {{^}}store_private_unknown_bits_vaddr:140; SICIVI: {{buffer|flat}}_load_dword [[VADDR:v[0-9]+]],141; SICIVI: v_lshlrev_b32_e32 [[ADDR:v[0-9]+]], 2, [[VADDR]]142; SICIVI-NOT [[ADDR]]143; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR]]144; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}145 146; GFX9: global_load_dword [[VADDR:v[0-9]+]],147; GFX9: v_lshl_add_u32 [[ADDR:v[0-9]+]], [[VADDR]], 2, s{{[0-9]+}}148; GFX9-NOT [[ADDR]]149; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen offset:32150define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 {151 %alloca = alloca [16 x i32], align 4, addrspace(5)152 %vaddr = load volatile i32, ptr addrspace(1) poison153 %vaddr.off = add i32 %vaddr, 8154 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %vaddr.off155 store volatile i32 9, ptr addrspace(5) %gep156 ret void157}158 159attributes #0 = { nounwind }160