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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s5; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s6; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s7 8; Signed 24-bit multiply is not supported on pre-Cayman GPUs.9define amdgpu_kernel void @test_smul24_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {10; SI-LABEL: test_smul24_i32:11; SI: ; %bb.0: ; %entry12; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x913; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: s_mov_b64 s[4:5], s[2:3]15; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_bfe_i32 s2, s4, 0x18000017; SI-NEXT: s_bfe_i32 s4, s5, 0x18000018; SI-NEXT: s_mul_i32 s4, s2, s419; SI-NEXT: s_mov_b32 s2, -120; SI-NEXT: v_mov_b32_e32 v0, s421; SI-NEXT: buffer_store_dword v0, off, s[0:3], 022; SI-NEXT: s_endpgm23;24; VI-LABEL: test_smul24_i32:25; VI: ; %bb.0: ; %entry26; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2427; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: s_mov_b64 s[4:5], s[2:3]29; VI-NEXT: s_bfe_i32 s4, s4, 0x18000030; VI-NEXT: s_bfe_i32 s5, s5, 0x18000031; VI-NEXT: s_mul_i32 s4, s4, s532; VI-NEXT: s_mov_b32 s3, 0xf00033; VI-NEXT: s_mov_b32 s2, -134; VI-NEXT: v_mov_b32_e32 v0, s435; VI-NEXT: buffer_store_dword v0, off, s[0:3], 036; VI-NEXT: s_endpgm37;38; GFX9-LABEL: test_smul24_i32:39; GFX9: ; %bb.0: ; %entry40; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2441; GFX9-NEXT: s_waitcnt lgkmcnt(0)42; GFX9-NEXT: s_mov_b64 s[4:5], s[2:3]43; GFX9-NEXT: s_bfe_i32 s4, s4, 0x18000044; GFX9-NEXT: s_bfe_i32 s5, s5, 0x18000045; GFX9-NEXT: s_mul_i32 s4, s4, s546; GFX9-NEXT: s_mov_b32 s3, 0xf00047; GFX9-NEXT: s_mov_b32 s2, -148; GFX9-NEXT: v_mov_b32_e32 v0, s449; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 050; GFX9-NEXT: s_endpgm51;52; EG-LABEL: test_smul24_i32:53; EG: ; %bb.0: ; %entry54; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]55; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 156; EG-NEXT: CF_END57; EG-NEXT: PAD58; EG-NEXT: ALU clause starting at 4:59; EG-NEXT: LSHL T0.W, KC0[2].Z, literal.x,60; EG-NEXT: LSHL * T1.W, KC0[2].W, literal.x,61; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)62; EG-NEXT: ASHR T1.W, PS, literal.x,63; EG-NEXT: ASHR * T0.W, PV.W, literal.x,64; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)65; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,66; EG-NEXT: MULLO_INT * T1.X, PS, PV.W,67; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)68;69; CM-LABEL: test_smul24_i32:70; CM: ; %bb.0: ; %entry71; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]72; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X73; CM-NEXT: CF_END74; CM-NEXT: PAD75; CM-NEXT: ALU clause starting at 4:76; CM-NEXT: LSHL T0.Z, KC0[2].Z, literal.x,77; CM-NEXT: LSHL * T0.W, KC0[2].W, literal.x,78; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)79; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x,80; CM-NEXT: ASHR T1.Z, PV.W, literal.y,81; CM-NEXT: ASHR * T0.W, PV.Z, literal.y,82; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44)83; CM-NEXT: MULLO_INT T1.X, T0.W, T1.Z,84; CM-NEXT: MULLO_INT T1.Y (MASKED), T0.W, T1.Z,85; CM-NEXT: MULLO_INT T1.Z (MASKED), T0.W, T1.Z,86; CM-NEXT: MULLO_INT * T1.W (MASKED), T0.W, T1.Z,87entry:88 %a.shl = shl i32 %a, 889 %a.24 = ashr i32 %a.shl, 890 %b.shl = shl i32 %b, 891 %b.24 = ashr i32 %b.shl, 892 %mul24 = mul i32 %a.24, %b.2493 store i32 %mul24, ptr addrspace(1) %out94 ret void95}96 97define amdgpu_kernel void @test_smulhi24_i64(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {98; SI-LABEL: test_smulhi24_i64:99; SI: ; %bb.0: ; %entry100; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9101; SI-NEXT: s_mov_b32 s7, 0xf000102; SI-NEXT: s_mov_b32 s6, -1103; SI-NEXT: s_waitcnt lgkmcnt(0)104; SI-NEXT: s_mov_b32 s4, s0105; SI-NEXT: s_mov_b32 s5, s1106; SI-NEXT: v_mov_b32_e32 v0, s3107; SI-NEXT: v_mul_hi_i32_i24_e32 v0, s2, v0108; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0109; SI-NEXT: s_endpgm110;111; VI-LABEL: test_smulhi24_i64:112; VI: ; %bb.0: ; %entry113; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24114; VI-NEXT: s_mov_b32 s7, 0xf000115; VI-NEXT: s_mov_b32 s6, -1116; VI-NEXT: s_waitcnt lgkmcnt(0)117; VI-NEXT: v_mov_b32_e32 v0, s3118; VI-NEXT: s_mov_b32 s4, s0119; VI-NEXT: s_mov_b32 s5, s1120; VI-NEXT: v_mul_hi_i32_i24_e32 v0, s2, v0121; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0122; VI-NEXT: s_endpgm123;124; GFX9-LABEL: test_smulhi24_i64:125; GFX9: ; %bb.0: ; %entry126; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24127; GFX9-NEXT: s_waitcnt lgkmcnt(0)128; GFX9-NEXT: s_mov_b64 s[4:5], s[2:3]129; GFX9-NEXT: s_bfe_i32 s4, s4, 0x180000130; GFX9-NEXT: s_bfe_i32 s5, s5, 0x180000131; GFX9-NEXT: s_mul_hi_i32 s4, s4, s5132; GFX9-NEXT: s_mov_b32 s3, 0xf000133; GFX9-NEXT: s_mov_b32 s2, -1134; GFX9-NEXT: v_mov_b32_e32 v0, s4135; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0136; GFX9-NEXT: s_endpgm137;138; EG-LABEL: test_smulhi24_i64:139; EG: ; %bb.0: ; %entry140; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]141; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1142; EG-NEXT: CF_END143; EG-NEXT: PAD144; EG-NEXT: ALU clause starting at 4:145; EG-NEXT: LSHL T0.W, KC0[2].Z, literal.x,146; EG-NEXT: LSHL * T1.W, KC0[2].W, literal.x,147; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)148; EG-NEXT: ASHR T1.W, PS, literal.x,149; EG-NEXT: ASHR * T0.W, PV.W, literal.x,150; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)151; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,152; EG-NEXT: MULHI_INT * T1.X, PS, PV.W,153; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)154;155; CM-LABEL: test_smulhi24_i64:156; CM: ; %bb.0: ; %entry157; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]158; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X159; CM-NEXT: CF_END160; CM-NEXT: PAD161; CM-NEXT: ALU clause starting at 4:162; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,163; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)164; CM-NEXT: MULHI_INT24 T1.X, KC0[2].Z, KC0[2].W,165; CM-NEXT: MULHI_INT24 T1.Y (MASKED), KC0[2].Z, KC0[2].W,166; CM-NEXT: MULHI_INT24 T1.Z (MASKED), KC0[2].Z, KC0[2].W,167; CM-NEXT: MULHI_INT24 * T1.W (MASKED), KC0[2].Z, KC0[2].W,168entry:169 %a.shl = shl i32 %a, 8170 %a.24 = ashr i32 %a.shl, 8171 %b.shl = shl i32 %b, 8172 %b.24 = ashr i32 %b.shl, 8173 %a.24.i64 = sext i32 %a.24 to i64174 %b.24.i64 = sext i32 %b.24 to i64175 %mul48 = mul i64 %a.24.i64, %b.24.i64176 %mul48.hi = lshr i64 %mul48, 32177 %mul24hi = trunc i64 %mul48.hi to i32178 store i32 %mul24hi, ptr addrspace(1) %out179 ret void180}181 182define i64 @test_smul48_i64(i64 %lhs, i64 %rhs) {183; SI-LABEL: test_smul48_i64:184; SI: ; %bb.0:185; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)186; SI-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v2187; SI-NEXT: v_mul_i32_i24_e32 v0, v0, v2188; SI-NEXT: s_setpc_b64 s[30:31]189;190; VI-LABEL: test_smul48_i64:191; VI: ; %bb.0:192; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; VI-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v2194; VI-NEXT: v_mul_i32_i24_e32 v0, v0, v2195; VI-NEXT: s_setpc_b64 s[30:31]196;197; GFX9-LABEL: test_smul48_i64:198; GFX9: ; %bb.0:199; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)200; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v2201; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v2202; GFX9-NEXT: s_setpc_b64 s[30:31]203;204; EG-LABEL: test_smul48_i64:205; EG: ; %bb.0:206; EG-NEXT: CF_END207; EG-NEXT: PAD208;209; CM-LABEL: test_smul48_i64:210; CM: ; %bb.0:211; CM-NEXT: CF_END212; CM-NEXT: PAD213 %shl.lhs = shl i64 %lhs, 40214 %lhs24 = ashr i64 %shl.lhs, 40215 %shl.rhs = shl i64 %rhs, 40216 %rhs24 = ashr i64 %shl.rhs, 40217 %mul = mul i64 %lhs24, %rhs24218 ret i64 %mul219}220 221define <2 x i64> @test_smul48_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {222; SI-LABEL: test_smul48_v2i64:223; SI: ; %bb.0:224; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)225; SI-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v4226; SI-NEXT: v_mul_i32_i24_e32 v0, v0, v4227; SI-NEXT: v_mul_hi_i32_i24_e32 v3, v2, v6228; SI-NEXT: v_mul_i32_i24_e32 v2, v2, v6229; SI-NEXT: s_setpc_b64 s[30:31]230;231; VI-LABEL: test_smul48_v2i64:232; VI: ; %bb.0:233; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)234; VI-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v4235; VI-NEXT: v_mul_i32_i24_e32 v0, v0, v4236; VI-NEXT: v_mul_hi_i32_i24_e32 v3, v2, v6237; VI-NEXT: v_mul_i32_i24_e32 v2, v2, v6238; VI-NEXT: s_setpc_b64 s[30:31]239;240; GFX9-LABEL: test_smul48_v2i64:241; GFX9: ; %bb.0:242; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)243; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v4244; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v4245; GFX9-NEXT: v_mul_hi_i32_i24_e32 v3, v2, v6246; GFX9-NEXT: v_mul_i32_i24_e32 v2, v2, v6247; GFX9-NEXT: s_setpc_b64 s[30:31]248;249; EG-LABEL: test_smul48_v2i64:250; EG: ; %bb.0:251; EG-NEXT: CF_END252; EG-NEXT: PAD253;254; CM-LABEL: test_smul48_v2i64:255; CM: ; %bb.0:256; CM-NEXT: CF_END257; CM-NEXT: PAD258 %shl.lhs = shl <2 x i64> %lhs, <i64 40, i64 40>259 %lhs24 = ashr <2 x i64> %shl.lhs, <i64 40, i64 40>260 %shl.rhs = shl <2 x i64> %rhs, <i64 40, i64 40>261 %rhs24 = ashr <2 x i64> %shl.rhs, <i64 40, i64 40>262 %mul = mul <2 x i64> %lhs24, %rhs24263 ret <2 x i64> %mul264}265 266; This requires handling of the original 64-bit mul node to eliminate267; unnecessary extension instructions because after legalization they268; will not be removed by SimplifyDemandedBits because there are269; multiple uses by the separate mul and mulhi.270define amdgpu_kernel void @test_smul24_i64(ptr addrspace(1) %out, [8 x i32], i32 %a, [8 x i32], i32 %b) #0 {271; SI-LABEL: test_smul24_i64:272; SI: ; %bb.0:273; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9274; SI-NEXT: s_load_dword s6, s[4:5], 0x13275; SI-NEXT: s_load_dword s4, s[4:5], 0x1c276; SI-NEXT: s_mov_b32 s3, 0xf000277; SI-NEXT: s_mov_b32 s2, -1278; SI-NEXT: s_waitcnt lgkmcnt(0)279; SI-NEXT: s_bfe_i32 s5, s6, 0x180000280; SI-NEXT: s_bfe_i32 s4, s4, 0x180000281; SI-NEXT: v_mov_b32_e32 v0, s5282; SI-NEXT: s_mul_i32 s5, s4, s5283; SI-NEXT: v_mul_hi_i32_i24_e32 v1, s4, v0284; SI-NEXT: v_mov_b32_e32 v0, s5285; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0286; SI-NEXT: s_endpgm287;288; VI-LABEL: test_smul24_i64:289; VI: ; %bb.0:290; VI-NEXT: s_load_dword s6, s[4:5], 0x4c291; VI-NEXT: s_load_dword s7, s[4:5], 0x70292; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24293; VI-NEXT: s_mov_b32 s3, 0xf000294; VI-NEXT: s_mov_b32 s2, -1295; VI-NEXT: s_waitcnt lgkmcnt(0)296; VI-NEXT: s_bfe_i32 s4, s6, 0x180000297; VI-NEXT: s_bfe_i32 s5, s7, 0x180000298; VI-NEXT: v_mov_b32_e32 v0, s4299; VI-NEXT: v_mul_hi_i32_i24_e32 v1, s5, v0300; VI-NEXT: v_mul_i32_i24_e32 v0, s5, v0301; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0302; VI-NEXT: s_endpgm303;304; GFX9-LABEL: test_smul24_i64:305; GFX9: ; %bb.0:306; GFX9-NEXT: s_load_dword s6, s[4:5], 0x4c307; GFX9-NEXT: s_load_dword s7, s[4:5], 0x70308; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24309; GFX9-NEXT: s_mov_b32 s3, 0xf000310; GFX9-NEXT: s_mov_b32 s2, -1311; GFX9-NEXT: s_waitcnt lgkmcnt(0)312; GFX9-NEXT: s_bfe_i32 s4, s6, 0x180000313; GFX9-NEXT: s_bfe_i32 s5, s7, 0x180000314; GFX9-NEXT: s_mul_hi_i32 s6, s5, s4315; GFX9-NEXT: s_mul_i32 s5, s5, s4316; GFX9-NEXT: v_mov_b32_e32 v0, s5317; GFX9-NEXT: v_mov_b32_e32 v1, s6318; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0319; GFX9-NEXT: s_endpgm320;321; EG-LABEL: test_smul24_i64:322; EG: ; %bb.0:323; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]324; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1325; EG-NEXT: CF_END326; EG-NEXT: PAD327; EG-NEXT: ALU clause starting at 4:328; EG-NEXT: LSHL T0.W, KC0[4].Z, literal.x,329; EG-NEXT: LSHL * T1.W, KC0[6].W, literal.x,330; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)331; EG-NEXT: ASHR T1.W, PS, literal.x,332; EG-NEXT: ASHR * T0.W, PV.W, literal.x,333; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)334; EG-NEXT: MULHI_INT * T0.Y, PV.W, PS,335; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,336; EG-NEXT: MULLO_INT * T0.X, T1.W, T0.W,337; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)338;339; CM-LABEL: test_smul24_i64:340; CM: ; %bb.0:341; CM-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[]342; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X343; CM-NEXT: CF_END344; CM-NEXT: PAD345; CM-NEXT: ALU clause starting at 4:346; CM-NEXT: LSHL T0.Z, KC0[4].Z, literal.x,347; CM-NEXT: LSHL * T0.W, KC0[6].W, literal.x,348; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)349; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x,350; CM-NEXT: ASHR T1.Z, PV.W, literal.y,351; CM-NEXT: ASHR * T0.W, PV.Z, literal.y,352; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44)353; CM-NEXT: MULLO_INT T1.X, T1.Z, T0.W,354; CM-NEXT: MULLO_INT T1.Y (MASKED), T1.Z, T0.W,355; CM-NEXT: MULLO_INT T1.Z (MASKED), T1.Z, T0.W,356; CM-NEXT: MULLO_INT * T1.W (MASKED), T1.Z, T0.W,357; CM-NEXT: MULHI_INT24 T1.X (MASKED), KC0[6].W, KC0[4].Z,358; CM-NEXT: MULHI_INT24 T1.Y, KC0[6].W, KC0[4].Z,359; CM-NEXT: MULHI_INT24 T1.Z (MASKED), KC0[6].W, KC0[4].Z,360; CM-NEXT: MULHI_INT24 * T1.W (MASKED), KC0[6].W, KC0[4].Z,361 %shl.i = shl i32 %a, 8362 %shr.i = ashr i32 %shl.i, 8363 %conv.i = sext i32 %shr.i to i64364 %shl1.i = shl i32 %b, 8365 %shr2.i = ashr i32 %shl1.i, 8366 %conv3.i = sext i32 %shr2.i to i64367 %mul.i = mul i64 %conv3.i, %conv.i368 store i64 %mul.i, ptr addrspace(1) %out369 ret void370}371 372define amdgpu_kernel void @test_smul24_i64_square(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {373; SI-LABEL: test_smul24_i64_square:374; SI: ; %bb.0:375; SI-NEXT: s_load_dword s6, s[4:5], 0xb376; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9377; SI-NEXT: s_mov_b32 s3, 0xf000378; SI-NEXT: s_mov_b32 s2, -1379; SI-NEXT: s_waitcnt lgkmcnt(0)380; SI-NEXT: s_bfe_i32 s4, s6, 0x180000381; SI-NEXT: s_mul_i32 s5, s4, s4382; SI-NEXT: v_mul_hi_i32_i24_e64 v1, s4, s4383; SI-NEXT: v_mov_b32_e32 v0, s5384; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0385; SI-NEXT: s_endpgm386;387; VI-LABEL: test_smul24_i64_square:388; VI: ; %bb.0:389; VI-NEXT: s_load_dword s6, s[4:5], 0x2c390; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24391; VI-NEXT: s_mov_b32 s3, 0xf000392; VI-NEXT: s_mov_b32 s2, -1393; VI-NEXT: s_waitcnt lgkmcnt(0)394; VI-NEXT: s_bfe_i32 s4, s6, 0x180000395; VI-NEXT: v_mul_hi_i32_i24_e64 v1, s4, s4396; VI-NEXT: v_mul_i32_i24_e64 v0, s4, s4397; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0398; VI-NEXT: s_endpgm399;400; GFX9-LABEL: test_smul24_i64_square:401; GFX9: ; %bb.0:402; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c403; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24404; GFX9-NEXT: s_mov_b32 s3, 0xf000405; GFX9-NEXT: s_mov_b32 s2, -1406; GFX9-NEXT: s_waitcnt lgkmcnt(0)407; GFX9-NEXT: s_bfe_i32 s4, s6, 0x180000408; GFX9-NEXT: s_mul_hi_i32 s5, s4, s4409; GFX9-NEXT: s_mul_i32 s4, s4, s4410; GFX9-NEXT: v_mov_b32_e32 v0, s4411; GFX9-NEXT: v_mov_b32_e32 v1, s5412; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0413; GFX9-NEXT: s_endpgm414;415; EG-LABEL: test_smul24_i64_square:416; EG: ; %bb.0:417; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]418; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1419; EG-NEXT: CF_END420; EG-NEXT: PAD421; EG-NEXT: ALU clause starting at 4:422; EG-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,423; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)424; EG-NEXT: ASHR * T0.W, PV.W, literal.x,425; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)426; EG-NEXT: MULHI_INT * T0.Y, PV.W, PV.W,427; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,428; EG-NEXT: MULLO_INT * T0.X, T0.W, T0.W,429; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)430;431; CM-LABEL: test_smul24_i64_square:432; CM: ; %bb.0:433; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]434; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X435; CM-NEXT: CF_END436; CM-NEXT: PAD437; CM-NEXT: ALU clause starting at 4:438; CM-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,439; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)440; CM-NEXT: LSHR T0.X, KC0[2].Y, literal.x,441; CM-NEXT: ASHR * T0.W, PV.W, literal.y,442; CM-NEXT: 2(2.802597e-45), 8(1.121039e-44)443; CM-NEXT: MULLO_INT T1.X, T0.W, T0.W,444; CM-NEXT: MULLO_INT T1.Y (MASKED), T0.W, T0.W,445; CM-NEXT: MULLO_INT T1.Z (MASKED), T0.W, T0.W,446; CM-NEXT: MULLO_INT * T1.W (MASKED), T0.W, T0.W,447; CM-NEXT: MULHI_INT24 T1.X (MASKED), KC0[2].Z, KC0[2].Z,448; CM-NEXT: MULHI_INT24 T1.Y, KC0[2].Z, KC0[2].Z,449; CM-NEXT: MULHI_INT24 T1.Z (MASKED), KC0[2].Z, KC0[2].Z,450; CM-NEXT: MULHI_INT24 * T1.W (MASKED), KC0[2].Z, KC0[2].Z,451 %shl.i = shl i32 %a, 8452 %shr.i = ashr i32 %shl.i, 8453 %conv.i = sext i32 %shr.i to i64454 %mul.i = mul i64 %conv.i, %conv.i455 store i64 %mul.i, ptr addrspace(1) %out456 ret void457}458 459define amdgpu_kernel void @test_smul24_i33(ptr addrspace(1) %out, i33 %a, i33 %b) #0 {460; SI-LABEL: test_smul24_i33:461; SI: ; %bb.0: ; %entry462; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9463; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd464; SI-NEXT: s_waitcnt lgkmcnt(0)465; SI-NEXT: s_mov_b64 s[6:7], s[2:3]466; SI-NEXT: s_mov_b32 s3, 0xf000467; SI-NEXT: s_mov_b32 s2, -1468; SI-NEXT: s_bfe_i32 s4, s4, 0x180000469; SI-NEXT: s_bfe_i32 s5, s6, 0x180000470; SI-NEXT: v_mov_b32_e32 v0, s4471; SI-NEXT: s_mul_i32 s4, s5, s4472; SI-NEXT: v_mul_hi_i32_i24_e32 v1, s5, v0473; SI-NEXT: v_mov_b32_e32 v0, s4474; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], 31475; SI-NEXT: v_ashr_i64 v[0:1], v[0:1], 31476; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0477; SI-NEXT: s_endpgm478;479; VI-LABEL: test_smul24_i33:480; VI: ; %bb.0: ; %entry481; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24482; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34483; VI-NEXT: s_waitcnt lgkmcnt(0)484; VI-NEXT: s_bfe_i32 s2, s2, 0x180000485; VI-NEXT: s_bfe_i32 s3, s4, 0x180000486; VI-NEXT: v_mov_b32_e32 v0, s3487; VI-NEXT: v_mul_hi_i32_i24_e32 v1, s2, v0488; VI-NEXT: v_mul_i32_i24_e32 v0, s2, v0489; VI-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]490; VI-NEXT: s_mov_b32 s3, 0xf000491; VI-NEXT: v_ashrrev_i64 v[0:1], 31, v[0:1]492; VI-NEXT: s_mov_b32 s2, -1493; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0494; VI-NEXT: s_endpgm495;496; GFX9-LABEL: test_smul24_i33:497; GFX9: ; %bb.0: ; %entry498; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c499; GFX9-NEXT: s_load_dword s7, s[4:5], 0x34500; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24501; GFX9-NEXT: s_mov_b32 s3, 0xf000502; GFX9-NEXT: s_mov_b32 s2, -1503; GFX9-NEXT: s_waitcnt lgkmcnt(0)504; GFX9-NEXT: s_bfe_i32 s4, s6, 0x180000505; GFX9-NEXT: s_bfe_i32 s6, s7, 0x180000506; GFX9-NEXT: s_mul_hi_i32 s5, s4, s6507; GFX9-NEXT: s_mul_i32 s4, s4, s6508; GFX9-NEXT: s_lshl_b64 s[4:5], s[4:5], 31509; GFX9-NEXT: s_ashr_i64 s[4:5], s[4:5], 31510; GFX9-NEXT: v_mov_b32_e32 v0, s4511; GFX9-NEXT: v_mov_b32_e32 v1, s5512; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0513; GFX9-NEXT: s_endpgm514;515; EG-LABEL: test_smul24_i33:516; EG: ; %bb.0: ; %entry517; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]518; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T2.X, 1519; EG-NEXT: CF_END520; EG-NEXT: PAD521; EG-NEXT: ALU clause starting at 4:522; EG-NEXT: LSHL T0.W, KC0[2].W, literal.x,523; EG-NEXT: LSHL * T1.W, KC0[3].Y, literal.x,524; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)525; EG-NEXT: ASHR T1.W, PS, literal.x,526; EG-NEXT: ASHR * T0.W, PV.W, literal.x,527; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)528; EG-NEXT: MULHI_INT * T0.X, PS, PV.W,529; EG-NEXT: MULLO_INT * T1.X, T0.W, T1.W,530; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,531; EG-NEXT: BFE_INT * T1.Y, T0.X, 0.0, 1,532; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)533;534; CM-LABEL: test_smul24_i33:535; CM: ; %bb.0: ; %entry536; CM-NEXT: ALU 16, @4, KC0[CB0:0-32], KC1[]537; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T2.X538; CM-NEXT: CF_END539; CM-NEXT: PAD540; CM-NEXT: ALU clause starting at 4:541; CM-NEXT: LSHL T0.Z, KC0[2].W, literal.x,542; CM-NEXT: LSHL * T0.W, KC0[3].Y, literal.x,543; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)544; CM-NEXT: ASHR T1.Z, PV.W, literal.x,545; CM-NEXT: ASHR * T0.W, PV.Z, literal.x,546; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)547; CM-NEXT: MULHI_INT24 T0.X, KC0[2].W, KC0[3].Y,548; CM-NEXT: MULHI_INT24 T0.Y (MASKED), KC0[2].W, KC0[3].Y,549; CM-NEXT: MULHI_INT24 T0.Z (MASKED), KC0[2].W, KC0[3].Y,550; CM-NEXT: MULHI_INT24 * T0.W (MASKED), KC0[2].W, KC0[3].Y,551; CM-NEXT: MULLO_INT T1.X, T0.W, T1.Z,552; CM-NEXT: MULLO_INT T1.Y (MASKED), T0.W, T1.Z,553; CM-NEXT: MULLO_INT T1.Z (MASKED), T0.W, T1.Z,554; CM-NEXT: MULLO_INT * T1.W (MASKED), T0.W, T1.Z,555; CM-NEXT: LSHR T2.X, KC0[2].Y, literal.x,556; CM-NEXT: BFE_INT * T1.Y, T0.X, 0.0, 1,557; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)558entry:559 %a.shl = shl i33 %a, 9560 %a.24 = ashr i33 %a.shl, 9561 %b.shl = shl i33 %b, 9562 %b.24 = ashr i33 %b.shl, 9563 %mul24 = mul i33 %a.24, %b.24564 %ext = sext i33 %mul24 to i64565 store i64 %ext, ptr addrspace(1) %out566 ret void567}568 569define amdgpu_kernel void @test_smulhi24_i33(ptr addrspace(1) %out, i33 %a, i33 %b) {570; SI-LABEL: test_smulhi24_i33:571; SI: ; %bb.0: ; %entry572; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9573; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd574; SI-NEXT: s_waitcnt lgkmcnt(0)575; SI-NEXT: s_mov_b64 s[6:7], s[2:3]576; SI-NEXT: s_mov_b32 s3, 0xf000577; SI-NEXT: s_mov_b32 s2, -1578; SI-NEXT: v_mov_b32_e32 v0, s4579; SI-NEXT: v_mul_hi_i32_i24_e32 v0, s6, v0580; SI-NEXT: v_and_b32_e32 v0, 1, v0581; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0582; SI-NEXT: s_endpgm583;584; VI-LABEL: test_smulhi24_i33:585; VI: ; %bb.0: ; %entry586; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24587; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34588; VI-NEXT: s_waitcnt lgkmcnt(0)589; VI-NEXT: s_mov_b64 s[6:7], s[2:3]590; VI-NEXT: v_mov_b32_e32 v0, s4591; VI-NEXT: v_mul_hi_i32_i24_e32 v0, s6, v0592; VI-NEXT: s_mov_b32 s3, 0xf000593; VI-NEXT: s_mov_b32 s2, -1594; VI-NEXT: v_and_b32_e32 v0, 1, v0595; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0596; VI-NEXT: s_endpgm597;598; GFX9-LABEL: test_smulhi24_i33:599; GFX9: ; %bb.0: ; %entry600; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c601; GFX9-NEXT: s_load_dword s7, s[4:5], 0x34602; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24603; GFX9-NEXT: s_mov_b32 s3, 0xf000604; GFX9-NEXT: s_mov_b32 s2, -1605; GFX9-NEXT: s_waitcnt lgkmcnt(0)606; GFX9-NEXT: s_bfe_i32 s4, s6, 0x180000607; GFX9-NEXT: s_bfe_i32 s5, s7, 0x180000608; GFX9-NEXT: s_mul_hi_i32 s4, s4, s5609; GFX9-NEXT: s_and_b32 s4, s4, 1610; GFX9-NEXT: v_mov_b32_e32 v0, s4611; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0612; GFX9-NEXT: s_endpgm613;614; EG-LABEL: test_smulhi24_i33:615; EG: ; %bb.0: ; %entry616; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]617; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1618; EG-NEXT: CF_END619; EG-NEXT: PAD620; EG-NEXT: ALU clause starting at 4:621; EG-NEXT: LSHL T0.W, KC0[2].W, literal.x,622; EG-NEXT: LSHL * T1.W, KC0[3].Y, literal.x,623; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)624; EG-NEXT: ASHR T1.W, PS, literal.x,625; EG-NEXT: ASHR * T0.W, PV.W, literal.x,626; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)627; EG-NEXT: MULHI_INT * T0.X, PS, PV.W,628; EG-NEXT: AND_INT T0.X, PS, 1,629; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,630; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)631;632; CM-LABEL: test_smulhi24_i33:633; CM: ; %bb.0: ; %entry634; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]635; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X636; CM-NEXT: CF_END637; CM-NEXT: PAD638; CM-NEXT: ALU clause starting at 4:639; CM-NEXT: MULHI_INT24 T0.X, KC0[2].W, KC0[3].Y,640; CM-NEXT: MULHI_INT24 T0.Y (MASKED), KC0[2].W, KC0[3].Y,641; CM-NEXT: MULHI_INT24 T0.Z (MASKED), KC0[2].W, KC0[3].Y,642; CM-NEXT: MULHI_INT24 * T0.W (MASKED), KC0[2].W, KC0[3].Y,643; CM-NEXT: AND_INT * T0.X, PV.X, 1,644; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,645; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)646entry:647 %tmp0 = shl i33 %a, 9648 %a_24 = ashr i33 %tmp0, 9649 %tmp1 = shl i33 %b, 9650 %b_24 = ashr i33 %tmp1, 9651 %tmp2 = mul i33 %a_24, %b_24652 %hi = lshr i33 %tmp2, 32653 %trunc = trunc i33 %hi to i32654 655 store i32 %trunc, ptr addrspace(1) %out656 ret void657}658 659define amdgpu_kernel void @simplify_i24_crash(ptr addrspace(1) %out, i32 %arg0, <2 x i32> %arg1, <2 x i32> %arg2) {660; SI-LABEL: simplify_i24_crash:661; SI: ; %bb.0: ; %bb662; SI-NEXT: s_load_dword s0, s[4:5], 0xb663; SI-NEXT: s_waitcnt lgkmcnt(0)664; SI-NEXT: s_cmp_lg_u32 s0, 0665; SI-NEXT: s_cbranch_scc0 .LBB8_2666; SI-NEXT: ; %bb.1: ; %bb7667; SI-NEXT: s_endpgm668; SI-NEXT: .LBB8_2: ; %bb11669; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd670; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9671; SI-NEXT: s_mov_b32 s7, 0xf000672; SI-NEXT: s_waitcnt lgkmcnt(0)673; SI-NEXT: s_bfe_i32 s0, s0, 0x180000674; SI-NEXT: s_bfe_i32 s1, s2, 0x180000675; SI-NEXT: s_mul_i32 s0, s0, s1676; SI-NEXT: s_mov_b32 s6, -1677; SI-NEXT: v_mov_b32_e32 v0, s0678; SI-NEXT: v_mov_b32_e32 v1, s0679; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0680; SI-NEXT: s_endpgm681;682; VI-LABEL: simplify_i24_crash:683; VI: ; %bb.0: ; %bb684; VI-NEXT: s_load_dword s0, s[4:5], 0x2c685; VI-NEXT: s_waitcnt lgkmcnt(0)686; VI-NEXT: s_cmp_lg_u32 s0, 0687; VI-NEXT: s_cbranch_scc0 .LBB8_2688; VI-NEXT: ; %bb.1: ; %bb7689; VI-NEXT: s_endpgm690; VI-NEXT: .LBB8_2: ; %bb11691; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34692; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24693; VI-NEXT: s_mov_b32 s7, 0xf000694; VI-NEXT: s_mov_b32 s6, -1695; VI-NEXT: s_waitcnt lgkmcnt(0)696; VI-NEXT: s_bfe_i32 s0, s0, 0x180000697; VI-NEXT: s_bfe_i32 s1, s2, 0x180000698; VI-NEXT: s_mul_i32 s0, s0, s1699; VI-NEXT: v_mov_b32_e32 v0, s0700; VI-NEXT: v_mov_b32_e32 v1, s0701; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0702; VI-NEXT: s_endpgm703;704; GFX9-LABEL: simplify_i24_crash:705; GFX9: ; %bb.0: ; %bb706; GFX9-NEXT: s_load_dword s0, s[4:5], 0x2c707; GFX9-NEXT: s_waitcnt lgkmcnt(0)708; GFX9-NEXT: s_cmp_lg_u32 s0, 0709; GFX9-NEXT: s_cbranch_scc0 .LBB8_2710; GFX9-NEXT: ; %bb.1: ; %bb7711; GFX9-NEXT: s_endpgm712; GFX9-NEXT: .LBB8_2: ; %bb11713; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34714; GFX9-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x24715; GFX9-NEXT: s_mov_b32 s11, 0xf000716; GFX9-NEXT: s_mov_b32 s10, -1717; GFX9-NEXT: s_waitcnt lgkmcnt(0)718; GFX9-NEXT: s_bfe_i32 s0, s0, 0x180000719; GFX9-NEXT: s_bfe_i32 s1, s2, 0x180000720; GFX9-NEXT: s_mul_i32 s0, s0, s1721; GFX9-NEXT: v_mov_b32_e32 v0, s0722; GFX9-NEXT: v_mov_b32_e32 v1, s0723; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0724; GFX9-NEXT: s_endpgm725;726; EG-LABEL: simplify_i24_crash:727; EG: ; %bb.0: ; %bb728; EG-NEXT: ALU_PUSH_BEFORE 1, @6, KC0[CB0:0-32], KC1[]729; EG-NEXT: JUMP @5 POP:1730; EG-NEXT: ALU 12, @8, KC0[CB0:0-32], KC1[]731; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 0732; EG-NEXT: POP @5 POP:1733; EG-NEXT: CF_END734; EG-NEXT: ALU clause starting at 6:735; EG-NEXT: SETNE_INT * T0.W, KC0[2].Z, 0.0,736; EG-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,737; EG-NEXT: ALU clause starting at 8:738; EG-NEXT: MOV T0.W, KC0[3].Y,739; EG-NEXT: MOV * T1.W, KC0[2].W,740; EG-NEXT: LSHL T1.W, PS, literal.x,741; EG-NEXT: LSHL * T0.W, PV.W, literal.x,742; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)743; EG-NEXT: ASHR T0.W, PS, literal.x,744; EG-NEXT: ASHR * T1.W, PV.W, literal.x,745; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)746; EG-NEXT: MOV T2.W, KC0[2].Y,747; EG-NEXT: MULLO_INT * T0.X, PS, PV.W,748; EG-NEXT: LSHR T1.X, PV.W, literal.x,749; EG-NEXT: MOV * T0.Y, PS,750; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)751;752; CM-LABEL: simplify_i24_crash:753; CM: ; %bb.0: ; %bb754; CM-NEXT: ALU_PUSH_BEFORE 1, @6, KC0[CB0:0-32], KC1[]755; CM-NEXT: JUMP @5 POP:1756; CM-NEXT: ALU 15, @8, KC0[CB0:0-32], KC1[]757; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X758; CM-NEXT: POP @5 POP:1759; CM-NEXT: CF_END760; CM-NEXT: ALU clause starting at 6:761; CM-NEXT: SETNE_INT * T0.W, KC0[2].Z, 0.0,762; CM-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0,763; CM-NEXT: ALU clause starting at 8:764; CM-NEXT: MOV T0.Z, KC0[3].Y,765; CM-NEXT: MOV * T0.W, KC0[2].W,766; CM-NEXT: LSHL T1.Z, PV.W, literal.x,767; CM-NEXT: LSHL * T0.W, PV.Z, literal.x,768; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)769; CM-NEXT: MOV T0.Y, KC0[2].Y,770; CM-NEXT: ASHR T0.Z, PV.W, literal.x,771; CM-NEXT: ASHR * T0.W, PV.Z, literal.x,772; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)773; CM-NEXT: MULLO_INT T0.X, T0.W, T0.Z,774; CM-NEXT: MULLO_INT T0.Y (MASKED), T0.W, T0.Z,775; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, T0.Z,776; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, T0.Z,777; CM-NEXT: LSHR T1.X, T0.Y, literal.x,778; CM-NEXT: MOV * T0.Y, PV.X,779; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)780bb:781 %cmp = icmp eq i32 %arg0, 0782 br i1 %cmp, label %bb11, label %bb7783 784bb11:785 %tmp14 = shufflevector <2 x i32> %arg1, <2 x i32> poison, <2 x i32> zeroinitializer786 %tmp16 = shufflevector <2 x i32> %arg2, <2 x i32> poison, <2 x i32> zeroinitializer787 %tmp17 = shl <2 x i32> %tmp14, <i32 8, i32 8>788 %tmp18 = ashr <2 x i32> %tmp17, <i32 8, i32 8>789 %tmp19 = shl <2 x i32> %tmp16, <i32 8, i32 8>790 %tmp20 = ashr <2 x i32> %tmp19, <i32 8, i32 8>791 %tmp21 = mul <2 x i32> %tmp18, %tmp20792 store <2 x i32> %tmp21, ptr addrspace(1) %out793 br label %bb7794 795bb7:796 ret void797 798}799 800define amdgpu_kernel void @test_umul_i24(ptr addrspace(1) %out, i32 %arg) {801; SI-LABEL: test_umul_i24:802; SI: ; %bb.0:803; SI-NEXT: s_load_dword s2, s[4:5], 0xb804; SI-NEXT: v_mov_b32_e32 v0, 0xff803fe1805; SI-NEXT: s_mov_b64 s[0:1], 0806; SI-NEXT: s_mov_b32 s3, 0xf000807; SI-NEXT: s_waitcnt lgkmcnt(0)808; SI-NEXT: s_lshr_b32 s2, s2, 9809; SI-NEXT: s_mul_i32 s4, s2, 0xff803fe1810; SI-NEXT: v_mul_hi_u32 v1, s2, v0811; SI-NEXT: v_mov_b32_e32 v0, s4812; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 1813; SI-NEXT: s_mov_b32 s2, -1814; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0815; SI-NEXT: s_endpgm816;817; VI-LABEL: test_umul_i24:818; VI: ; %bb.0:819; VI-NEXT: s_load_dword s0, s[4:5], 0x2c820; VI-NEXT: v_mov_b32_e32 v0, 0xff803fe1821; VI-NEXT: s_mov_b32 s3, 0xf000822; VI-NEXT: s_mov_b32 s2, -1823; VI-NEXT: s_waitcnt lgkmcnt(0)824; VI-NEXT: s_lshr_b32 s0, s0, 9825; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s0, v0, 0826; VI-NEXT: s_mov_b64 s[0:1], 0827; VI-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]828; VI-NEXT: s_nop 2829; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0830; VI-NEXT: s_endpgm831;832; GFX9-LABEL: test_umul_i24:833; GFX9: ; %bb.0:834; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c835; GFX9-NEXT: s_mov_b64 s[0:1], 0836; GFX9-NEXT: s_mov_b32 s3, 0xf000837; GFX9-NEXT: s_waitcnt lgkmcnt(0)838; GFX9-NEXT: s_lshr_b32 s2, s2, 9839; GFX9-NEXT: s_mul_hi_u32 s5, s2, 0xff803fe1840; GFX9-NEXT: s_mul_i32 s4, s2, 0xff803fe1841; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1842; GFX9-NEXT: s_mov_b32 s2, -1843; GFX9-NEXT: v_mov_b32_e32 v0, s4844; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0845; GFX9-NEXT: s_endpgm846;847; EG-LABEL: test_umul_i24:848; EG: ; %bb.0:849; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]850; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1851; EG-NEXT: CF_END852; EG-NEXT: PAD853; EG-NEXT: ALU clause starting at 4:854; EG-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,855; EG-NEXT: 9(1.261169e-44), 0(0.000000e+00)856; EG-NEXT: MULHI * T0.X, PV.W, literal.x,857; EG-NEXT: -8372255(nan), 0(0.000000e+00)858; EG-NEXT: MULLO_INT * T0.Y, T0.W, literal.x,859; EG-NEXT: -8372255(nan), 0(0.000000e+00)860; EG-NEXT: BIT_ALIGN_INT T0.X, T0.X, PS, 1,861; EG-NEXT: MOV * T1.X, literal.x,862; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)863;864; CM-LABEL: test_umul_i24:865; CM: ; %bb.0:866; CM-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[]867; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X868; CM-NEXT: CF_END869; CM-NEXT: PAD870; CM-NEXT: ALU clause starting at 4:871; CM-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,872; CM-NEXT: 9(1.261169e-44), 0(0.000000e+00)873; CM-NEXT: MULHI T0.X, T0.W, literal.x,874; CM-NEXT: MULHI T0.Y (MASKED), T0.W, literal.x,875; CM-NEXT: MULHI T0.Z (MASKED), T0.W, literal.x,876; CM-NEXT: MULHI * T0.W (MASKED), T0.W, literal.x,877; CM-NEXT: -8372255(nan), 0(0.000000e+00)878; CM-NEXT: MULLO_INT T0.X (MASKED), T0.W, literal.x,879; CM-NEXT: MULLO_INT T0.Y, T0.W, literal.x,880; CM-NEXT: MULLO_INT T0.Z (MASKED), T0.W, literal.x,881; CM-NEXT: MULLO_INT * T0.W (MASKED), T0.W, literal.x,882; CM-NEXT: -8372255(nan), 0(0.000000e+00)883; CM-NEXT: BIT_ALIGN_INT * T0.X, T0.X, PV.Y, 1,884; CM-NEXT: MOV * T1.X, literal.x,885; CM-NEXT: 0(0.000000e+00), 0(0.000000e+00)886 %i = lshr i32 %arg, 9887 %i1 = zext i32 %i to i64888 %i2 = mul i64 %i1, 4286595041889 %i3 = lshr i64 %i2, 1890 %i4 = trunc i64 %i3 to i32891 store i32 %i4, ptr addrspace(1) null, align 4892 ret void893}894 895attributes #0 = { nounwind }896